GNU Linux-libre 4.4.289-gnu1
[releases.git] / drivers / mfd / intel-lpss.c
1 /*
2  * Intel Sunrisepoint LPSS core support.
3  *
4  * Copyright (C) 2015, Intel Corporation
5  *
6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
8  *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
9  *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/idr.h>
21 #include <linux/ioport.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mfd/core.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
29
30 #include "intel-lpss.h"
31
32 #define LPSS_DEV_OFFSET         0x000
33 #define LPSS_DEV_SIZE           0x200
34 #define LPSS_PRIV_OFFSET        0x200
35 #define LPSS_PRIV_SIZE          0x100
36 #define LPSS_PRIV_REG_COUNT     (LPSS_PRIV_SIZE / 4)
37 #define LPSS_IDMA64_OFFSET      0x800
38 #define LPSS_IDMA64_SIZE        0x800
39
40 /* Offsets from lpss->priv */
41 #define LPSS_PRIV_RESETS                0x04
42 #define LPSS_PRIV_RESETS_FUNC           BIT(2)
43 #define LPSS_PRIV_RESETS_IDMA           0x3
44
45 #define LPSS_PRIV_ACTIVELTR             0x10
46 #define LPSS_PRIV_IDLELTR               0x14
47
48 #define LPSS_PRIV_LTR_REQ               BIT(15)
49 #define LPSS_PRIV_LTR_SCALE_MASK        0xc00
50 #define LPSS_PRIV_LTR_SCALE_1US         0x800
51 #define LPSS_PRIV_LTR_SCALE_32US        0xc00
52 #define LPSS_PRIV_LTR_VALUE_MASK        0x3ff
53
54 #define LPSS_PRIV_SSP_REG               0x20
55 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN   BIT(0)
56
57 #define LPSS_PRIV_REMAP_ADDR            0x40
58
59 #define LPSS_PRIV_CAPS                  0xfc
60 #define LPSS_PRIV_CAPS_NO_IDMA          BIT(8)
61 #define LPSS_PRIV_CAPS_TYPE_SHIFT       4
62 #define LPSS_PRIV_CAPS_TYPE_MASK        (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
63
64 /* This matches the type field in CAPS register */
65 enum intel_lpss_dev_type {
66         LPSS_DEV_I2C = 0,
67         LPSS_DEV_UART,
68         LPSS_DEV_SPI,
69 };
70
71 struct intel_lpss {
72         const struct intel_lpss_platform_info *info;
73         enum intel_lpss_dev_type type;
74         struct clk *clk;
75         struct clk_lookup *clock;
76         const struct mfd_cell *cell;
77         struct device *dev;
78         void __iomem *priv;
79         u32 priv_ctx[LPSS_PRIV_REG_COUNT];
80         int devid;
81         u32 caps;
82         u32 active_ltr;
83         u32 idle_ltr;
84         struct dentry *debugfs;
85 };
86
87 static const struct resource intel_lpss_dev_resources[] = {
88         DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
89         DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
90         DEFINE_RES_IRQ(0),
91 };
92
93 static const struct resource intel_lpss_idma64_resources[] = {
94         DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
95         DEFINE_RES_IRQ(0),
96 };
97
98 #define LPSS_IDMA64_DRIVER_NAME         "idma64"
99
100 /*
101  * Cells needs to be ordered so that the iDMA is created first. This is
102  * because we need to be sure the DMA is available when the host controller
103  * driver is probed.
104  */
105 static const struct mfd_cell intel_lpss_idma64_cell = {
106         .name = LPSS_IDMA64_DRIVER_NAME,
107         .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
108         .resources = intel_lpss_idma64_resources,
109 };
110
111 static const struct mfd_cell intel_lpss_i2c_cell = {
112         .name = "i2c_designware",
113         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
114         .resources = intel_lpss_dev_resources,
115 };
116
117 static const struct mfd_cell intel_lpss_uart_cell = {
118         .name = "dw-apb-uart",
119         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
120         .resources = intel_lpss_dev_resources,
121 };
122
123 static const struct mfd_cell intel_lpss_spi_cell = {
124         .name = "pxa2xx-spi",
125         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
126         .resources = intel_lpss_dev_resources,
127 };
128
129 static DEFINE_IDA(intel_lpss_devid_ida);
130 static struct dentry *intel_lpss_debugfs;
131
132 static int intel_lpss_request_dma_module(const char *name)
133 {
134         static bool intel_lpss_dma_requested;
135
136         if (intel_lpss_dma_requested)
137                 return 0;
138
139         intel_lpss_dma_requested = true;
140         return request_module("%s", name);
141 }
142
143 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
144 {
145         lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
146         lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
147 }
148
149 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
150 {
151         struct dentry *dir;
152
153         dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
154         if (IS_ERR(dir))
155                 return PTR_ERR(dir);
156
157         /* Cache the values into lpss structure */
158         intel_lpss_cache_ltr(lpss);
159
160         debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
161         debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
162         debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
163
164         lpss->debugfs = dir;
165         return 0;
166 }
167
168 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
169 {
170         debugfs_remove_recursive(lpss->debugfs);
171 }
172
173 static void intel_lpss_ltr_set(struct device *dev, s32 val)
174 {
175         struct intel_lpss *lpss = dev_get_drvdata(dev);
176         u32 ltr;
177
178         /*
179          * Program latency tolerance (LTR) accordingly what has been asked
180          * by the PM QoS layer or disable it in case we were passed
181          * negative value or PM_QOS_LATENCY_ANY.
182          */
183         ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
184
185         if (val == PM_QOS_LATENCY_ANY || val < 0) {
186                 ltr &= ~LPSS_PRIV_LTR_REQ;
187         } else {
188                 ltr |= LPSS_PRIV_LTR_REQ;
189                 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
190                 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
191
192                 if (val > LPSS_PRIV_LTR_VALUE_MASK)
193                         ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
194                 else
195                         ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
196         }
197
198         if (ltr == lpss->active_ltr)
199                 return;
200
201         writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
202         writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
203
204         /* Cache the values into lpss structure */
205         intel_lpss_cache_ltr(lpss);
206 }
207
208 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
209 {
210         lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
211         dev_pm_qos_expose_latency_tolerance(lpss->dev);
212 }
213
214 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
215 {
216         dev_pm_qos_hide_latency_tolerance(lpss->dev);
217         lpss->dev->power.set_latency_tolerance = NULL;
218 }
219
220 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
221 {
222         unsigned int type;
223
224         type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
225         type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
226
227         switch (type) {
228         case LPSS_DEV_I2C:
229                 lpss->cell = &intel_lpss_i2c_cell;
230                 break;
231         case LPSS_DEV_UART:
232                 lpss->cell = &intel_lpss_uart_cell;
233                 break;
234         case LPSS_DEV_SPI:
235                 lpss->cell = &intel_lpss_spi_cell;
236                 break;
237         default:
238                 return -ENODEV;
239         }
240
241         lpss->type = type;
242
243         return 0;
244 }
245
246 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
247 {
248         return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
249 }
250
251 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
252 {
253         resource_size_t addr = lpss->info->mem->start;
254
255         lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
256 }
257
258 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
259 {
260         u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
261
262         /* Bring out the device from reset */
263         writel(value, lpss->priv + LPSS_PRIV_RESETS);
264 }
265
266 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
267 {
268         u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
269
270         /* Set the device in reset state */
271         writel(0, lpss->priv + LPSS_PRIV_RESETS);
272
273         intel_lpss_deassert_reset(lpss);
274
275         intel_lpss_set_remap_addr(lpss);
276
277         if (!intel_lpss_has_idma(lpss))
278                 return;
279
280         /* Make sure that SPI multiblock DMA transfers are re-enabled */
281         if (lpss->type == LPSS_DEV_SPI)
282                 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
283 }
284
285 static void intel_lpss_unregister_clock_tree(struct clk *clk)
286 {
287         struct clk *parent;
288
289         while (clk) {
290                 parent = clk_get_parent(clk);
291                 clk_unregister(clk);
292                 clk = parent;
293         }
294 }
295
296 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
297                                              const char *devname,
298                                              struct clk **clk)
299 {
300         char name[32];
301         struct clk *tmp = *clk;
302
303         snprintf(name, sizeof(name), "%s-enable", devname);
304         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
305                                 lpss->priv, 0, 0, NULL);
306         if (IS_ERR(tmp))
307                 return PTR_ERR(tmp);
308
309         snprintf(name, sizeof(name), "%s-div", devname);
310         tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
311                                               0, lpss->priv, 1, 15, 16, 15, 0,
312                                               NULL);
313         if (IS_ERR(tmp))
314                 return PTR_ERR(tmp);
315         *clk = tmp;
316
317         snprintf(name, sizeof(name), "%s-update", devname);
318         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
319                                 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
320         if (IS_ERR(tmp))
321                 return PTR_ERR(tmp);
322         *clk = tmp;
323
324         return 0;
325 }
326
327 static int intel_lpss_register_clock(struct intel_lpss *lpss)
328 {
329         const struct mfd_cell *cell = lpss->cell;
330         struct clk *clk;
331         char devname[24];
332         int ret;
333
334         if (!lpss->info->clk_rate)
335                 return 0;
336
337         /* Root clock */
338         clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
339                                       CLK_IS_ROOT, lpss->info->clk_rate);
340         if (IS_ERR(clk))
341                 return PTR_ERR(clk);
342
343         snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
344
345         /*
346          * Support for clock divider only if it has some preset value.
347          * Otherwise we assume that the divider is not used.
348          */
349         if (lpss->type != LPSS_DEV_I2C) {
350                 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
351                 if (ret)
352                         goto err_clk_register;
353         }
354
355         ret = -ENOMEM;
356
357         /* Clock for the host controller */
358         lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
359         if (!lpss->clock)
360                 goto err_clk_register;
361
362         lpss->clk = clk;
363
364         return 0;
365
366 err_clk_register:
367         intel_lpss_unregister_clock_tree(clk);
368
369         return ret;
370 }
371
372 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
373 {
374         if (IS_ERR_OR_NULL(lpss->clk))
375                 return;
376
377         clkdev_drop(lpss->clock);
378         intel_lpss_unregister_clock_tree(lpss->clk);
379 }
380
381 int intel_lpss_probe(struct device *dev,
382                      const struct intel_lpss_platform_info *info)
383 {
384         struct intel_lpss *lpss;
385         int ret;
386
387         if (!info || !info->mem || info->irq <= 0)
388                 return -EINVAL;
389
390         lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
391         if (!lpss)
392                 return -ENOMEM;
393
394         lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
395                                   LPSS_PRIV_SIZE);
396         if (!lpss->priv)
397                 return -ENOMEM;
398
399         lpss->info = info;
400         lpss->dev = dev;
401         lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
402
403         dev_set_drvdata(dev, lpss);
404
405         ret = intel_lpss_assign_devs(lpss);
406         if (ret)
407                 return ret;
408
409         intel_lpss_init_dev(lpss);
410
411         lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
412         if (lpss->devid < 0)
413                 return lpss->devid;
414
415         ret = intel_lpss_register_clock(lpss);
416         if (ret)
417                 goto err_clk_register;
418
419         intel_lpss_ltr_expose(lpss);
420
421         ret = intel_lpss_debugfs_add(lpss);
422         if (ret)
423                 dev_warn(dev, "Failed to create debugfs entries\n");
424
425         if (intel_lpss_has_idma(lpss)) {
426                 /*
427                  * Ensure the DMA driver is loaded before the host
428                  * controller device appears, so that the host controller
429                  * driver can request its DMA channels as early as
430                  * possible.
431                  *
432                  * If the DMA module is not there that's OK as well.
433                  */
434                 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
435
436                 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
437                                       1, info->mem, info->irq, NULL);
438                 if (ret)
439                         dev_warn(dev, "Failed to add %s, fallback to PIO\n",
440                                  LPSS_IDMA64_DRIVER_NAME);
441         }
442
443         ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
444                               1, info->mem, info->irq, NULL);
445         if (ret)
446                 goto err_remove_ltr;
447
448         return 0;
449
450 err_remove_ltr:
451         intel_lpss_debugfs_remove(lpss);
452         intel_lpss_ltr_hide(lpss);
453         intel_lpss_unregister_clock(lpss);
454
455 err_clk_register:
456         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
457
458         return ret;
459 }
460 EXPORT_SYMBOL_GPL(intel_lpss_probe);
461
462 void intel_lpss_remove(struct device *dev)
463 {
464         struct intel_lpss *lpss = dev_get_drvdata(dev);
465
466         mfd_remove_devices(dev);
467         intel_lpss_debugfs_remove(lpss);
468         intel_lpss_ltr_hide(lpss);
469         intel_lpss_unregister_clock(lpss);
470         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
471 }
472 EXPORT_SYMBOL_GPL(intel_lpss_remove);
473
474 static int resume_lpss_device(struct device *dev, void *data)
475 {
476         pm_runtime_resume(dev);
477         return 0;
478 }
479
480 int intel_lpss_prepare(struct device *dev)
481 {
482         /*
483          * Resume both child devices before entering system sleep. This
484          * ensures that they are in proper state before they get suspended.
485          */
486         device_for_each_child_reverse(dev, NULL, resume_lpss_device);
487         return 0;
488 }
489 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
490
491 int intel_lpss_suspend(struct device *dev)
492 {
493         struct intel_lpss *lpss = dev_get_drvdata(dev);
494         unsigned int i;
495
496         /* Save device context */
497         for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
498                 lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
499
500         return 0;
501 }
502 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
503
504 int intel_lpss_resume(struct device *dev)
505 {
506         struct intel_lpss *lpss = dev_get_drvdata(dev);
507         unsigned int i;
508
509         intel_lpss_deassert_reset(lpss);
510
511         /* Restore device context */
512         for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
513                 writel(lpss->priv_ctx[i], lpss->priv + i * 4);
514
515         return 0;
516 }
517 EXPORT_SYMBOL_GPL(intel_lpss_resume);
518
519 static int __init intel_lpss_init(void)
520 {
521         intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
522         return 0;
523 }
524 module_init(intel_lpss_init);
525
526 static void __exit intel_lpss_exit(void)
527 {
528         ida_destroy(&intel_lpss_devid_ida);
529         debugfs_remove(intel_lpss_debugfs);
530 }
531 module_exit(intel_lpss_exit);
532
533 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
534 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
535 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
536 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
537 MODULE_DESCRIPTION("Intel LPSS core driver");
538 MODULE_LICENSE("GPL v2");