drivers/mfd/exynos-lpass.c

   1 /*
   2  * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
   3  *
   4  * Authors: Inha Song <ideal.song@samsung.com>
   5  *          Sylwester Nawrocki <s.nawrocki@samsung.com>
   6  *
   7  * Samsung Exynos SoC series Low Power Audio Subsystem driver.
   8  *
   9  * This module provides regmap for the Top SFR region and instantiates
  10  * devices for IP blocks like DMAC, I2S, UART.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 and
  14  * only version 2 as published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <linux/mfd/syscon/exynos5-pmu.h>
  22 #include <linux/of.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/types.h>
  27
  28 /* LPASS Top register definitions */
  29 #define SFR_LPASS_CORE_SW_RESET         0x08
  30 #define  LPASS_SB_SW_RESET              BIT(11)
  31 #define  LPASS_UART_SW_RESET            BIT(10)
  32 #define  LPASS_PCM_SW_RESET             BIT(9)
  33 #define  LPASS_I2S_SW_RESET             BIT(8)
  34 #define  LPASS_WDT1_SW_RESET            BIT(4)
  35 #define  LPASS_WDT0_SW_RESET            BIT(3)
  36 #define  LPASS_TIMER_SW_RESET           BIT(2)
  37 #define  LPASS_MEM_SW_RESET             BIT(1)
  38 #define  LPASS_DMA_SW_RESET             BIT(0)
  39
  40 #define SFR_LPASS_INTR_CA5_MASK         0x48
  41 #define SFR_LPASS_INTR_CPU_MASK         0x58
  42 #define  LPASS_INTR_APM                 BIT(9)
  43 #define  LPASS_INTR_MIF                 BIT(8)
  44 #define  LPASS_INTR_TIMER               BIT(7)
  45 #define  LPASS_INTR_DMA                 BIT(6)
  46 #define  LPASS_INTR_GPIO                BIT(5)
  47 #define  LPASS_INTR_I2S                 BIT(4)
  48 #define  LPASS_INTR_PCM                 BIT(3)
  49 #define  LPASS_INTR_SLIMBUS             BIT(2)
  50 #define  LPASS_INTR_UART                BIT(1)
  51 #define  LPASS_INTR_SFR                 BIT(0)
  52
  53 struct exynos_lpass {
  54         /* pointer to the Power Management Unit regmap */
  55         struct regmap *pmu;
  56         /* pointer to the LPASS TOP regmap */
  57         struct regmap *top;
  58 };
  59
  60 static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
  61 {
  62         unsigned int val = 0;
  63
  64         regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
  65
  66         val &= ~mask;
  67         regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
  68
  69         usleep_range(100, 150);
  70
  71         val |= mask;
  72         regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
  73 }
  74
  75 static void exynos_lpass_enable(struct exynos_lpass *lpass)
  76 {
  77         /* Unmask SFR, DMA and I2S interrupt */
  78         regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
  79                      LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
  80
  81         regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
  82                      LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
  83
  84         /* Activate related PADs from retention state */
  85         regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
  86                      EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
  87
  88         exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
  89         exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
  90         exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
  91 }
  92
  93 static void exynos_lpass_disable(struct exynos_lpass *lpass)
  94 {
  95         /* Mask any unmasked IP interrupt sources */
  96         regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
  97         regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
  98
  99         /* Deactivate related PADs from retention state */
 100         regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
 101 }
 102
 103 static const struct regmap_config exynos_lpass_reg_conf = {
 104         .reg_bits       = 32,
 105         .reg_stride     = 4,
 106         .val_bits       = 32,
 107         .max_register   = 0xfc,
 108         .fast_io        = true,
 109 };
 110
 111 static int exynos_lpass_probe(struct platform_device *pdev)
 112 {
 113         struct device *dev = &pdev->dev;
 114         struct exynos_lpass *lpass;
 115         void __iomem *base_top;
 116         struct resource *res;
 117
 118         lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
 119         if (!lpass)
 120                 return -ENOMEM;
 121
 122         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 123         base_top = devm_ioremap_resource(dev, res);
 124         if (IS_ERR(base_top))
 125                 return PTR_ERR(base_top);
 126
 127         lpass->top = regmap_init_mmio(dev, base_top,
 128                                         &exynos_lpass_reg_conf);
 129         if (IS_ERR(lpass->top)) {
 130                 dev_err(dev, "LPASS top regmap initialization failed\n");
 131                 return PTR_ERR(lpass->top);
 132         }
 133
 134         lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
 135                                                 "samsung,pmu-syscon");
 136         if (IS_ERR(lpass->pmu)) {
 137                 dev_err(dev, "Failed to lookup PMU regmap\n");
 138                 return PTR_ERR(lpass->pmu);
 139         }
 140
 141         platform_set_drvdata(pdev, lpass);
 142         exynos_lpass_enable(lpass);
 143
 144         return of_platform_populate(dev->of_node, NULL, NULL, dev);
 145 }
 146
 147 static int __maybe_unused exynos_lpass_suspend(struct device *dev)
 148 {
 149         struct exynos_lpass *lpass = dev_get_drvdata(dev);
 150
 151         exynos_lpass_disable(lpass);
 152
 153         return 0;
 154 }
 155
 156 static int __maybe_unused exynos_lpass_resume(struct device *dev)
 157 {
 158         struct exynos_lpass *lpass = dev_get_drvdata(dev);
 159
 160         exynos_lpass_enable(lpass);
 161
 162         return 0;
 163 }
 164
 165 static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
 166                                         exynos_lpass_resume);
 167
 168 static const struct of_device_id exynos_lpass_of_match[] = {
 169         { .compatible = "samsung,exynos5433-lpass" },
 170         { },
 171 };
 172 MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
 173
 174 static struct platform_driver exynos_lpass_driver = {
 175         .driver = {
 176                 .name           = "exynos-lpass",
 177                 .pm             = &lpass_pm_ops,
 178                 .of_match_table = exynos_lpass_of_match,
 179         },
 180         .probe  = exynos_lpass_probe,
 181 };
 182 module_platform_driver(exynos_lpass_driver);
 183
 184 MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
 185 MODULE_LICENSE("GPL v2");