1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
6 #include <dt-bindings/memory/tegra210-mc.h>
10 static const struct tegra_mc_client tegra210_mc_clients[] = {
14 .swgroup = TEGRA_SWGROUP_PTC,
18 .swgroup = TEGRA_SWGROUP_DC,
34 .swgroup = TEGRA_SWGROUP_DCB,
50 .swgroup = TEGRA_SWGROUP_DC,
66 .swgroup = TEGRA_SWGROUP_DCB,
82 .swgroup = TEGRA_SWGROUP_DC,
98 .swgroup = TEGRA_SWGROUP_DCB,
114 .swgroup = TEGRA_SWGROUP_AFI,
130 .swgroup = TEGRA_SWGROUP_AVPC,
146 .swgroup = TEGRA_SWGROUP_DC,
161 .name = "displayhcb",
162 .swgroup = TEGRA_SWGROUP_DCB,
178 .swgroup = TEGRA_SWGROUP_HDA,
193 .name = "host1xdmar",
194 .swgroup = TEGRA_SWGROUP_HC,
210 .swgroup = TEGRA_SWGROUP_HC,
226 .swgroup = TEGRA_SWGROUP_NVENC,
241 .name = "ppcsahbdmar",
242 .swgroup = TEGRA_SWGROUP_PPCS,
257 .name = "ppcsahbslvr",
258 .swgroup = TEGRA_SWGROUP_PPCS,
274 .swgroup = TEGRA_SWGROUP_SATA,
290 .swgroup = TEGRA_SWGROUP_MPCORE,
302 .swgroup = TEGRA_SWGROUP_NVENC,
318 .swgroup = TEGRA_SWGROUP_AFI,
334 .swgroup = TEGRA_SWGROUP_AVPC,
350 .swgroup = TEGRA_SWGROUP_HDA,
366 .swgroup = TEGRA_SWGROUP_HC,
382 .swgroup = TEGRA_SWGROUP_MPCORE,
393 .name = "ppcsahbdmaw",
394 .swgroup = TEGRA_SWGROUP_PPCS,
409 .name = "ppcsahbslvw",
410 .swgroup = TEGRA_SWGROUP_PPCS,
426 .swgroup = TEGRA_SWGROUP_SATA,
442 .swgroup = TEGRA_SWGROUP_ISP2,
458 .swgroup = TEGRA_SWGROUP_ISP2,
474 .swgroup = TEGRA_SWGROUP_ISP2,
489 .name = "xusb_hostr",
490 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
505 .name = "xusb_hostw",
506 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
522 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
538 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
554 .swgroup = TEGRA_SWGROUP_ISP2B,
570 .swgroup = TEGRA_SWGROUP_ISP2B,
586 .swgroup = TEGRA_SWGROUP_ISP2B,
602 .swgroup = TEGRA_SWGROUP_TSEC,
618 .swgroup = TEGRA_SWGROUP_TSEC,
634 .swgroup = TEGRA_SWGROUP_A9AVP,
650 .swgroup = TEGRA_SWGROUP_A9AVP,
666 .swgroup = TEGRA_SWGROUP_GPU,
683 .swgroup = TEGRA_SWGROUP_GPU,
700 .swgroup = TEGRA_SWGROUP_DC,
716 .swgroup = TEGRA_SWGROUP_SDMMC1A,
732 .swgroup = TEGRA_SWGROUP_SDMMC2A,
748 .swgroup = TEGRA_SWGROUP_SDMMC3A,
763 .swgroup = TEGRA_SWGROUP_SDMMC4A,
780 .swgroup = TEGRA_SWGROUP_SDMMC1A,
796 .swgroup = TEGRA_SWGROUP_SDMMC2A,
812 .swgroup = TEGRA_SWGROUP_SDMMC3A,
828 .swgroup = TEGRA_SWGROUP_SDMMC4A,
844 .swgroup = TEGRA_SWGROUP_VIC,
860 .swgroup = TEGRA_SWGROUP_VIC,
876 .swgroup = TEGRA_SWGROUP_VI,
892 .swgroup = TEGRA_SWGROUP_DC,
908 .swgroup = TEGRA_SWGROUP_NVDEC,
924 .swgroup = TEGRA_SWGROUP_NVDEC,
940 .swgroup = TEGRA_SWGROUP_APE,
956 .swgroup = TEGRA_SWGROUP_APE,
972 .swgroup = TEGRA_SWGROUP_NVJPG,
988 .swgroup = TEGRA_SWGROUP_NVJPG,
1004 .swgroup = TEGRA_SWGROUP_SE,
1020 .swgroup = TEGRA_SWGROUP_SE,
1036 .swgroup = TEGRA_SWGROUP_AXIAP,
1052 .swgroup = TEGRA_SWGROUP_AXIAP,
1068 .swgroup = TEGRA_SWGROUP_ETR,
1084 .swgroup = TEGRA_SWGROUP_ETR,
1100 .swgroup = TEGRA_SWGROUP_TSECB,
1116 .swgroup = TEGRA_SWGROUP_TSECB,
1132 .swgroup = TEGRA_SWGROUP_GPU,
1149 .swgroup = TEGRA_SWGROUP_GPU,
1166 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1167 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1168 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1169 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1170 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1171 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1172 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1173 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1174 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1175 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1176 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
1177 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1178 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1179 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1180 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1181 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1182 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1183 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1184 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1185 { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
1186 { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
1187 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1188 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1189 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1190 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1191 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1192 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1193 { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
1194 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1195 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1196 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1197 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1198 { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
1199 { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
1200 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1201 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1202 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1203 { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
1204 { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
1205 { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },
1208 static const unsigned int tegra210_group_display[] = {
1213 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1216 .swgroups = tegra210_group_display,
1217 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1221 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1222 .clients = tegra210_mc_clients,
1223 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1224 .swgroups = tegra210_swgroups,
1225 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1226 .groups = tegra210_groups,
1227 .num_groups = ARRAY_SIZE(tegra210_groups),
1228 .supports_round_robin_arbitration = true,
1229 .supports_request_limit = true,
1230 .num_tlb_lines = 48,
1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
1237 .id = TEGRA210_MC_RESET_##_name, \
1238 .control = _control, \
1239 .status = _status, \
1243 static const struct tegra_mc_reset tegra210_mc_resets[] = {
1244 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1245 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1246 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1247 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1248 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1249 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1250 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1251 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1252 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1253 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1254 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1255 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1256 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1257 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1258 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1259 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1260 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1261 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1262 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1263 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1264 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1265 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1266 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1267 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1268 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1269 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1270 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1271 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1272 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1273 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1276 const struct tegra_mc_soc tegra210_mc_soc = {
1277 .clients = tegra210_mc_clients,
1278 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1279 .num_address_bits = 34,
1281 .client_id_mask = 0xff,
1282 .smmu = &tegra210_smmu_soc,
1283 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1284 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1285 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1286 .reset_ops = &tegra_mc_reset_ops_common,
1287 .resets = tegra210_mc_resets,
1288 .num_resets = ARRAY_SIZE(tegra210_mc_resets),
1289 .ops = &tegra30_mc_ops,