1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
6 #include <dt-bindings/memory/tegra210-mc.h>
10 static const struct tegra_mc_client tegra210_mc_clients[] = {
14 .swgroup = TEGRA_SWGROUP_PTC,
18 .swgroup = TEGRA_SWGROUP_DC,
32 .swgroup = TEGRA_SWGROUP_DCB,
46 .swgroup = TEGRA_SWGROUP_DC,
60 .swgroup = TEGRA_SWGROUP_DCB,
74 .swgroup = TEGRA_SWGROUP_DC,
88 .swgroup = TEGRA_SWGROUP_DCB,
102 .swgroup = TEGRA_SWGROUP_AFI,
116 .swgroup = TEGRA_SWGROUP_AVPC,
130 .swgroup = TEGRA_SWGROUP_DC,
143 .name = "displayhcb",
144 .swgroup = TEGRA_SWGROUP_DCB,
158 .swgroup = TEGRA_SWGROUP_HDA,
171 .name = "host1xdmar",
172 .swgroup = TEGRA_SWGROUP_HC,
186 .swgroup = TEGRA_SWGROUP_HC,
200 .swgroup = TEGRA_SWGROUP_NVENC,
213 .name = "ppcsahbdmar",
214 .swgroup = TEGRA_SWGROUP_PPCS,
227 .name = "ppcsahbslvr",
228 .swgroup = TEGRA_SWGROUP_PPCS,
242 .swgroup = TEGRA_SWGROUP_SATA,
256 .swgroup = TEGRA_SWGROUP_MPCORE,
266 .swgroup = TEGRA_SWGROUP_NVENC,
280 .swgroup = TEGRA_SWGROUP_AFI,
294 .swgroup = TEGRA_SWGROUP_AVPC,
308 .swgroup = TEGRA_SWGROUP_HDA,
322 .swgroup = TEGRA_SWGROUP_HC,
336 .swgroup = TEGRA_SWGROUP_MPCORE,
345 .name = "ppcsahbdmaw",
346 .swgroup = TEGRA_SWGROUP_PPCS,
359 .name = "ppcsahbslvw",
360 .swgroup = TEGRA_SWGROUP_PPCS,
374 .swgroup = TEGRA_SWGROUP_SATA,
388 .swgroup = TEGRA_SWGROUP_ISP2,
402 .swgroup = TEGRA_SWGROUP_ISP2,
416 .swgroup = TEGRA_SWGROUP_ISP2,
429 .name = "xusb_hostr",
430 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
443 .name = "xusb_hostw",
444 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
458 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
472 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
486 .swgroup = TEGRA_SWGROUP_ISP2B,
500 .swgroup = TEGRA_SWGROUP_ISP2B,
514 .swgroup = TEGRA_SWGROUP_ISP2B,
528 .swgroup = TEGRA_SWGROUP_TSEC,
542 .swgroup = TEGRA_SWGROUP_TSEC,
556 .swgroup = TEGRA_SWGROUP_A9AVP,
570 .swgroup = TEGRA_SWGROUP_A9AVP,
584 .swgroup = TEGRA_SWGROUP_GPU,
599 .swgroup = TEGRA_SWGROUP_GPU,
614 .swgroup = TEGRA_SWGROUP_DC,
628 .swgroup = TEGRA_SWGROUP_SDMMC1A,
642 .swgroup = TEGRA_SWGROUP_SDMMC2A,
656 .swgroup = TEGRA_SWGROUP_SDMMC3A,
669 .swgroup = TEGRA_SWGROUP_SDMMC4A,
684 .swgroup = TEGRA_SWGROUP_SDMMC1A,
698 .swgroup = TEGRA_SWGROUP_SDMMC2A,
712 .swgroup = TEGRA_SWGROUP_SDMMC3A,
726 .swgroup = TEGRA_SWGROUP_SDMMC4A,
740 .swgroup = TEGRA_SWGROUP_VIC,
754 .swgroup = TEGRA_SWGROUP_VIC,
768 .swgroup = TEGRA_SWGROUP_VI,
782 .swgroup = TEGRA_SWGROUP_DC,
796 .swgroup = TEGRA_SWGROUP_NVDEC,
810 .swgroup = TEGRA_SWGROUP_NVDEC,
824 .swgroup = TEGRA_SWGROUP_APE,
838 .swgroup = TEGRA_SWGROUP_APE,
852 .swgroup = TEGRA_SWGROUP_NVJPG,
866 .swgroup = TEGRA_SWGROUP_NVJPG,
880 .swgroup = TEGRA_SWGROUP_SE,
894 .swgroup = TEGRA_SWGROUP_SE,
908 .swgroup = TEGRA_SWGROUP_AXIAP,
922 .swgroup = TEGRA_SWGROUP_AXIAP,
936 .swgroup = TEGRA_SWGROUP_ETR,
950 .swgroup = TEGRA_SWGROUP_ETR,
964 .swgroup = TEGRA_SWGROUP_TSECB,
978 .swgroup = TEGRA_SWGROUP_TSECB,
992 .swgroup = TEGRA_SWGROUP_GPU,
1007 .swgroup = TEGRA_SWGROUP_GPU,
1022 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1023 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1024 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1025 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1026 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1027 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1028 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1029 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1030 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1031 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1032 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1033 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1034 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1035 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1036 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1037 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1038 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1039 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1040 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1041 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1042 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1043 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1044 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1045 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1046 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1047 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1048 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1049 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1050 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1051 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1054 static const unsigned int tegra210_group_display[] = {
1059 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1062 .swgroups = tegra210_group_display,
1063 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1067 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1068 .clients = tegra210_mc_clients,
1069 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1070 .swgroups = tegra210_swgroups,
1071 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1072 .groups = tegra210_groups,
1073 .num_groups = ARRAY_SIZE(tegra210_groups),
1074 .supports_round_robin_arbitration = true,
1075 .supports_request_limit = true,
1076 .num_tlb_lines = 48,
1080 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
1083 .id = TEGRA210_MC_RESET_##_name, \
1084 .control = _control, \
1085 .status = _status, \
1089 static const struct tegra_mc_reset tegra210_mc_resets[] = {
1090 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1091 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1092 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1093 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1094 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1095 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1096 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1097 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1098 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1099 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1101 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1102 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1103 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1104 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1105 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1106 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1107 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1108 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1109 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1110 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1111 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1112 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1113 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1114 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1115 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1116 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1117 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1118 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1119 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1122 const struct tegra_mc_soc tegra210_mc_soc = {
1123 .clients = tegra210_mc_clients,
1124 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1125 .num_address_bits = 34,
1127 .client_id_mask = 0xff,
1128 .smmu = &tegra210_smmu_soc,
1129 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1130 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1131 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1132 .reset_ops = &tegra_mc_reset_ops_common,
1133 .resets = tegra210_mc_resets,
1134 .num_resets = ARRAY_SIZE(tegra210_mc_resets),