1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
6 #include <dt-bindings/memory/tegra20-mc.h>
10 static const struct tegra_mc_client tegra20_mc_clients[] = {
88 .name = "ppcsahbdmar",
91 .name = "ppcsahbslvr",
154 .name = "ppcsahbdmaw",
157 .name = "ppcsahbslvw",
170 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \
173 .id = TEGRA20_MC_RESET_##_name, \
174 .control = _control, \
180 static const struct tegra_mc_reset tegra20_mc_resets[] = {
181 TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
182 TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
183 TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
184 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
185 TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
186 TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
187 TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
188 TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
189 TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
190 TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9),
191 TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10),
192 TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11),
193 TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12),
194 TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13),
195 TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
198 static int tegra20_mc_hotreset_assert(struct tegra_mc *mc,
199 const struct tegra_mc_reset *rst)
204 spin_lock_irqsave(&mc->lock, flags);
206 value = mc_readl(mc, rst->reset);
207 mc_writel(mc, value & ~BIT(rst->bit), rst->reset);
209 spin_unlock_irqrestore(&mc->lock, flags);
214 static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc,
215 const struct tegra_mc_reset *rst)
220 spin_lock_irqsave(&mc->lock, flags);
222 value = mc_readl(mc, rst->reset);
223 mc_writel(mc, value | BIT(rst->bit), rst->reset);
225 spin_unlock_irqrestore(&mc->lock, flags);
230 static int tegra20_mc_block_dma(struct tegra_mc *mc,
231 const struct tegra_mc_reset *rst)
236 spin_lock_irqsave(&mc->lock, flags);
238 value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
239 mc_writel(mc, value, rst->control);
241 spin_unlock_irqrestore(&mc->lock, flags);
246 static bool tegra20_mc_dma_idling(struct tegra_mc *mc,
247 const struct tegra_mc_reset *rst)
249 return mc_readl(mc, rst->status) == 0;
252 static int tegra20_mc_reset_status(struct tegra_mc *mc,
253 const struct tegra_mc_reset *rst)
255 return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
258 static int tegra20_mc_unblock_dma(struct tegra_mc *mc,
259 const struct tegra_mc_reset *rst)
264 spin_lock_irqsave(&mc->lock, flags);
266 value = mc_readl(mc, rst->control) | BIT(rst->bit);
267 mc_writel(mc, value, rst->control);
269 spin_unlock_irqrestore(&mc->lock, flags);
274 static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = {
275 .hotreset_assert = tegra20_mc_hotreset_assert,
276 .hotreset_deassert = tegra20_mc_hotreset_deassert,
277 .block_dma = tegra20_mc_block_dma,
278 .dma_idling = tegra20_mc_dma_idling,
279 .unblock_dma = tegra20_mc_unblock_dma,
280 .reset_status = tegra20_mc_reset_status,
283 const struct tegra_mc_soc tegra20_mc_soc = {
284 .clients = tegra20_mc_clients,
285 .num_clients = ARRAY_SIZE(tegra20_mc_clients),
286 .num_address_bits = 32,
287 .client_id_mask = 0x3f,
288 .intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
290 .reset_ops = &tegra20_mc_reset_ops,
291 .resets = tegra20_mc_resets,
292 .num_resets = ARRAY_SIZE(tegra20_mc_resets),