2 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/memory/tegra20-mc.h>
13 static const struct tegra_mc_client tegra20_mc_clients[] = {
91 .name = "ppcsahbdmar",
94 .name = "ppcsahbslvr",
157 .name = "ppcsahbdmaw",
160 .name = "ppcsahbslvw",
173 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \
176 .id = TEGRA20_MC_RESET_##_name, \
177 .control = _control, \
183 static const struct tegra_mc_reset tegra20_mc_resets[] = {
184 TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
185 TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
186 TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
187 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
188 TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
189 TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
190 TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
191 TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
192 TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
193 TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9),
194 TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10),
195 TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11),
196 TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12),
197 TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13),
198 TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
201 static int terga20_mc_hotreset_assert(struct tegra_mc *mc,
202 const struct tegra_mc_reset *rst)
207 spin_lock_irqsave(&mc->lock, flags);
209 value = mc_readl(mc, rst->reset);
210 mc_writel(mc, value & ~BIT(rst->bit), rst->reset);
212 spin_unlock_irqrestore(&mc->lock, flags);
217 static int terga20_mc_hotreset_deassert(struct tegra_mc *mc,
218 const struct tegra_mc_reset *rst)
223 spin_lock_irqsave(&mc->lock, flags);
225 value = mc_readl(mc, rst->reset);
226 mc_writel(mc, value | BIT(rst->bit), rst->reset);
228 spin_unlock_irqrestore(&mc->lock, flags);
233 static int terga20_mc_block_dma(struct tegra_mc *mc,
234 const struct tegra_mc_reset *rst)
239 spin_lock_irqsave(&mc->lock, flags);
241 value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
242 mc_writel(mc, value, rst->control);
244 spin_unlock_irqrestore(&mc->lock, flags);
249 static bool terga20_mc_dma_idling(struct tegra_mc *mc,
250 const struct tegra_mc_reset *rst)
252 return mc_readl(mc, rst->status) == 0;
255 static int terga20_mc_reset_status(struct tegra_mc *mc,
256 const struct tegra_mc_reset *rst)
258 return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
261 static int terga20_mc_unblock_dma(struct tegra_mc *mc,
262 const struct tegra_mc_reset *rst)
267 spin_lock_irqsave(&mc->lock, flags);
269 value = mc_readl(mc, rst->control) | BIT(rst->bit);
270 mc_writel(mc, value, rst->control);
272 spin_unlock_irqrestore(&mc->lock, flags);
277 const struct tegra_mc_reset_ops terga20_mc_reset_ops = {
278 .hotreset_assert = terga20_mc_hotreset_assert,
279 .hotreset_deassert = terga20_mc_hotreset_deassert,
280 .block_dma = terga20_mc_block_dma,
281 .dma_idling = terga20_mc_dma_idling,
282 .unblock_dma = terga20_mc_unblock_dma,
283 .reset_status = terga20_mc_reset_status,
286 const struct tegra_mc_soc tegra20_mc_soc = {
287 .clients = tegra20_mc_clients,
288 .num_clients = ARRAY_SIZE(tegra20_mc_clients),
289 .num_address_bits = 32,
290 .client_id_mask = 0x3f,
291 .intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
293 .reset_ops = &terga20_mc_reset_ops,
294 .resets = tegra20_mc_resets,
295 .num_resets = ARRAY_SIZE(tegra20_mc_resets),