1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra114-mc.h>
13 static const struct tegra_mc_client tegra114_mc_clients[] = {
17 .swgroup = TEGRA_SWGROUP_PTC,
29 .swgroup = TEGRA_SWGROUP_DC,
45 .swgroup = TEGRA_SWGROUP_DCB,
61 .swgroup = TEGRA_SWGROUP_DC,
77 .swgroup = TEGRA_SWGROUP_DCB,
93 .swgroup = TEGRA_SWGROUP_DC,
108 .name = "display0cb",
109 .swgroup = TEGRA_SWGROUP_DCB,
125 .swgroup = TEGRA_SWGROUP_EPP,
141 .swgroup = TEGRA_SWGROUP_G2,
157 .swgroup = TEGRA_SWGROUP_G2,
173 .swgroup = TEGRA_SWGROUP_AVPC,
189 .swgroup = TEGRA_SWGROUP_DC,
204 .name = "displayhcb",
205 .swgroup = TEGRA_SWGROUP_DCB,
221 .swgroup = TEGRA_SWGROUP_NV,
237 .swgroup = TEGRA_SWGROUP_NV,
253 .swgroup = TEGRA_SWGROUP_G2,
269 .swgroup = TEGRA_SWGROUP_HDA,
284 .name = "host1xdmar",
285 .swgroup = TEGRA_SWGROUP_HC,
301 .swgroup = TEGRA_SWGROUP_HC,
317 .swgroup = TEGRA_SWGROUP_NV,
333 .swgroup = TEGRA_SWGROUP_MSENC,
348 .name = "ppcsahbdmar",
349 .swgroup = TEGRA_SWGROUP_PPCS,
364 .name = "ppcsahbslvr",
365 .swgroup = TEGRA_SWGROUP_PPCS,
381 .swgroup = TEGRA_SWGROUP_NV,
397 .swgroup = TEGRA_SWGROUP_VDE,
413 .swgroup = TEGRA_SWGROUP_VDE,
429 .swgroup = TEGRA_SWGROUP_VDE,
445 .swgroup = TEGRA_SWGROUP_VDE,
461 .swgroup = TEGRA_SWGROUP_MPCORELP,
473 .swgroup = TEGRA_SWGROUP_MPCORE,
485 .swgroup = TEGRA_SWGROUP_EPP,
501 .swgroup = TEGRA_SWGROUP_EPP,
517 .swgroup = TEGRA_SWGROUP_EPP,
533 .swgroup = TEGRA_SWGROUP_MSENC,
549 .swgroup = TEGRA_SWGROUP_VI,
565 .swgroup = TEGRA_SWGROUP_VI,
581 .swgroup = TEGRA_SWGROUP_VI,
597 .swgroup = TEGRA_SWGROUP_VI,
613 .swgroup = TEGRA_SWGROUP_G2,
629 .swgroup = TEGRA_SWGROUP_AVPC,
645 .swgroup = TEGRA_SWGROUP_NV,
661 .swgroup = TEGRA_SWGROUP_NV,
677 .swgroup = TEGRA_SWGROUP_HDA,
693 .swgroup = TEGRA_SWGROUP_HC,
709 .swgroup = TEGRA_SWGROUP_ISP,
725 .swgroup = TEGRA_SWGROUP_MPCORELP,
737 .swgroup = TEGRA_SWGROUP_MPCORE,
748 .name = "ppcsahbdmaw",
749 .swgroup = TEGRA_SWGROUP_PPCS,
764 .name = "ppcsahbslvw",
765 .swgroup = TEGRA_SWGROUP_PPCS,
781 .swgroup = TEGRA_SWGROUP_VDE,
797 .swgroup = TEGRA_SWGROUP_VDE,
813 .swgroup = TEGRA_SWGROUP_VDE,
829 .swgroup = TEGRA_SWGROUP_VDE,
844 .name = "xusb_hostr",
845 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
860 .name = "xusb_hostw",
861 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
877 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
893 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
909 .swgroup = TEGRA_SWGROUP_NV,
925 .swgroup = TEGRA_SWGROUP_NV,
941 .swgroup = TEGRA_SWGROUP_NV,
957 .swgroup = TEGRA_SWGROUP_NV,
973 .swgroup = TEGRA_SWGROUP_EMUCIF,
985 .swgroup = TEGRA_SWGROUP_EMUCIF,
997 .swgroup = TEGRA_SWGROUP_TSEC,
1013 .swgroup = TEGRA_SWGROUP_TSEC,
1029 static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
1030 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1031 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1032 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
1033 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
1034 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1036 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1037 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1038 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1039 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1040 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1041 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1042 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
1043 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1044 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1045 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1048 static const unsigned int tegra114_group_drm[] = {
1055 static const struct tegra_smmu_group_soc tegra114_groups[] = {
1058 .swgroups = tegra114_group_drm,
1059 .num_swgroups = ARRAY_SIZE(tegra114_group_drm),
1063 static const struct tegra_smmu_soc tegra114_smmu_soc = {
1064 .clients = tegra114_mc_clients,
1065 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1066 .swgroups = tegra114_swgroups,
1067 .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
1068 .groups = tegra114_groups,
1069 .num_groups = ARRAY_SIZE(tegra114_groups),
1070 .supports_round_robin_arbitration = false,
1071 .supports_request_limit = false,
1072 .num_tlb_lines = 32,
1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \
1079 .id = TEGRA114_MC_RESET_##_name, \
1080 .control = _control, \
1081 .status = _status, \
1085 static const struct tegra_mc_reset tegra114_mc_resets[] = {
1086 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
1087 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
1088 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
1089 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
1090 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
1091 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
1092 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
1093 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
1094 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
1095 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1096 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
1097 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
1098 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
1099 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
1101 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
1104 const struct tegra_mc_soc tegra114_mc_soc = {
1105 .clients = tegra114_mc_clients,
1106 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1107 .num_address_bits = 32,
1109 .client_id_mask = 0x7f,
1110 .smmu = &tegra114_smmu_soc,
1111 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1113 .reset_ops = &tegra_mc_reset_ops_common,
1114 .resets = tegra114_mc_resets,
1115 .num_resets = ARRAY_SIZE(tegra114_mc_resets),
1116 .ops = &tegra30_mc_ops,