drivers/memory/tegra/tegra114.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra114-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const struct tegra_mc_client tegra114_mc_clients[] = {
  14         {
  15                 .id = 0x00,
  16                 .name = "ptcr",
  17                 .swgroup = TEGRA_SWGROUP_PTC,
  18                 .la = {
  19                         .reg = 0x34c,
  20                         .shift = 0,
  21                         .mask = 0xff,
  22                         .def = 0x0,
  23                 },
  24         }, {
  25                 .id = 0x01,
  26                 .name = "display0a",
  27                 .swgroup = TEGRA_SWGROUP_DC,
  28                 .smmu = {
  29                         .reg = 0x228,
  30                         .bit = 1,
  31                 },
  32                 .la = {
  33                         .reg = 0x2e8,
  34                         .shift = 0,
  35                         .mask = 0xff,
  36                         .def = 0x4e,
  37                 },
  38         }, {
  39                 .id = 0x02,
  40                 .name = "display0ab",
  41                 .swgroup = TEGRA_SWGROUP_DCB,
  42                 .smmu = {
  43                         .reg = 0x228,
  44                         .bit = 2,
  45                 },
  46                 .la = {
  47                         .reg = 0x2f4,
  48                         .shift = 0,
  49                         .mask = 0xff,
  50                         .def = 0x4e,
  51                 },
  52         }, {
  53                 .id = 0x03,
  54                 .name = "display0b",
  55                 .swgroup = TEGRA_SWGROUP_DC,
  56                 .smmu = {
  57                         .reg = 0x228,
  58                         .bit = 3,
  59                 },
  60                 .la = {
  61                         .reg = 0x2e8,
  62                         .shift = 16,
  63                         .mask = 0xff,
  64                         .def = 0x4e,
  65                 },
  66         }, {
  67                 .id = 0x04,
  68                 .name = "display0bb",
  69                 .swgroup = TEGRA_SWGROUP_DCB,
  70                 .smmu = {
  71                         .reg = 0x228,
  72                         .bit = 4,
  73                 },
  74                 .la = {
  75                         .reg = 0x2f4,
  76                         .shift = 16,
  77                         .mask = 0xff,
  78                         .def = 0x4e,
  79                 },
  80         }, {
  81                 .id = 0x05,
  82                 .name = "display0c",
  83                 .swgroup = TEGRA_SWGROUP_DC,
  84                 .smmu = {
  85                         .reg = 0x228,
  86                         .bit = 5,
  87                 },
  88                 .la = {
  89                         .reg = 0x2ec,
  90                         .shift = 0,
  91                         .mask = 0xff,
  92                         .def = 0x4e,
  93                 },
  94         }, {
  95                 .id = 0x06,
  96                 .name = "display0cb",
  97                 .swgroup = TEGRA_SWGROUP_DCB,
  98                 .smmu = {
  99                         .reg = 0x228,
 100                         .bit = 6,
 101                 },
 102                 .la = {
 103                         .reg = 0x2f8,
 104                         .shift = 0,
 105                         .mask = 0xff,
 106                         .def = 0x4e,
 107                 },
 108         }, {
 109                 .id = 0x09,
 110                 .name = "eppup",
 111                 .swgroup = TEGRA_SWGROUP_EPP,
 112                 .smmu = {
 113                         .reg = 0x228,
 114                         .bit = 9,
 115                 },
 116                 .la = {
 117                         .reg = 0x300,
 118                         .shift = 0,
 119                         .mask = 0xff,
 120                         .def = 0x33,
 121                 },
 122         }, {
 123                 .id = 0x0a,
 124                 .name = "g2pr",
 125                 .swgroup = TEGRA_SWGROUP_G2,
 126                 .smmu = {
 127                         .reg = 0x228,
 128                         .bit = 10,
 129                 },
 130                 .la = {
 131                         .reg = 0x308,
 132                         .shift = 0,
 133                         .mask = 0xff,
 134                         .def = 0x09,
 135                 },
 136         }, {
 137                 .id = 0x0b,
 138                 .name = "g2sr",
 139                 .swgroup = TEGRA_SWGROUP_G2,
 140                 .smmu = {
 141                         .reg = 0x228,
 142                         .bit = 11,
 143                 },
 144                 .la = {
 145                         .reg = 0x308,
 146                         .shift = 16,
 147                         .mask = 0xff,
 148                         .def = 0x09,
 149                 },
 150         }, {
 151                 .id = 0x0f,
 152                 .name = "avpcarm7r",
 153                 .swgroup = TEGRA_SWGROUP_AVPC,
 154                 .smmu = {
 155                         .reg = 0x228,
 156                         .bit = 15,
 157                 },
 158                 .la = {
 159                         .reg = 0x2e4,
 160                         .shift = 0,
 161                         .mask = 0xff,
 162                         .def = 0x04,
 163                 },
 164         }, {
 165                 .id = 0x10,
 166                 .name = "displayhc",
 167                 .swgroup = TEGRA_SWGROUP_DC,
 168                 .smmu = {
 169                         .reg = 0x228,
 170                         .bit = 16,
 171                 },
 172                 .la = {
 173                         .reg = 0x2f0,
 174                         .shift = 0,
 175                         .mask = 0xff,
 176                         .def = 0x68,
 177                 },
 178         }, {
 179                 .id = 0x11,
 180                 .name = "displayhcb",
 181                 .swgroup = TEGRA_SWGROUP_DCB,
 182                 .smmu = {
 183                         .reg = 0x228,
 184                         .bit = 17,
 185                 },
 186                 .la = {
 187                         .reg = 0x2fc,
 188                         .shift = 0,
 189                         .mask = 0xff,
 190                         .def = 0x68,
 191                 },
 192         }, {
 193                 .id = 0x12,
 194                 .name = "fdcdrd",
 195                 .swgroup = TEGRA_SWGROUP_NV,
 196                 .smmu = {
 197                         .reg = 0x228,
 198                         .bit = 18,
 199                 },
 200                 .la = {
 201                         .reg = 0x334,
 202                         .shift = 0,
 203                         .mask = 0xff,
 204                         .def = 0x0c,
 205                 },
 206         }, {
 207                 .id = 0x13,
 208                 .name = "fdcdrd2",
 209                 .swgroup = TEGRA_SWGROUP_NV,
 210                 .smmu = {
 211                         .reg = 0x228,
 212                         .bit = 19,
 213                 },
 214                 .la = {
 215                         .reg = 0x33c,
 216                         .shift = 0,
 217                         .mask = 0xff,
 218                         .def = 0x0c,
 219                 },
 220         }, {
 221                 .id = 0x14,
 222                 .name = "g2dr",
 223                 .swgroup = TEGRA_SWGROUP_G2,
 224                 .smmu = {
 225                         .reg = 0x228,
 226                         .bit = 20,
 227                 },
 228                 .la = {
 229                         .reg = 0x30c,
 230                         .shift = 0,
 231                         .mask = 0xff,
 232                         .def = 0x0a,
 233                 },
 234         }, {
 235                 .id = 0x15,
 236                 .name = "hdar",
 237                 .swgroup = TEGRA_SWGROUP_HDA,
 238                 .smmu = {
 239                         .reg = 0x228,
 240                         .bit = 21,
 241                 },
 242                 .la = {
 243                         .reg = 0x318,
 244                         .shift = 0,
 245                         .mask = 0xff,
 246                         .def = 0xff,
 247                 },
 248         }, {
 249                 .id = 0x16,
 250                 .name = "host1xdmar",
 251                 .swgroup = TEGRA_SWGROUP_HC,
 252                 .smmu = {
 253                         .reg = 0x228,
 254                         .bit = 22,
 255                 },
 256                 .la = {
 257                         .reg = 0x310,
 258                         .shift = 0,
 259                         .mask = 0xff,
 260                         .def = 0x10,
 261                 },
 262         }, {
 263                 .id = 0x17,
 264                 .name = "host1xr",
 265                 .swgroup = TEGRA_SWGROUP_HC,
 266                 .smmu = {
 267                         .reg = 0x228,
 268                         .bit = 23,
 269                 },
 270                 .la = {
 271                         .reg = 0x310,
 272                         .shift = 16,
 273                         .mask = 0xff,
 274                         .def = 0xa5,
 275                 },
 276         }, {
 277                 .id = 0x18,
 278                 .name = "idxsrd",
 279                 .swgroup = TEGRA_SWGROUP_NV,
 280                 .smmu = {
 281                         .reg = 0x228,
 282                         .bit = 24,
 283                 },
 284                 .la = {
 285                         .reg = 0x334,
 286                         .shift = 16,
 287                         .mask = 0xff,
 288                         .def = 0x0b,
 289                 },
 290         }, {
 291                 .id = 0x1c,
 292                 .name = "msencsrd",
 293                 .swgroup = TEGRA_SWGROUP_MSENC,
 294                 .smmu = {
 295                         .reg = 0x228,
 296                         .bit = 28,
 297                 },
 298                 .la = {
 299                         .reg = 0x328,
 300                         .shift = 0,
 301                         .mask = 0xff,
 302                         .def = 0x80,
 303                 },
 304         }, {
 305                 .id = 0x1d,
 306                 .name = "ppcsahbdmar",
 307                 .swgroup = TEGRA_SWGROUP_PPCS,
 308                 .smmu = {
 309                         .reg = 0x228,
 310                         .bit = 29,
 311                 },
 312                 .la = {
 313                         .reg = 0x344,
 314                         .shift = 0,
 315                         .mask = 0xff,
 316                         .def = 0x50,
 317                 },
 318         }, {
 319                 .id = 0x1e,
 320                 .name = "ppcsahbslvr",
 321                 .swgroup = TEGRA_SWGROUP_PPCS,
 322                 .smmu = {
 323                         .reg = 0x228,
 324                         .bit = 30,
 325                 },
 326                 .la = {
 327                         .reg = 0x344,
 328                         .shift = 16,
 329                         .mask = 0xff,
 330                         .def = 0xe8,
 331                 },
 332         }, {
 333                 .id = 0x20,
 334                 .name = "texl2srd",
 335                 .swgroup = TEGRA_SWGROUP_NV,
 336                 .smmu = {
 337                         .reg = 0x22c,
 338                         .bit = 0,
 339                 },
 340                 .la = {
 341                         .reg = 0x338,
 342                         .shift = 0,
 343                         .mask = 0xff,
 344                         .def = 0x0c,
 345                 },
 346         }, {
 347                 .id = 0x22,
 348                 .name = "vdebsevr",
 349                 .swgroup = TEGRA_SWGROUP_VDE,
 350                 .smmu = {
 351                         .reg = 0x22c,
 352                         .bit = 2,
 353                 },
 354                 .la = {
 355                         .reg = 0x354,
 356                         .shift = 0,
 357                         .mask = 0xff,
 358                         .def = 0xff,
 359                 },
 360         }, {
 361                 .id = 0x23,
 362                 .name = "vdember",
 363                 .swgroup = TEGRA_SWGROUP_VDE,
 364                 .smmu = {
 365                         .reg = 0x22c,
 366                         .bit = 3,
 367                 },
 368                 .la = {
 369                         .reg = 0x354,
 370                         .shift = 16,
 371                         .mask = 0xff,
 372                         .def = 0xff,
 373                 },
 374         }, {
 375                 .id = 0x24,
 376                 .name = "vdemcer",
 377                 .swgroup = TEGRA_SWGROUP_VDE,
 378                 .smmu = {
 379                         .reg = 0x22c,
 380                         .bit = 4,
 381                 },
 382                 .la = {
 383                         .reg = 0x358,
 384                         .shift = 0,
 385                         .mask = 0xff,
 386                         .def = 0xb8,
 387                 },
 388         }, {
 389                 .id = 0x25,
 390                 .name = "vdetper",
 391                 .swgroup = TEGRA_SWGROUP_VDE,
 392                 .smmu = {
 393                         .reg = 0x22c,
 394                         .bit = 5,
 395                 },
 396                 .la = {
 397                         .reg = 0x358,
 398                         .shift = 16,
 399                         .mask = 0xff,
 400                         .def = 0xee,
 401                 },
 402         }, {
 403                 .id = 0x26,
 404                 .name = "mpcorelpr",
 405                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 406                 .la = {
 407                         .reg = 0x324,
 408                         .shift = 0,
 409                         .mask = 0xff,
 410                         .def = 0x04,
 411                 },
 412         }, {
 413                 .id = 0x27,
 414                 .name = "mpcorer",
 415                 .swgroup = TEGRA_SWGROUP_MPCORE,
 416                 .la = {
 417                         .reg = 0x320,
 418                         .shift = 0,
 419                         .mask = 0xff,
 420                         .def = 0x04,
 421                 },
 422         }, {
 423                 .id = 0x28,
 424                 .name = "eppu",
 425                 .swgroup = TEGRA_SWGROUP_EPP,
 426                 .smmu = {
 427                         .reg = 0x22c,
 428                         .bit = 8,
 429                 },
 430                 .la = {
 431                         .reg = 0x300,
 432                         .shift = 16,
 433                         .mask = 0xff,
 434                         .def = 0x33,
 435                 },
 436         }, {
 437                 .id = 0x29,
 438                 .name = "eppv",
 439                 .swgroup = TEGRA_SWGROUP_EPP,
 440                 .smmu = {
 441                         .reg = 0x22c,
 442                         .bit = 9,
 443                 },
 444                 .la = {
 445                         .reg = 0x304,
 446                         .shift = 0,
 447                         .mask = 0xff,
 448                         .def = 0x6c,
 449                 },
 450         }, {
 451                 .id = 0x2a,
 452                 .name = "eppy",
 453                 .swgroup = TEGRA_SWGROUP_EPP,
 454                 .smmu = {
 455                         .reg = 0x22c,
 456                         .bit = 10,
 457                 },
 458                 .la = {
 459                         .reg = 0x304,
 460                         .shift = 16,
 461                         .mask = 0xff,
 462                         .def = 0x6c,
 463                 },
 464         }, {
 465                 .id = 0x2b,
 466                 .name = "msencswr",
 467                 .swgroup = TEGRA_SWGROUP_MSENC,
 468                 .smmu = {
 469                         .reg = 0x22c,
 470                         .bit = 11,
 471                 },
 472                 .la = {
 473                         .reg = 0x328,
 474                         .shift = 16,
 475                         .mask = 0xff,
 476                         .def = 0x80,
 477                 },
 478         }, {
 479                 .id = 0x2c,
 480                 .name = "viwsb",
 481                 .swgroup = TEGRA_SWGROUP_VI,
 482                 .smmu = {
 483                         .reg = 0x22c,
 484                         .bit = 12,
 485                 },
 486                 .la = {
 487                         .reg = 0x364,
 488                         .shift = 0,
 489                         .mask = 0xff,
 490                         .def = 0x47,
 491                 },
 492         }, {
 493                 .id = 0x2d,
 494                 .name = "viwu",
 495                 .swgroup = TEGRA_SWGROUP_VI,
 496                 .smmu = {
 497                         .reg = 0x22c,
 498                         .bit = 13,
 499                 },
 500                 .la = {
 501                         .reg = 0x368,
 502                         .shift = 0,
 503                         .mask = 0xff,
 504                         .def = 0xff,
 505                 },
 506         }, {
 507                 .id = 0x2e,
 508                 .name = "viwv",
 509                 .swgroup = TEGRA_SWGROUP_VI,
 510                 .smmu = {
 511                         .reg = 0x22c,
 512                         .bit = 14,
 513                 },
 514                 .la = {
 515                         .reg = 0x368,
 516                         .shift = 16,
 517                         .mask = 0xff,
 518                         .def = 0xff,
 519                 },
 520         }, {
 521                 .id = 0x2f,
 522                 .name = "viwy",
 523                 .swgroup = TEGRA_SWGROUP_VI,
 524                 .smmu = {
 525                         .reg = 0x22c,
 526                         .bit = 15,
 527                 },
 528                 .la = {
 529                         .reg = 0x36c,
 530                         .shift = 0,
 531                         .mask = 0xff,
 532                         .def = 0x47,
 533                 },
 534         }, {
 535                 .id = 0x30,
 536                 .name = "g2dw",
 537                 .swgroup = TEGRA_SWGROUP_G2,
 538                 .smmu = {
 539                         .reg = 0x22c,
 540                         .bit = 16,
 541                 },
 542                 .la = {
 543                         .reg = 0x30c,
 544                         .shift = 16,
 545                         .mask = 0xff,
 546                         .def = 0x9,
 547                 },
 548         }, {
 549                 .id = 0x32,
 550                 .name = "avpcarm7w",
 551                 .swgroup = TEGRA_SWGROUP_AVPC,
 552                 .smmu = {
 553                         .reg = 0x22c,
 554                         .bit = 18,
 555                 },
 556                 .la = {
 557                         .reg = 0x2e4,
 558                         .shift = 16,
 559                         .mask = 0xff,
 560                         .def = 0x0e,
 561                 },
 562         }, {
 563                 .id = 0x33,
 564                 .name = "fdcdwr",
 565                 .swgroup = TEGRA_SWGROUP_NV,
 566                 .smmu = {
 567                         .reg = 0x22c,
 568                         .bit = 19,
 569                 },
 570                 .la = {
 571                         .reg = 0x338,
 572                         .shift = 16,
 573                         .mask = 0xff,
 574                         .def = 0x10,
 575                 },
 576         }, {
 577                 .id = 0x34,
 578                 .name = "fdcdwr2",
 579                 .swgroup = TEGRA_SWGROUP_NV,
 580                 .smmu = {
 581                         .reg = 0x22c,
 582                         .bit = 20,
 583                 },
 584                 .la = {
 585                         .reg = 0x340,
 586                         .shift = 0,
 587                         .mask = 0xff,
 588                         .def = 0x10,
 589                 },
 590         }, {
 591                 .id = 0x35,
 592                 .name = "hdaw",
 593                 .swgroup = TEGRA_SWGROUP_HDA,
 594                 .smmu = {
 595                         .reg = 0x22c,
 596                         .bit = 21,
 597                 },
 598                 .la = {
 599                         .reg = 0x318,
 600                         .shift = 16,
 601                         .mask = 0xff,
 602                         .def = 0xff,
 603                 },
 604         }, {
 605                 .id = 0x36,
 606                 .name = "host1xw",
 607                 .swgroup = TEGRA_SWGROUP_HC,
 608                 .smmu = {
 609                         .reg = 0x22c,
 610                         .bit = 22,
 611                 },
 612                 .la = {
 613                         .reg = 0x314,
 614                         .shift = 0,
 615                         .mask = 0xff,
 616                         .def = 0x25,
 617                 },
 618         }, {
 619                 .id = 0x37,
 620                 .name = "ispw",
 621                 .swgroup = TEGRA_SWGROUP_ISP,
 622                 .smmu = {
 623                         .reg = 0x22c,
 624                         .bit = 23,
 625                 },
 626                 .la = {
 627                         .reg = 0x31c,
 628                         .shift = 0,
 629                         .mask = 0xff,
 630                         .def = 0xff,
 631                 },
 632         }, {
 633                 .id = 0x38,
 634                 .name = "mpcorelpw",
 635                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 636                 .la = {
 637                         .reg = 0x324,
 638                         .shift = 16,
 639                         .mask = 0xff,
 640                         .def = 0x80,
 641                 },
 642         }, {
 643                 .id = 0x39,
 644                 .name = "mpcorew",
 645                 .swgroup = TEGRA_SWGROUP_MPCORE,
 646                 .la = {
 647                         .reg = 0x320,
 648                         .shift = 16,
 649                         .mask = 0xff,
 650                         .def = 0x0e,
 651                 },
 652         }, {
 653                 .id = 0x3b,
 654                 .name = "ppcsahbdmaw",
 655                 .swgroup = TEGRA_SWGROUP_PPCS,
 656                 .smmu = {
 657                         .reg = 0x22c,
 658                         .bit = 27,
 659                 },
 660                 .la = {
 661                         .reg = 0x348,
 662                         .shift = 0,
 663                         .mask = 0xff,
 664                         .def = 0xa5,
 665                 },
 666         }, {
 667                 .id = 0x3c,
 668                 .name = "ppcsahbslvw",
 669                 .swgroup = TEGRA_SWGROUP_PPCS,
 670                 .smmu = {
 671                         .reg = 0x22c,
 672                         .bit = 28,
 673                 },
 674                 .la = {
 675                         .reg = 0x348,
 676                         .shift = 16,
 677                         .mask = 0xff,
 678                         .def = 0xe8,
 679                 },
 680         }, {
 681                 .id = 0x3e,
 682                 .name = "vdebsevw",
 683                 .swgroup = TEGRA_SWGROUP_VDE,
 684                 .smmu = {
 685                         .reg = 0x22c,
 686                         .bit = 30,
 687                 },
 688                 .la = {
 689                         .reg = 0x35c,
 690                         .shift = 0,
 691                         .mask = 0xff,
 692                         .def = 0xff,
 693                 },
 694         }, {
 695                 .id = 0x3f,
 696                 .name = "vdedbgw",
 697                 .swgroup = TEGRA_SWGROUP_VDE,
 698                 .smmu = {
 699                         .reg = 0x22c,
 700                         .bit = 31,
 701                 },
 702                 .la = {
 703                         .reg = 0x35c,
 704                         .shift = 16,
 705                         .mask = 0xff,
 706                         .def = 0xff,
 707                 },
 708         }, {
 709                 .id = 0x40,
 710                 .name = "vdembew",
 711                 .swgroup = TEGRA_SWGROUP_VDE,
 712                 .smmu = {
 713                         .reg = 0x230,
 714                         .bit = 0,
 715                 },
 716                 .la = {
 717                         .reg = 0x360,
 718                         .shift = 0,
 719                         .mask = 0xff,
 720                         .def = 0x89,
 721                 },
 722         }, {
 723                 .id = 0x41,
 724                 .name = "vdetpmw",
 725                 .swgroup = TEGRA_SWGROUP_VDE,
 726                 .smmu = {
 727                         .reg = 0x230,
 728                         .bit = 1,
 729                 },
 730                 .la = {
 731                         .reg = 0x360,
 732                         .shift = 16,
 733                         .mask = 0xff,
 734                         .def = 0x59,
 735                 },
 736         }, {
 737                 .id = 0x4a,
 738                 .name = "xusb_hostr",
 739                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 740                 .smmu = {
 741                         .reg = 0x230,
 742                         .bit = 10,
 743                 },
 744                 .la = {
 745                         .reg = 0x37c,
 746                         .shift = 0,
 747                         .mask = 0xff,
 748                         .def = 0xa5,
 749                 },
 750         }, {
 751                 .id = 0x4b,
 752                 .name = "xusb_hostw",
 753                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 754                 .smmu = {
 755                         .reg = 0x230,
 756                         .bit = 11,
 757                 },
 758                 .la = {
 759                         .reg = 0x37c,
 760                         .shift = 16,
 761                         .mask = 0xff,
 762                         .def = 0xa5,
 763                 },
 764         }, {
 765                 .id = 0x4c,
 766                 .name = "xusb_devr",
 767                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 768                 .smmu = {
 769                         .reg = 0x230,
 770                         .bit = 12,
 771                 },
 772                 .la = {
 773                         .reg = 0x380,
 774                         .shift = 0,
 775                         .mask = 0xff,
 776                         .def = 0xa5,
 777                 },
 778         }, {
 779                 .id = 0x4d,
 780                 .name = "xusb_devw",
 781                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 782                 .smmu = {
 783                         .reg = 0x230,
 784                         .bit = 13,
 785                 },
 786                 .la = {
 787                         .reg = 0x380,
 788                         .shift = 16,
 789                         .mask = 0xff,
 790                         .def = 0xa5,
 791                 },
 792         }, {
 793                 .id = 0x4e,
 794                 .name = "fdcdwr3",
 795                 .swgroup = TEGRA_SWGROUP_NV,
 796                 .smmu = {
 797                         .reg = 0x230,
 798                         .bit = 14,
 799                 },
 800                 .la = {
 801                         .reg = 0x388,
 802                         .shift = 0,
 803                         .mask = 0xff,
 804                         .def = 0x10,
 805                 },
 806         }, {
 807                 .id = 0x4f,
 808                 .name = "fdcdrd3",
 809                 .swgroup = TEGRA_SWGROUP_NV,
 810                 .smmu = {
 811                         .reg = 0x230,
 812                         .bit = 15,
 813                 },
 814                 .la = {
 815                         .reg = 0x384,
 816                         .shift = 0,
 817                         .mask = 0xff,
 818                         .def = 0x0c,
 819                 },
 820         }, {
 821                 .id = 0x50,
 822                 .name = "fdcwr4",
 823                 .swgroup = TEGRA_SWGROUP_NV,
 824                 .smmu = {
 825                         .reg = 0x230,
 826                         .bit = 16,
 827                 },
 828                 .la = {
 829                         .reg = 0x388,
 830                         .shift = 16,
 831                         .mask = 0xff,
 832                         .def = 0x10,
 833                 },
 834         }, {
 835                 .id = 0x51,
 836                 .name = "fdcrd4",
 837                 .swgroup = TEGRA_SWGROUP_NV,
 838                 .smmu = {
 839                         .reg = 0x230,
 840                         .bit = 17,
 841                 },
 842                 .la = {
 843                         .reg = 0x384,
 844                         .shift = 16,
 845                         .mask = 0xff,
 846                         .def = 0x0c,
 847                 },
 848         }, {
 849                 .id = 0x52,
 850                 .name = "emucifr",
 851                 .swgroup = TEGRA_SWGROUP_EMUCIF,
 852                 .la = {
 853                         .reg = 0x38c,
 854                         .shift = 0,
 855                         .mask = 0xff,
 856                         .def = 0x04,
 857                 },
 858         }, {
 859                 .id = 0x53,
 860                 .name = "emucifw",
 861                 .swgroup = TEGRA_SWGROUP_EMUCIF,
 862                 .la = {
 863                         .reg = 0x38c,
 864                         .shift = 16,
 865                         .mask = 0xff,
 866                         .def = 0x0e,
 867                 },
 868         }, {
 869                 .id = 0x54,
 870                 .name = "tsecsrd",
 871                 .swgroup = TEGRA_SWGROUP_TSEC,
 872                 .smmu = {
 873                         .reg = 0x230,
 874                         .bit = 20,
 875                 },
 876                 .la = {
 877                         .reg = 0x390,
 878                         .shift = 0,
 879                         .mask = 0xff,
 880                         .def = 0x50,
 881                 },
 882         }, {
 883                 .id = 0x55,
 884                 .name = "tsecswr",
 885                 .swgroup = TEGRA_SWGROUP_TSEC,
 886                 .smmu = {
 887                         .reg = 0x230,
 888                         .bit = 21,
 889                 },
 890                 .la = {
 891                         .reg = 0x390,
 892                         .shift = 16,
 893                         .mask = 0xff,
 894                         .def = 0x50,
 895                 },
 896         },
 897 };
 898
 899 static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
 900         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 901         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 902         { .name = "epp",       .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },
 903         { .name = "g2",        .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },
 904         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 905         { .name = "nv",        .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },
 906         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 907         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 908         { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 909         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 910         { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 911         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 912         { .name = "isp",       .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },
 913         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 914         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 915         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 916 };
 917
 918 static const unsigned int tegra114_group_drm[] = {
 919         TEGRA_SWGROUP_DC,
 920         TEGRA_SWGROUP_DCB,
 921         TEGRA_SWGROUP_G2,
 922         TEGRA_SWGROUP_NV,
 923 };
 924
 925 static const struct tegra_smmu_group_soc tegra114_groups[] = {
 926         {
 927                 .name = "drm",
 928                 .swgroups = tegra114_group_drm,
 929                 .num_swgroups = ARRAY_SIZE(tegra114_group_drm),
 930         },
 931 };
 932
 933 static const struct tegra_smmu_soc tegra114_smmu_soc = {
 934         .clients = tegra114_mc_clients,
 935         .num_clients = ARRAY_SIZE(tegra114_mc_clients),
 936         .swgroups = tegra114_swgroups,
 937         .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
 938         .groups = tegra114_groups,
 939         .num_groups = ARRAY_SIZE(tegra114_groups),
 940         .supports_round_robin_arbitration = false,
 941         .supports_request_limit = false,
 942         .num_tlb_lines = 32,
 943         .num_asids = 4,
 944 };
 945
 946 #define TEGRA114_MC_RESET(_name, _control, _status, _bit)       \
 947         {                                                       \
 948                 .name = #_name,                                 \
 949                 .id = TEGRA114_MC_RESET_##_name,                \
 950                 .control = _control,                            \
 951                 .status = _status,                              \
 952                 .bit = _bit,                                    \
 953         }
 954
 955 static const struct tegra_mc_reset tegra114_mc_resets[] = {
 956         TEGRA114_MC_RESET(AVPC,     0x200, 0x204,  1),
 957         TEGRA114_MC_RESET(DC,       0x200, 0x204,  2),
 958         TEGRA114_MC_RESET(DCB,      0x200, 0x204,  3),
 959         TEGRA114_MC_RESET(EPP,      0x200, 0x204,  4),
 960         TEGRA114_MC_RESET(2D,       0x200, 0x204,  5),
 961         TEGRA114_MC_RESET(HC,       0x200, 0x204,  6),
 962         TEGRA114_MC_RESET(HDA,      0x200, 0x204,  7),
 963         TEGRA114_MC_RESET(ISP,      0x200, 0x204,  8),
 964         TEGRA114_MC_RESET(MPCORE,   0x200, 0x204,  9),
 965         TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
 966         TEGRA114_MC_RESET(MPE,      0x200, 0x204, 11),
 967         TEGRA114_MC_RESET(3D,       0x200, 0x204, 12),
 968         TEGRA114_MC_RESET(3D2,      0x200, 0x204, 13),
 969         TEGRA114_MC_RESET(PPCS,     0x200, 0x204, 14),
 970         TEGRA114_MC_RESET(VDE,      0x200, 0x204, 16),
 971         TEGRA114_MC_RESET(VI,       0x200, 0x204, 17),
 972 };
 973
 974 const struct tegra_mc_soc tegra114_mc_soc = {
 975         .clients = tegra114_mc_clients,
 976         .num_clients = ARRAY_SIZE(tegra114_mc_clients),
 977         .num_address_bits = 32,
 978         .atom_size = 32,
 979         .client_id_mask = 0x7f,
 980         .smmu = &tegra114_smmu_soc,
 981         .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
 982                    MC_INT_DECERR_EMEM,
 983         .reset_ops = &tegra_mc_reset_ops_common,
 984         .resets = tegra114_mc_resets,
 985         .num_resets = ARRAY_SIZE(tegra114_mc_resets),
 986 };