1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra114-mc.h>
13 static const struct tegra_mc_client tegra114_mc_clients[] = {
17 .swgroup = TEGRA_SWGROUP_PTC,
21 .swgroup = TEGRA_SWGROUP_DC,
35 .swgroup = TEGRA_SWGROUP_DCB,
49 .swgroup = TEGRA_SWGROUP_DC,
63 .swgroup = TEGRA_SWGROUP_DCB,
77 .swgroup = TEGRA_SWGROUP_DC,
91 .swgroup = TEGRA_SWGROUP_DCB,
105 .swgroup = TEGRA_SWGROUP_EPP,
119 .swgroup = TEGRA_SWGROUP_G2,
133 .swgroup = TEGRA_SWGROUP_G2,
147 .swgroup = TEGRA_SWGROUP_AVPC,
161 .swgroup = TEGRA_SWGROUP_DC,
174 .name = "displayhcb",
175 .swgroup = TEGRA_SWGROUP_DCB,
189 .swgroup = TEGRA_SWGROUP_NV,
203 .swgroup = TEGRA_SWGROUP_NV,
217 .swgroup = TEGRA_SWGROUP_G2,
231 .swgroup = TEGRA_SWGROUP_HDA,
244 .name = "host1xdmar",
245 .swgroup = TEGRA_SWGROUP_HC,
259 .swgroup = TEGRA_SWGROUP_HC,
273 .swgroup = TEGRA_SWGROUP_NV,
287 .swgroup = TEGRA_SWGROUP_MSENC,
300 .name = "ppcsahbdmar",
301 .swgroup = TEGRA_SWGROUP_PPCS,
314 .name = "ppcsahbslvr",
315 .swgroup = TEGRA_SWGROUP_PPCS,
329 .swgroup = TEGRA_SWGROUP_NV,
343 .swgroup = TEGRA_SWGROUP_VDE,
357 .swgroup = TEGRA_SWGROUP_VDE,
371 .swgroup = TEGRA_SWGROUP_VDE,
385 .swgroup = TEGRA_SWGROUP_VDE,
399 .swgroup = TEGRA_SWGROUP_MPCORELP,
409 .swgroup = TEGRA_SWGROUP_MPCORE,
419 .swgroup = TEGRA_SWGROUP_EPP,
433 .swgroup = TEGRA_SWGROUP_EPP,
447 .swgroup = TEGRA_SWGROUP_EPP,
461 .swgroup = TEGRA_SWGROUP_MSENC,
475 .swgroup = TEGRA_SWGROUP_VI,
489 .swgroup = TEGRA_SWGROUP_VI,
503 .swgroup = TEGRA_SWGROUP_VI,
517 .swgroup = TEGRA_SWGROUP_VI,
531 .swgroup = TEGRA_SWGROUP_G2,
545 .swgroup = TEGRA_SWGROUP_AVPC,
559 .swgroup = TEGRA_SWGROUP_NV,
573 .swgroup = TEGRA_SWGROUP_NV,
587 .swgroup = TEGRA_SWGROUP_HDA,
601 .swgroup = TEGRA_SWGROUP_HC,
615 .swgroup = TEGRA_SWGROUP_ISP,
629 .swgroup = TEGRA_SWGROUP_MPCORELP,
639 .swgroup = TEGRA_SWGROUP_MPCORE,
648 .name = "ppcsahbdmaw",
649 .swgroup = TEGRA_SWGROUP_PPCS,
662 .name = "ppcsahbslvw",
663 .swgroup = TEGRA_SWGROUP_PPCS,
677 .swgroup = TEGRA_SWGROUP_VDE,
691 .swgroup = TEGRA_SWGROUP_VDE,
705 .swgroup = TEGRA_SWGROUP_VDE,
719 .swgroup = TEGRA_SWGROUP_VDE,
732 .name = "xusb_hostr",
733 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
746 .name = "xusb_hostw",
747 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
761 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
775 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
789 .swgroup = TEGRA_SWGROUP_NV,
803 .swgroup = TEGRA_SWGROUP_NV,
817 .swgroup = TEGRA_SWGROUP_NV,
831 .swgroup = TEGRA_SWGROUP_NV,
845 .swgroup = TEGRA_SWGROUP_EMUCIF,
855 .swgroup = TEGRA_SWGROUP_EMUCIF,
865 .swgroup = TEGRA_SWGROUP_TSEC,
879 .swgroup = TEGRA_SWGROUP_TSEC,
893 static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
894 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
895 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
896 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
897 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
898 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
899 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
900 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
901 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
902 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
903 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
904 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
905 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
906 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
907 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
908 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
909 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
912 static const unsigned int tegra114_group_drm[] = {
919 static const struct tegra_smmu_group_soc tegra114_groups[] = {
922 .swgroups = tegra114_group_drm,
923 .num_swgroups = ARRAY_SIZE(tegra114_group_drm),
927 static const struct tegra_smmu_soc tegra114_smmu_soc = {
928 .clients = tegra114_mc_clients,
929 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
930 .swgroups = tegra114_swgroups,
931 .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
932 .groups = tegra114_groups,
933 .num_groups = ARRAY_SIZE(tegra114_groups),
934 .supports_round_robin_arbitration = false,
935 .supports_request_limit = false,
940 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \
943 .id = TEGRA114_MC_RESET_##_name, \
944 .control = _control, \
949 static const struct tegra_mc_reset tegra114_mc_resets[] = {
950 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
951 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
952 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
953 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
954 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
955 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
956 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
957 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
958 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
959 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
960 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
961 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
962 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
963 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
964 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
965 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
968 const struct tegra_mc_soc tegra114_mc_soc = {
969 .clients = tegra114_mc_clients,
970 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
971 .num_address_bits = 32,
973 .client_id_mask = 0x7f,
974 .smmu = &tegra114_smmu_soc,
975 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
977 .reset_ops = &tegra_mc_reset_ops_common,
978 .resets = tegra114_mc_resets,
979 .num_resets = ARRAY_SIZE(tegra114_mc_resets),