drivers/memory/tegra/tegra114.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra114-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const struct tegra_mc_client tegra114_mc_clients[] = {
  14         {
  15                 .id = 0x00,
  16                 .name = "ptcr",
  17                 .swgroup = TEGRA_SWGROUP_PTC,
  18                 .regs = {
  19                         .la = {
  20                                 .reg = 0x34c,
  21                                 .shift = 0,
  22                                 .mask = 0xff,
  23                                 .def = 0x0,
  24                         },
  25                 },
  26         }, {
  27                 .id = 0x01,
  28                 .name = "display0a",
  29                 .swgroup = TEGRA_SWGROUP_DC,
  30                 .regs = {
  31                         .smmu = {
  32                                 .reg = 0x228,
  33                                 .bit = 1,
  34                         },
  35                         .la = {
  36                                 .reg = 0x2e8,
  37                                 .shift = 0,
  38                                 .mask = 0xff,
  39                                 .def = 0x4e,
  40                         },
  41                 },
  42         }, {
  43                 .id = 0x02,
  44                 .name = "display0ab",
  45                 .swgroup = TEGRA_SWGROUP_DCB,
  46                 .regs = {
  47                         .smmu = {
  48                                 .reg = 0x228,
  49                                 .bit = 2,
  50                         },
  51                         .la = {
  52                                 .reg = 0x2f4,
  53                                 .shift = 0,
  54                                 .mask = 0xff,
  55                                 .def = 0x4e,
  56                         },
  57                 },
  58         }, {
  59                 .id = 0x03,
  60                 .name = "display0b",
  61                 .swgroup = TEGRA_SWGROUP_DC,
  62                 .regs = {
  63                         .smmu = {
  64                                 .reg = 0x228,
  65                                 .bit = 3,
  66                         },
  67                         .la = {
  68                                 .reg = 0x2e8,
  69                                 .shift = 16,
  70                                 .mask = 0xff,
  71                                 .def = 0x4e,
  72                         },
  73                 },
  74         }, {
  75                 .id = 0x04,
  76                 .name = "display0bb",
  77                 .swgroup = TEGRA_SWGROUP_DCB,
  78                 .regs = {
  79                         .smmu = {
  80                                 .reg = 0x228,
  81                                 .bit = 4,
  82                         },
  83                         .la = {
  84                                 .reg = 0x2f4,
  85                                 .shift = 16,
  86                                 .mask = 0xff,
  87                                 .def = 0x4e,
  88                         },
  89                 },
  90         }, {
  91                 .id = 0x05,
  92                 .name = "display0c",
  93                 .swgroup = TEGRA_SWGROUP_DC,
  94                 .regs = {
  95                         .smmu = {
  96                                 .reg = 0x228,
  97                                 .bit = 5,
  98                         },
  99                         .la = {
 100                                 .reg = 0x2ec,
 101                                 .shift = 0,
 102                                 .mask = 0xff,
 103                                 .def = 0x4e,
 104                         },
 105                 },
 106         }, {
 107                 .id = 0x06,
 108                 .name = "display0cb",
 109                 .swgroup = TEGRA_SWGROUP_DCB,
 110                 .regs = {
 111                         .smmu = {
 112                                 .reg = 0x228,
 113                                 .bit = 6,
 114                         },
 115                         .la = {
 116                                 .reg = 0x2f8,
 117                                 .shift = 0,
 118                                 .mask = 0xff,
 119                                 .def = 0x4e,
 120                         },
 121                 },
 122         }, {
 123                 .id = 0x09,
 124                 .name = "eppup",
 125                 .swgroup = TEGRA_SWGROUP_EPP,
 126                 .regs = {
 127                         .smmu = {
 128                                 .reg = 0x228,
 129                                 .bit = 9,
 130                         },
 131                         .la = {
 132                                 .reg = 0x300,
 133                                 .shift = 0,
 134                                 .mask = 0xff,
 135                                 .def = 0x33,
 136                         },
 137                 },
 138         }, {
 139                 .id = 0x0a,
 140                 .name = "g2pr",
 141                 .swgroup = TEGRA_SWGROUP_G2,
 142                 .regs = {
 143                         .smmu = {
 144                                 .reg = 0x228,
 145                                 .bit = 10,
 146                         },
 147                         .la = {
 148                                 .reg = 0x308,
 149                                 .shift = 0,
 150                                 .mask = 0xff,
 151                                 .def = 0x09,
 152                         },
 153                 },
 154         }, {
 155                 .id = 0x0b,
 156                 .name = "g2sr",
 157                 .swgroup = TEGRA_SWGROUP_G2,
 158                 .regs = {
 159                         .smmu = {
 160                                 .reg = 0x228,
 161                                 .bit = 11,
 162                         },
 163                         .la = {
 164                                 .reg = 0x308,
 165                                 .shift = 16,
 166                                 .mask = 0xff,
 167                                 .def = 0x09,
 168                         },
 169                 },
 170         }, {
 171                 .id = 0x0f,
 172                 .name = "avpcarm7r",
 173                 .swgroup = TEGRA_SWGROUP_AVPC,
 174                 .regs = {
 175                         .smmu = {
 176                                 .reg = 0x228,
 177                                 .bit = 15,
 178                         },
 179                         .la = {
 180                                 .reg = 0x2e4,
 181                                 .shift = 0,
 182                                 .mask = 0xff,
 183                                 .def = 0x04,
 184                         },
 185                 },
 186         }, {
 187                 .id = 0x10,
 188                 .name = "displayhc",
 189                 .swgroup = TEGRA_SWGROUP_DC,
 190                 .regs = {
 191                         .smmu = {
 192                                 .reg = 0x228,
 193                                 .bit = 16,
 194                         },
 195                         .la = {
 196                                 .reg = 0x2f0,
 197                                 .shift = 0,
 198                                 .mask = 0xff,
 199                                 .def = 0x68,
 200                         },
 201                 },
 202         }, {
 203                 .id = 0x11,
 204                 .name = "displayhcb",
 205                 .swgroup = TEGRA_SWGROUP_DCB,
 206                 .regs = {
 207                         .smmu = {
 208                                 .reg = 0x228,
 209                                 .bit = 17,
 210                         },
 211                         .la = {
 212                                 .reg = 0x2fc,
 213                                 .shift = 0,
 214                                 .mask = 0xff,
 215                                 .def = 0x68,
 216                         },
 217                 },
 218         }, {
 219                 .id = 0x12,
 220                 .name = "fdcdrd",
 221                 .swgroup = TEGRA_SWGROUP_NV,
 222                 .regs = {
 223                         .smmu = {
 224                                 .reg = 0x228,
 225                                 .bit = 18,
 226                         },
 227                         .la = {
 228                                 .reg = 0x334,
 229                                 .shift = 0,
 230                                 .mask = 0xff,
 231                                 .def = 0x0c,
 232                         },
 233                 },
 234         }, {
 235                 .id = 0x13,
 236                 .name = "fdcdrd2",
 237                 .swgroup = TEGRA_SWGROUP_NV,
 238                 .regs = {
 239                         .smmu = {
 240                                 .reg = 0x228,
 241                                 .bit = 19,
 242                         },
 243                         .la = {
 244                                 .reg = 0x33c,
 245                                 .shift = 0,
 246                                 .mask = 0xff,
 247                                 .def = 0x0c,
 248                         },
 249                 },
 250         }, {
 251                 .id = 0x14,
 252                 .name = "g2dr",
 253                 .swgroup = TEGRA_SWGROUP_G2,
 254                 .regs = {
 255                         .smmu = {
 256                                 .reg = 0x228,
 257                                 .bit = 20,
 258                         },
 259                         .la = {
 260                                 .reg = 0x30c,
 261                                 .shift = 0,
 262                                 .mask = 0xff,
 263                                 .def = 0x0a,
 264                         },
 265                 },
 266         }, {
 267                 .id = 0x15,
 268                 .name = "hdar",
 269                 .swgroup = TEGRA_SWGROUP_HDA,
 270                 .regs = {
 271                         .smmu = {
 272                                 .reg = 0x228,
 273                                 .bit = 21,
 274                         },
 275                         .la = {
 276                                 .reg = 0x318,
 277                                 .shift = 0,
 278                                 .mask = 0xff,
 279                                 .def = 0xff,
 280                         },
 281                 },
 282         }, {
 283                 .id = 0x16,
 284                 .name = "host1xdmar",
 285                 .swgroup = TEGRA_SWGROUP_HC,
 286                 .regs = {
 287                         .smmu = {
 288                                 .reg = 0x228,
 289                                 .bit = 22,
 290                         },
 291                         .la = {
 292                                 .reg = 0x310,
 293                                 .shift = 0,
 294                                 .mask = 0xff,
 295                                 .def = 0x10,
 296                         },
 297                 },
 298         }, {
 299                 .id = 0x17,
 300                 .name = "host1xr",
 301                 .swgroup = TEGRA_SWGROUP_HC,
 302                 .regs = {
 303                         .smmu = {
 304                                 .reg = 0x228,
 305                                 .bit = 23,
 306                         },
 307                         .la = {
 308                                 .reg = 0x310,
 309                                 .shift = 16,
 310                                 .mask = 0xff,
 311                                 .def = 0xa5,
 312                         },
 313                 },
 314         }, {
 315                 .id = 0x18,
 316                 .name = "idxsrd",
 317                 .swgroup = TEGRA_SWGROUP_NV,
 318                 .regs = {
 319                         .smmu = {
 320                                 .reg = 0x228,
 321                                 .bit = 24,
 322                         },
 323                         .la = {
 324                                 .reg = 0x334,
 325                                 .shift = 16,
 326                                 .mask = 0xff,
 327                                 .def = 0x0b,
 328                         },
 329                 },
 330         }, {
 331                 .id = 0x1c,
 332                 .name = "msencsrd",
 333                 .swgroup = TEGRA_SWGROUP_MSENC,
 334                 .regs = {
 335                         .smmu = {
 336                                 .reg = 0x228,
 337                                 .bit = 28,
 338                         },
 339                         .la = {
 340                                 .reg = 0x328,
 341                                 .shift = 0,
 342                                 .mask = 0xff,
 343                                 .def = 0x80,
 344                         },
 345                 },
 346         }, {
 347                 .id = 0x1d,
 348                 .name = "ppcsahbdmar",
 349                 .swgroup = TEGRA_SWGROUP_PPCS,
 350                 .regs = {
 351                         .smmu = {
 352                                 .reg = 0x228,
 353                                 .bit = 29,
 354                         },
 355                         .la = {
 356                                 .reg = 0x344,
 357                                 .shift = 0,
 358                                 .mask = 0xff,
 359                                 .def = 0x50,
 360                         },
 361                 },
 362         }, {
 363                 .id = 0x1e,
 364                 .name = "ppcsahbslvr",
 365                 .swgroup = TEGRA_SWGROUP_PPCS,
 366                 .regs = {
 367                         .smmu = {
 368                                 .reg = 0x228,
 369                                 .bit = 30,
 370                         },
 371                         .la = {
 372                                 .reg = 0x344,
 373                                 .shift = 16,
 374                                 .mask = 0xff,
 375                                 .def = 0xe8,
 376                         },
 377                 },
 378         }, {
 379                 .id = 0x20,
 380                 .name = "texl2srd",
 381                 .swgroup = TEGRA_SWGROUP_NV,
 382                 .regs = {
 383                         .smmu = {
 384                                 .reg = 0x22c,
 385                                 .bit = 0,
 386                         },
 387                         .la = {
 388                                 .reg = 0x338,
 389                                 .shift = 0,
 390                                 .mask = 0xff,
 391                                 .def = 0x0c,
 392                         },
 393                 },
 394         }, {
 395                 .id = 0x22,
 396                 .name = "vdebsevr",
 397                 .swgroup = TEGRA_SWGROUP_VDE,
 398                 .regs = {
 399                         .smmu = {
 400                                 .reg = 0x22c,
 401                                 .bit = 2,
 402                         },
 403                         .la = {
 404                                 .reg = 0x354,
 405                                 .shift = 0,
 406                                 .mask = 0xff,
 407                                 .def = 0xff,
 408                         },
 409                 },
 410         }, {
 411                 .id = 0x23,
 412                 .name = "vdember",
 413                 .swgroup = TEGRA_SWGROUP_VDE,
 414                 .regs = {
 415                         .smmu = {
 416                                 .reg = 0x22c,
 417                                 .bit = 3,
 418                         },
 419                         .la = {
 420                                 .reg = 0x354,
 421                                 .shift = 16,
 422                                 .mask = 0xff,
 423                                 .def = 0xff,
 424                         },
 425                 },
 426         }, {
 427                 .id = 0x24,
 428                 .name = "vdemcer",
 429                 .swgroup = TEGRA_SWGROUP_VDE,
 430                 .regs = {
 431                         .smmu = {
 432                                 .reg = 0x22c,
 433                                 .bit = 4,
 434                         },
 435                         .la = {
 436                                 .reg = 0x358,
 437                                 .shift = 0,
 438                                 .mask = 0xff,
 439                                 .def = 0xb8,
 440                         },
 441                 },
 442         }, {
 443                 .id = 0x25,
 444                 .name = "vdetper",
 445                 .swgroup = TEGRA_SWGROUP_VDE,
 446                 .regs = {
 447                         .smmu = {
 448                                 .reg = 0x22c,
 449                                 .bit = 5,
 450                         },
 451                         .la = {
 452                                 .reg = 0x358,
 453                                 .shift = 16,
 454                                 .mask = 0xff,
 455                                 .def = 0xee,
 456                         },
 457                 },
 458         }, {
 459                 .id = 0x26,
 460                 .name = "mpcorelpr",
 461                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 462                 .regs = {
 463                         .la = {
 464                                 .reg = 0x324,
 465                                 .shift = 0,
 466                                 .mask = 0xff,
 467                                 .def = 0x04,
 468                         },
 469                 },
 470         }, {
 471                 .id = 0x27,
 472                 .name = "mpcorer",
 473                 .swgroup = TEGRA_SWGROUP_MPCORE,
 474                 .regs = {
 475                         .la = {
 476                                 .reg = 0x320,
 477                                 .shift = 0,
 478                                 .mask = 0xff,
 479                                 .def = 0x04,
 480                         },
 481                 },
 482         }, {
 483                 .id = 0x28,
 484                 .name = "eppu",
 485                 .swgroup = TEGRA_SWGROUP_EPP,
 486                 .regs = {
 487                         .smmu = {
 488                                 .reg = 0x22c,
 489                                 .bit = 8,
 490                         },
 491                         .la = {
 492                                 .reg = 0x300,
 493                                 .shift = 16,
 494                                 .mask = 0xff,
 495                                 .def = 0x33,
 496                         },
 497                 },
 498         }, {
 499                 .id = 0x29,
 500                 .name = "eppv",
 501                 .swgroup = TEGRA_SWGROUP_EPP,
 502                 .regs = {
 503                         .smmu = {
 504                                 .reg = 0x22c,
 505                                 .bit = 9,
 506                         },
 507                         .la = {
 508                                 .reg = 0x304,
 509                                 .shift = 0,
 510                                 .mask = 0xff,
 511                                 .def = 0x6c,
 512                         },
 513                 },
 514         }, {
 515                 .id = 0x2a,
 516                 .name = "eppy",
 517                 .swgroup = TEGRA_SWGROUP_EPP,
 518                 .regs = {
 519                         .smmu = {
 520                                 .reg = 0x22c,
 521                                 .bit = 10,
 522                         },
 523                         .la = {
 524                                 .reg = 0x304,
 525                                 .shift = 16,
 526                                 .mask = 0xff,
 527                                 .def = 0x6c,
 528                         },
 529                 },
 530         }, {
 531                 .id = 0x2b,
 532                 .name = "msencswr",
 533                 .swgroup = TEGRA_SWGROUP_MSENC,
 534                 .regs = {
 535                         .smmu = {
 536                                 .reg = 0x22c,
 537                                 .bit = 11,
 538                         },
 539                         .la = {
 540                                 .reg = 0x328,
 541                                 .shift = 16,
 542                                 .mask = 0xff,
 543                                 .def = 0x80,
 544                         },
 545                 },
 546         }, {
 547                 .id = 0x2c,
 548                 .name = "viwsb",
 549                 .swgroup = TEGRA_SWGROUP_VI,
 550                 .regs = {
 551                         .smmu = {
 552                                 .reg = 0x22c,
 553                                 .bit = 12,
 554                         },
 555                         .la = {
 556                                 .reg = 0x364,
 557                                 .shift = 0,
 558                                 .mask = 0xff,
 559                                 .def = 0x47,
 560                         },
 561                 },
 562         }, {
 563                 .id = 0x2d,
 564                 .name = "viwu",
 565                 .swgroup = TEGRA_SWGROUP_VI,
 566                 .regs = {
 567                         .smmu = {
 568                                 .reg = 0x22c,
 569                                 .bit = 13,
 570                         },
 571                         .la = {
 572                                 .reg = 0x368,
 573                                 .shift = 0,
 574                                 .mask = 0xff,
 575                                 .def = 0xff,
 576                         },
 577                 },
 578         }, {
 579                 .id = 0x2e,
 580                 .name = "viwv",
 581                 .swgroup = TEGRA_SWGROUP_VI,
 582                 .regs = {
 583                         .smmu = {
 584                                 .reg = 0x22c,
 585                                 .bit = 14,
 586                         },
 587                         .la = {
 588                                 .reg = 0x368,
 589                                 .shift = 16,
 590                                 .mask = 0xff,
 591                                 .def = 0xff,
 592                         },
 593                 },
 594         }, {
 595                 .id = 0x2f,
 596                 .name = "viwy",
 597                 .swgroup = TEGRA_SWGROUP_VI,
 598                 .regs = {
 599                         .smmu = {
 600                                 .reg = 0x22c,
 601                                 .bit = 15,
 602                         },
 603                         .la = {
 604                                 .reg = 0x36c,
 605                                 .shift = 0,
 606                                 .mask = 0xff,
 607                                 .def = 0x47,
 608                         },
 609                 },
 610         }, {
 611                 .id = 0x30,
 612                 .name = "g2dw",
 613                 .swgroup = TEGRA_SWGROUP_G2,
 614                 .regs = {
 615                         .smmu = {
 616                                 .reg = 0x22c,
 617                                 .bit = 16,
 618                         },
 619                         .la = {
 620                                 .reg = 0x30c,
 621                                 .shift = 16,
 622                                 .mask = 0xff,
 623                                 .def = 0x9,
 624                         },
 625                 },
 626         }, {
 627                 .id = 0x32,
 628                 .name = "avpcarm7w",
 629                 .swgroup = TEGRA_SWGROUP_AVPC,
 630                 .regs = {
 631                         .smmu = {
 632                                 .reg = 0x22c,
 633                                 .bit = 18,
 634                         },
 635                         .la = {
 636                                 .reg = 0x2e4,
 637                                 .shift = 16,
 638                                 .mask = 0xff,
 639                                 .def = 0x0e,
 640                         },
 641                 },
 642         }, {
 643                 .id = 0x33,
 644                 .name = "fdcdwr",
 645                 .swgroup = TEGRA_SWGROUP_NV,
 646                 .regs = {
 647                         .smmu = {
 648                                 .reg = 0x22c,
 649                                 .bit = 19,
 650                         },
 651                         .la = {
 652                                 .reg = 0x338,
 653                                 .shift = 16,
 654                                 .mask = 0xff,
 655                                 .def = 0x10,
 656                         },
 657                 },
 658         }, {
 659                 .id = 0x34,
 660                 .name = "fdcdwr2",
 661                 .swgroup = TEGRA_SWGROUP_NV,
 662                 .regs = {
 663                         .smmu = {
 664                                 .reg = 0x22c,
 665                                 .bit = 20,
 666                         },
 667                         .la = {
 668                                 .reg = 0x340,
 669                                 .shift = 0,
 670                                 .mask = 0xff,
 671                                 .def = 0x10,
 672                         },
 673                 },
 674         }, {
 675                 .id = 0x35,
 676                 .name = "hdaw",
 677                 .swgroup = TEGRA_SWGROUP_HDA,
 678                 .regs = {
 679                         .smmu = {
 680                                 .reg = 0x22c,
 681                                 .bit = 21,
 682                         },
 683                         .la = {
 684                                 .reg = 0x318,
 685                                 .shift = 16,
 686                                 .mask = 0xff,
 687                                 .def = 0xff,
 688                         },
 689                 },
 690         }, {
 691                 .id = 0x36,
 692                 .name = "host1xw",
 693                 .swgroup = TEGRA_SWGROUP_HC,
 694                 .regs = {
 695                         .smmu = {
 696                                 .reg = 0x22c,
 697                                 .bit = 22,
 698                         },
 699                         .la = {
 700                                 .reg = 0x314,
 701                                 .shift = 0,
 702                                 .mask = 0xff,
 703                                 .def = 0x25,
 704                         },
 705                 },
 706         }, {
 707                 .id = 0x37,
 708                 .name = "ispw",
 709                 .swgroup = TEGRA_SWGROUP_ISP,
 710                 .regs = {
 711                         .smmu = {
 712                                 .reg = 0x22c,
 713                                 .bit = 23,
 714                         },
 715                         .la = {
 716                                 .reg = 0x31c,
 717                                 .shift = 0,
 718                                 .mask = 0xff,
 719                                 .def = 0xff,
 720                         },
 721                 },
 722         }, {
 723                 .id = 0x38,
 724                 .name = "mpcorelpw",
 725                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 726                 .regs = {
 727                         .la = {
 728                                 .reg = 0x324,
 729                                 .shift = 16,
 730                                 .mask = 0xff,
 731                                 .def = 0x80,
 732                         },
 733                 },
 734         }, {
 735                 .id = 0x39,
 736                 .name = "mpcorew",
 737                 .swgroup = TEGRA_SWGROUP_MPCORE,
 738                 .regs = {
 739                         .la = {
 740                                 .reg = 0x320,
 741                                 .shift = 16,
 742                                 .mask = 0xff,
 743                                 .def = 0x0e,
 744                         },
 745                 },
 746         }, {
 747                 .id = 0x3b,
 748                 .name = "ppcsahbdmaw",
 749                 .swgroup = TEGRA_SWGROUP_PPCS,
 750                 .regs = {
 751                         .smmu = {
 752                                 .reg = 0x22c,
 753                                 .bit = 27,
 754                         },
 755                         .la = {
 756                                 .reg = 0x348,
 757                                 .shift = 0,
 758                                 .mask = 0xff,
 759                                 .def = 0xa5,
 760                         },
 761                 },
 762         }, {
 763                 .id = 0x3c,
 764                 .name = "ppcsahbslvw",
 765                 .swgroup = TEGRA_SWGROUP_PPCS,
 766                 .regs = {
 767                         .smmu = {
 768                                 .reg = 0x22c,
 769                                 .bit = 28,
 770                         },
 771                         .la = {
 772                                 .reg = 0x348,
 773                                 .shift = 16,
 774                                 .mask = 0xff,
 775                                 .def = 0xe8,
 776                         },
 777                 },
 778         }, {
 779                 .id = 0x3e,
 780                 .name = "vdebsevw",
 781                 .swgroup = TEGRA_SWGROUP_VDE,
 782                 .regs = {
 783                         .smmu = {
 784                                 .reg = 0x22c,
 785                                 .bit = 30,
 786                         },
 787                         .la = {
 788                                 .reg = 0x35c,
 789                                 .shift = 0,
 790                                 .mask = 0xff,
 791                                 .def = 0xff,
 792                         },
 793                 },
 794         }, {
 795                 .id = 0x3f,
 796                 .name = "vdedbgw",
 797                 .swgroup = TEGRA_SWGROUP_VDE,
 798                 .regs = {
 799                         .smmu = {
 800                                 .reg = 0x22c,
 801                                 .bit = 31,
 802                         },
 803                         .la = {
 804                                 .reg = 0x35c,
 805                                 .shift = 16,
 806                                 .mask = 0xff,
 807                                 .def = 0xff,
 808                         },
 809                 },
 810         }, {
 811                 .id = 0x40,
 812                 .name = "vdembew",
 813                 .swgroup = TEGRA_SWGROUP_VDE,
 814                 .regs = {
 815                         .smmu = {
 816                                 .reg = 0x230,
 817                                 .bit = 0,
 818                         },
 819                         .la = {
 820                                 .reg = 0x360,
 821                                 .shift = 0,
 822                                 .mask = 0xff,
 823                                 .def = 0x89,
 824                         },
 825                 },
 826         }, {
 827                 .id = 0x41,
 828                 .name = "vdetpmw",
 829                 .swgroup = TEGRA_SWGROUP_VDE,
 830                 .regs = {
 831                         .smmu = {
 832                                 .reg = 0x230,
 833                                 .bit = 1,
 834                         },
 835                         .la = {
 836                                 .reg = 0x360,
 837                                 .shift = 16,
 838                                 .mask = 0xff,
 839                                 .def = 0x59,
 840                         },
 841                 },
 842         }, {
 843                 .id = 0x4a,
 844                 .name = "xusb_hostr",
 845                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 846                 .regs = {
 847                         .smmu = {
 848                                 .reg = 0x230,
 849                                 .bit = 10,
 850                         },
 851                         .la = {
 852                                 .reg = 0x37c,
 853                                 .shift = 0,
 854                                 .mask = 0xff,
 855                                 .def = 0xa5,
 856                         },
 857                 },
 858         }, {
 859                 .id = 0x4b,
 860                 .name = "xusb_hostw",
 861                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 862                 .regs = {
 863                         .smmu = {
 864                                 .reg = 0x230,
 865                                 .bit = 11,
 866                         },
 867                         .la = {
 868                                 .reg = 0x37c,
 869                                 .shift = 16,
 870                                 .mask = 0xff,
 871                                 .def = 0xa5,
 872                         },
 873                 },
 874         }, {
 875                 .id = 0x4c,
 876                 .name = "xusb_devr",
 877                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 878                 .regs = {
 879                         .smmu = {
 880                                 .reg = 0x230,
 881                                 .bit = 12,
 882                         },
 883                         .la = {
 884                                 .reg = 0x380,
 885                                 .shift = 0,
 886                                 .mask = 0xff,
 887                                 .def = 0xa5,
 888                         },
 889                 },
 890         }, {
 891                 .id = 0x4d,
 892                 .name = "xusb_devw",
 893                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 894                 .regs = {
 895                         .smmu = {
 896                                 .reg = 0x230,
 897                                 .bit = 13,
 898                         },
 899                         .la = {
 900                                 .reg = 0x380,
 901                                 .shift = 16,
 902                                 .mask = 0xff,
 903                                 .def = 0xa5,
 904                         },
 905                 },
 906         }, {
 907                 .id = 0x4e,
 908                 .name = "fdcdwr3",
 909                 .swgroup = TEGRA_SWGROUP_NV,
 910                 .regs = {
 911                         .smmu = {
 912                                 .reg = 0x230,
 913                                 .bit = 14,
 914                         },
 915                         .la = {
 916                                 .reg = 0x388,
 917                                 .shift = 0,
 918                                 .mask = 0xff,
 919                                 .def = 0x10,
 920                         },
 921                 },
 922         }, {
 923                 .id = 0x4f,
 924                 .name = "fdcdrd3",
 925                 .swgroup = TEGRA_SWGROUP_NV,
 926                 .regs = {
 927                         .smmu = {
 928                                 .reg = 0x230,
 929                                 .bit = 15,
 930                         },
 931                         .la = {
 932                                 .reg = 0x384,
 933                                 .shift = 0,
 934                                 .mask = 0xff,
 935                                 .def = 0x0c,
 936                         },
 937                 },
 938         }, {
 939                 .id = 0x50,
 940                 .name = "fdcwr4",
 941                 .swgroup = TEGRA_SWGROUP_NV,
 942                 .regs = {
 943                         .smmu = {
 944                                 .reg = 0x230,
 945                                 .bit = 16,
 946                         },
 947                         .la = {
 948                                 .reg = 0x388,
 949                                 .shift = 16,
 950                                 .mask = 0xff,
 951                                 .def = 0x10,
 952                         },
 953                 },
 954         }, {
 955                 .id = 0x51,
 956                 .name = "fdcrd4",
 957                 .swgroup = TEGRA_SWGROUP_NV,
 958                 .regs = {
 959                         .smmu = {
 960                                 .reg = 0x230,
 961                                 .bit = 17,
 962                         },
 963                         .la = {
 964                                 .reg = 0x384,
 965                                 .shift = 16,
 966                                 .mask = 0xff,
 967                                 .def = 0x0c,
 968                         },
 969                 },
 970         }, {
 971                 .id = 0x52,
 972                 .name = "emucifr",
 973                 .swgroup = TEGRA_SWGROUP_EMUCIF,
 974                 .regs = {
 975                         .la = {
 976                                 .reg = 0x38c,
 977                                 .shift = 0,
 978                                 .mask = 0xff,
 979                                 .def = 0x04,
 980                         },
 981                 },
 982         }, {
 983                 .id = 0x53,
 984                 .name = "emucifw",
 985                 .swgroup = TEGRA_SWGROUP_EMUCIF,
 986                 .regs = {
 987                         .la = {
 988                                 .reg = 0x38c,
 989                                 .shift = 16,
 990                                 .mask = 0xff,
 991                                 .def = 0x0e,
 992                         },
 993                 },
 994         }, {
 995                 .id = 0x54,
 996                 .name = "tsecsrd",
 997                 .swgroup = TEGRA_SWGROUP_TSEC,
 998                 .regs = {
 999                         .smmu = {
1000                                 .reg = 0x230,
1001                                 .bit = 20,
1002                         },
1003                         .la = {
1004                                 .reg = 0x390,
1005                                 .shift = 0,
1006                                 .mask = 0xff,
1007                                 .def = 0x50,
1008                         },
1009                 },
1010         }, {
1011                 .id = 0x55,
1012                 .name = "tsecswr",
1013                 .swgroup = TEGRA_SWGROUP_TSEC,
1014                 .regs = {
1015                         .smmu = {
1016                                 .reg = 0x230,
1017                                 .bit = 21,
1018                         },
1019                         .la = {
1020                                 .reg = 0x390,
1021                                 .shift = 16,
1022                                 .mask = 0xff,
1023                                 .def = 0x50,
1024                         },
1025                 },
1026         },
1027 };
1028
1029 static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
1030         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
1031         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
1032         { .name = "epp",       .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },
1033         { .name = "g2",        .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },
1034         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
1035         { .name = "nv",        .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },
1036         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
1037         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
1038         { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
1039         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
1040         { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
1041         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
1042         { .name = "isp",       .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },
1043         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1044         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
1045         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
1046 };
1047
1048 static const unsigned int tegra114_group_drm[] = {
1049         TEGRA_SWGROUP_DC,
1050         TEGRA_SWGROUP_DCB,
1051         TEGRA_SWGROUP_G2,
1052         TEGRA_SWGROUP_NV,
1053 };
1054
1055 static const struct tegra_smmu_group_soc tegra114_groups[] = {
1056         {
1057                 .name = "drm",
1058                 .swgroups = tegra114_group_drm,
1059                 .num_swgroups = ARRAY_SIZE(tegra114_group_drm),
1060         },
1061 };
1062
1063 static const struct tegra_smmu_soc tegra114_smmu_soc = {
1064         .clients = tegra114_mc_clients,
1065         .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1066         .swgroups = tegra114_swgroups,
1067         .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
1068         .groups = tegra114_groups,
1069         .num_groups = ARRAY_SIZE(tegra114_groups),
1070         .supports_round_robin_arbitration = false,
1071         .supports_request_limit = false,
1072         .num_tlb_lines = 32,
1073         .num_asids = 4,
1074 };
1075
1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit)       \
1077         {                                                       \
1078                 .name = #_name,                                 \
1079                 .id = TEGRA114_MC_RESET_##_name,                \
1080                 .control = _control,                            \
1081                 .status = _status,                              \
1082                 .bit = _bit,                                    \
1083         }
1084
1085 static const struct tegra_mc_reset tegra114_mc_resets[] = {
1086         TEGRA114_MC_RESET(AVPC,     0x200, 0x204,  1),
1087         TEGRA114_MC_RESET(DC,       0x200, 0x204,  2),
1088         TEGRA114_MC_RESET(DCB,      0x200, 0x204,  3),
1089         TEGRA114_MC_RESET(EPP,      0x200, 0x204,  4),
1090         TEGRA114_MC_RESET(2D,       0x200, 0x204,  5),
1091         TEGRA114_MC_RESET(HC,       0x200, 0x204,  6),
1092         TEGRA114_MC_RESET(HDA,      0x200, 0x204,  7),
1093         TEGRA114_MC_RESET(ISP,      0x200, 0x204,  8),
1094         TEGRA114_MC_RESET(MPCORE,   0x200, 0x204,  9),
1095         TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1096         TEGRA114_MC_RESET(MPE,      0x200, 0x204, 11),
1097         TEGRA114_MC_RESET(3D,       0x200, 0x204, 12),
1098         TEGRA114_MC_RESET(3D2,      0x200, 0x204, 13),
1099         TEGRA114_MC_RESET(PPCS,     0x200, 0x204, 14),
1100         TEGRA114_MC_RESET(VDE,      0x200, 0x204, 16),
1101         TEGRA114_MC_RESET(VI,       0x200, 0x204, 17),
1102 };
1103
1104 const struct tegra_mc_soc tegra114_mc_soc = {
1105         .clients = tegra114_mc_clients,
1106         .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1107         .num_address_bits = 32,
1108         .atom_size = 32,
1109         .client_id_mask = 0x7f,
1110         .smmu = &tegra114_smmu_soc,
1111         .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1112                    MC_INT_DECERR_EMEM,
1113         .reset_ops = &tegra_mc_reset_ops_common,
1114         .resets = tegra114_mc_resets,
1115         .num_resets = ARRAY_SIZE(tegra114_mc_resets),
1116         .ops = &tegra30_mc_ops,
1117 };