2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
18 #include <soc/tegra/fuse.h>
22 #define MC_INTSTATUS 0x000
24 #define MC_INTMASK 0x004
26 #define MC_ERR_STATUS 0x08
27 #define MC_ERR_STATUS_TYPE_SHIFT 28
28 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
29 #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
30 #define MC_ERR_STATUS_READABLE (1 << 27)
31 #define MC_ERR_STATUS_WRITABLE (1 << 26)
32 #define MC_ERR_STATUS_NONSECURE (1 << 25)
33 #define MC_ERR_STATUS_ADR_HI_SHIFT 20
34 #define MC_ERR_STATUS_ADR_HI_MASK 0x3
35 #define MC_ERR_STATUS_SECURITY (1 << 17)
36 #define MC_ERR_STATUS_RW (1 << 16)
38 #define MC_ERR_ADR 0x0c
40 #define MC_EMEM_ARB_CFG 0x90
41 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
42 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
43 #define MC_EMEM_ARB_MISC0 0xd8
45 #define MC_EMEM_ADR_CFG 0x54
46 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
48 static const struct of_device_id tegra_mc_of_match[] = {
49 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
50 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
52 #ifdef CONFIG_ARCH_TEGRA_114_SOC
53 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
55 #ifdef CONFIG_ARCH_TEGRA_124_SOC
56 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
58 #ifdef CONFIG_ARCH_TEGRA_132_SOC
59 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
61 #ifdef CONFIG_ARCH_TEGRA_210_SOC
62 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
66 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
68 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
70 unsigned long long tick;
74 /* compute the number of MC clock cycles per tick */
75 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
76 do_div(tick, NSEC_PER_SEC);
78 value = readl(mc->regs + MC_EMEM_ARB_CFG);
79 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
80 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
81 writel(value, mc->regs + MC_EMEM_ARB_CFG);
83 /* write latency allowance defaults */
84 for (i = 0; i < mc->soc->num_clients; i++) {
85 const struct tegra_mc_la *la = &mc->soc->clients[i].la;
88 value = readl(mc->regs + la->reg);
89 value &= ~(la->mask << la->shift);
90 value |= (la->def & la->mask) << la->shift;
91 writel(value, mc->regs + la->reg);
97 void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
100 struct tegra_mc_timing *timing = NULL;
102 for (i = 0; i < mc->num_timings; i++) {
103 if (mc->timings[i].rate == rate) {
104 timing = &mc->timings[i];
110 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
115 for (i = 0; i < mc->soc->num_emem_regs; ++i)
116 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
119 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
123 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
124 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
130 static int load_one_timing(struct tegra_mc *mc,
131 struct tegra_mc_timing *timing,
132 struct device_node *node)
137 err = of_property_read_u32(node, "clock-frequency", &tmp);
140 "timing %s: failed to read rate\n", node->name);
145 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
146 sizeof(u32), GFP_KERNEL);
147 if (!timing->emem_data)
150 err = of_property_read_u32_array(node, "nvidia,emem-configuration",
152 mc->soc->num_emem_regs);
155 "timing %s: failed to read EMEM configuration\n",
163 static int load_timings(struct tegra_mc *mc, struct device_node *node)
165 struct device_node *child;
166 struct tegra_mc_timing *timing;
167 int child_count = of_get_child_count(node);
170 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
175 mc->num_timings = child_count;
177 for_each_child_of_node(node, child) {
178 timing = &mc->timings[i++];
180 err = load_one_timing(mc, timing, child);
190 static int tegra_mc_setup_timings(struct tegra_mc *mc)
192 struct device_node *node;
193 u32 ram_code, node_ram_code;
196 ram_code = tegra_read_ram_code();
200 for_each_child_of_node(mc->dev->of_node, node) {
201 err = of_property_read_u32(node, "nvidia,ram-code",
203 if (err || (node_ram_code != ram_code))
206 err = load_timings(mc, node);
213 if (mc->num_timings == 0)
215 "no memory timings for RAM code %u registered\n",
221 static const char *const status_names[32] = {
222 [ 1] = "External interrupt",
223 [ 6] = "EMEM address decode error",
224 [ 8] = "Security violation",
225 [ 9] = "EMEM arbitration error",
227 [11] = "Invalid APB ASID update",
228 [12] = "VPR violation",
229 [13] = "Secure carveout violation",
230 [16] = "MTS carveout violation",
233 static const char *const error_names[8] = {
234 [2] = "EMEM decode error",
235 [3] = "TrustZone violation",
236 [4] = "Carveout violation",
237 [6] = "SMMU translation error",
240 static irqreturn_t tegra_mc_irq(int irq, void *data)
242 struct tegra_mc *mc = data;
243 unsigned long status;
246 /* mask all interrupts to avoid flooding */
247 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
251 for_each_set_bit(bit, &status, 32) {
252 const char *error = status_names[bit] ?: "unknown";
253 const char *client = "unknown", *desc;
254 const char *direction, *secure;
255 phys_addr_t addr = 0;
261 value = mc_readl(mc, MC_ERR_STATUS);
263 #ifdef CONFIG_PHYS_ADDR_T_64BIT
264 if (mc->soc->num_address_bits > 32) {
265 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
266 MC_ERR_STATUS_ADR_HI_MASK);
271 if (value & MC_ERR_STATUS_RW)
276 if (value & MC_ERR_STATUS_SECURITY)
281 id = value & mc->soc->client_id_mask;
283 for (i = 0; i < mc->soc->num_clients; i++) {
284 if (mc->soc->clients[i].id == id) {
285 client = mc->soc->clients[i].name;
290 type = (value & MC_ERR_STATUS_TYPE_MASK) >>
291 MC_ERR_STATUS_TYPE_SHIFT;
292 desc = error_names[type];
294 switch (value & MC_ERR_STATUS_TYPE_MASK) {
295 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
299 if (value & MC_ERR_STATUS_READABLE)
304 if (value & MC_ERR_STATUS_WRITABLE)
309 if (value & MC_ERR_STATUS_NONSECURE)
323 value = mc_readl(mc, MC_ERR_ADR);
326 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
327 client, secure, direction, &addr, error,
331 /* clear interrupts */
332 mc_writel(mc, status, MC_INTSTATUS);
337 static int tegra_mc_probe(struct platform_device *pdev)
339 const struct of_device_id *match;
340 struct resource *res;
344 match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
348 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
352 platform_set_drvdata(pdev, mc);
353 mc->soc = match->data;
354 mc->dev = &pdev->dev;
356 /* length of MC tick in nanoseconds */
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 mc->regs = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(mc->regs))
362 return PTR_ERR(mc->regs);
364 mc->clk = devm_clk_get(&pdev->dev, "mc");
365 if (IS_ERR(mc->clk)) {
366 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
368 return PTR_ERR(mc->clk);
371 err = tegra_mc_setup_latency_allowance(mc);
373 dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
378 err = tegra_mc_setup_timings(mc);
380 dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
384 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
385 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
386 if (IS_ERR(mc->smmu)) {
387 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
389 return PTR_ERR(mc->smmu);
393 mc->irq = platform_get_irq(pdev, 0);
395 dev_err(&pdev->dev, "interrupt not specified\n");
399 err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
400 dev_name(&pdev->dev), mc);
402 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
407 WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
409 mc_writel(mc, mc->soc->intmask, MC_INTMASK);
414 static struct platform_driver tegra_mc_driver = {
417 .of_match_table = tegra_mc_of_match,
418 .suppress_bind_attrs = true,
420 .prevent_deferred_probe = true,
421 .probe = tegra_mc_probe,
424 static int tegra_mc_init(void)
426 return platform_driver_register(&tegra_mc_driver);
428 arch_initcall(tegra_mc_init);
430 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
431 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
432 MODULE_LICENSE("GPL v2");