1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
18 #include <soc/tegra/fuse.h>
22 static const struct of_device_id tegra_mc_of_match[] = {
23 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
26 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
29 #ifdef CONFIG_ARCH_TEGRA_114_SOC
30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
32 #ifdef CONFIG_ARCH_TEGRA_124_SOC
33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
35 #ifdef CONFIG_ARCH_TEGRA_132_SOC
36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
38 #ifdef CONFIG_ARCH_TEGRA_210_SOC
39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
43 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
45 static int tegra_mc_block_dma_common(struct tegra_mc *mc,
46 const struct tegra_mc_reset *rst)
51 spin_lock_irqsave(&mc->lock, flags);
53 value = mc_readl(mc, rst->control) | BIT(rst->bit);
54 mc_writel(mc, value, rst->control);
56 spin_unlock_irqrestore(&mc->lock, flags);
61 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
62 const struct tegra_mc_reset *rst)
64 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
67 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
68 const struct tegra_mc_reset *rst)
73 spin_lock_irqsave(&mc->lock, flags);
75 value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
76 mc_writel(mc, value, rst->control);
78 spin_unlock_irqrestore(&mc->lock, flags);
83 static int tegra_mc_reset_status_common(struct tegra_mc *mc,
84 const struct tegra_mc_reset *rst)
86 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
89 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
90 .block_dma = tegra_mc_block_dma_common,
91 .dma_idling = tegra_mc_dma_idling_common,
92 .unblock_dma = tegra_mc_unblock_dma_common,
93 .reset_status = tegra_mc_reset_status_common,
96 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
98 return container_of(rcdev, struct tegra_mc, reset);
101 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
106 for (i = 0; i < mc->soc->num_resets; i++)
107 if (mc->soc->resets[i].id == id)
108 return &mc->soc->resets[i];
113 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
116 struct tegra_mc *mc = reset_to_mc(rcdev);
117 const struct tegra_mc_reset_ops *rst_ops;
118 const struct tegra_mc_reset *rst;
122 rst = tegra_mc_reset_find(mc, id);
126 rst_ops = mc->soc->reset_ops;
130 if (rst_ops->block_dma) {
131 /* block clients DMA requests */
132 err = rst_ops->block_dma(mc, rst);
134 dev_err(mc->dev, "failed to block %s DMA: %d\n",
140 if (rst_ops->dma_idling) {
141 /* wait for completion of the outstanding DMA requests */
142 while (!rst_ops->dma_idling(mc, rst)) {
144 dev_err(mc->dev, "failed to flush %s DMA\n",
149 usleep_range(10, 100);
153 if (rst_ops->hotreset_assert) {
154 /* clear clients DMA requests sitting before arbitration */
155 err = rst_ops->hotreset_assert(mc, rst);
157 dev_err(mc->dev, "failed to hot reset %s: %d\n",
166 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
169 struct tegra_mc *mc = reset_to_mc(rcdev);
170 const struct tegra_mc_reset_ops *rst_ops;
171 const struct tegra_mc_reset *rst;
174 rst = tegra_mc_reset_find(mc, id);
178 rst_ops = mc->soc->reset_ops;
182 if (rst_ops->hotreset_deassert) {
183 /* take out client from hot reset */
184 err = rst_ops->hotreset_deassert(mc, rst);
186 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
192 if (rst_ops->unblock_dma) {
193 /* allow new DMA requests to proceed to arbitration */
194 err = rst_ops->unblock_dma(mc, rst);
196 dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
205 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
208 struct tegra_mc *mc = reset_to_mc(rcdev);
209 const struct tegra_mc_reset_ops *rst_ops;
210 const struct tegra_mc_reset *rst;
212 rst = tegra_mc_reset_find(mc, id);
216 rst_ops = mc->soc->reset_ops;
220 return rst_ops->reset_status(mc, rst);
223 static const struct reset_control_ops tegra_mc_reset_ops = {
224 .assert = tegra_mc_hotreset_assert,
225 .deassert = tegra_mc_hotreset_deassert,
226 .status = tegra_mc_hotreset_status,
229 static int tegra_mc_reset_setup(struct tegra_mc *mc)
233 mc->reset.ops = &tegra_mc_reset_ops;
234 mc->reset.owner = THIS_MODULE;
235 mc->reset.of_node = mc->dev->of_node;
236 mc->reset.of_reset_n_cells = 1;
237 mc->reset.nr_resets = mc->soc->num_resets;
239 err = reset_controller_register(&mc->reset);
246 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
248 unsigned long long tick;
252 /* compute the number of MC clock cycles per tick */
253 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
254 do_div(tick, NSEC_PER_SEC);
256 value = mc_readl(mc, MC_EMEM_ARB_CFG);
257 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
258 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
259 mc_writel(mc, value, MC_EMEM_ARB_CFG);
261 /* write latency allowance defaults */
262 for (i = 0; i < mc->soc->num_clients; i++) {
263 const struct tegra_mc_la *la = &mc->soc->clients[i].la;
266 value = mc_readl(mc, la->reg);
267 value &= ~(la->mask << la->shift);
268 value |= (la->def & la->mask) << la->shift;
269 mc_writel(mc, value, la->reg);
272 /* latch new values */
273 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
278 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
281 struct tegra_mc_timing *timing = NULL;
283 for (i = 0; i < mc->num_timings; i++) {
284 if (mc->timings[i].rate == rate) {
285 timing = &mc->timings[i];
291 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
296 for (i = 0; i < mc->soc->num_emem_regs; ++i)
297 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
302 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
306 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
307 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
313 static int load_one_timing(struct tegra_mc *mc,
314 struct tegra_mc_timing *timing,
315 struct device_node *node)
320 err = of_property_read_u32(node, "clock-frequency", &tmp);
323 "timing %pOFn: failed to read rate\n", node);
328 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
329 sizeof(u32), GFP_KERNEL);
330 if (!timing->emem_data)
333 err = of_property_read_u32_array(node, "nvidia,emem-configuration",
335 mc->soc->num_emem_regs);
338 "timing %pOFn: failed to read EMEM configuration\n",
346 static int load_timings(struct tegra_mc *mc, struct device_node *node)
348 struct device_node *child;
349 struct tegra_mc_timing *timing;
350 int child_count = of_get_child_count(node);
353 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
358 mc->num_timings = child_count;
360 for_each_child_of_node(node, child) {
361 timing = &mc->timings[i++];
363 err = load_one_timing(mc, timing, child);
373 static int tegra_mc_setup_timings(struct tegra_mc *mc)
375 struct device_node *node;
376 u32 ram_code, node_ram_code;
379 ram_code = tegra_read_ram_code();
383 for_each_child_of_node(mc->dev->of_node, node) {
384 err = of_property_read_u32(node, "nvidia,ram-code",
386 if (err || (node_ram_code != ram_code))
389 err = load_timings(mc, node);
396 if (mc->num_timings == 0)
398 "no memory timings for RAM code %u registered\n",
404 static const char *const status_names[32] = {
405 [ 1] = "External interrupt",
406 [ 6] = "EMEM address decode error",
407 [ 7] = "GART page fault",
408 [ 8] = "Security violation",
409 [ 9] = "EMEM arbitration error",
411 [11] = "Invalid APB ASID update",
412 [12] = "VPR violation",
413 [13] = "Secure carveout violation",
414 [16] = "MTS carveout violation",
417 static const char *const error_names[8] = {
418 [2] = "EMEM decode error",
419 [3] = "TrustZone violation",
420 [4] = "Carveout violation",
421 [6] = "SMMU translation error",
424 static irqreturn_t tegra_mc_irq(int irq, void *data)
426 struct tegra_mc *mc = data;
427 unsigned long status;
430 /* mask all interrupts to avoid flooding */
431 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
435 for_each_set_bit(bit, &status, 32) {
436 const char *error = status_names[bit] ?: "unknown";
437 const char *client = "unknown", *desc;
438 const char *direction, *secure;
439 phys_addr_t addr = 0;
445 value = mc_readl(mc, MC_ERR_STATUS);
447 #ifdef CONFIG_PHYS_ADDR_T_64BIT
448 if (mc->soc->num_address_bits > 32) {
449 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
450 MC_ERR_STATUS_ADR_HI_MASK);
455 if (value & MC_ERR_STATUS_RW)
460 if (value & MC_ERR_STATUS_SECURITY)
465 id = value & mc->soc->client_id_mask;
467 for (i = 0; i < mc->soc->num_clients; i++) {
468 if (mc->soc->clients[i].id == id) {
469 client = mc->soc->clients[i].name;
474 type = (value & MC_ERR_STATUS_TYPE_MASK) >>
475 MC_ERR_STATUS_TYPE_SHIFT;
476 desc = error_names[type];
478 switch (value & MC_ERR_STATUS_TYPE_MASK) {
479 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
483 if (value & MC_ERR_STATUS_READABLE)
488 if (value & MC_ERR_STATUS_WRITABLE)
493 if (value & MC_ERR_STATUS_NONSECURE)
507 value = mc_readl(mc, MC_ERR_ADR);
510 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
511 client, secure, direction, &addr, error,
515 /* clear interrupts */
516 mc_writel(mc, status, MC_INTSTATUS);
521 static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
523 struct tegra_mc *mc = data;
524 unsigned long status;
527 /* mask all interrupts to avoid flooding */
528 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
532 for_each_set_bit(bit, &status, 32) {
533 const char *direction = "read", *secure = "";
534 const char *error = status_names[bit];
535 const char *client, *desc;
541 case MC_INT_DECERR_EMEM:
542 reg = MC_DECERR_EMEM_OTHERS_STATUS;
543 value = mc_readl(mc, reg);
545 id = value & mc->soc->client_id_mask;
546 desc = error_names[2];
552 case MC_INT_INVALID_GART_PAGE:
553 reg = MC_GART_ERROR_REQ;
554 value = mc_readl(mc, reg);
556 id = (value >> 1) & mc->soc->client_id_mask;
557 desc = error_names[2];
563 case MC_INT_SECURITY_VIOLATION:
564 reg = MC_SECURITY_VIOLATION_STATUS;
565 value = mc_readl(mc, reg);
567 id = value & mc->soc->client_id_mask;
568 type = (value & BIT(30)) ? 4 : 3;
569 desc = error_names[type];
580 client = mc->soc->clients[id].name;
581 addr = mc_readl(mc, reg + sizeof(u32));
583 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
584 client, secure, direction, &addr, error,
588 /* clear interrupts */
589 mc_writel(mc, status, MC_INTSTATUS);
594 static int tegra_mc_probe(struct platform_device *pdev)
596 struct resource *res;
602 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
606 platform_set_drvdata(pdev, mc);
607 spin_lock_init(&mc->lock);
608 mc->soc = of_device_get_match_data(&pdev->dev);
609 mc->dev = &pdev->dev;
611 mask = DMA_BIT_MASK(mc->soc->num_address_bits);
613 err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
615 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
619 /* length of MC tick in nanoseconds */
622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
623 mc->regs = devm_ioremap_resource(&pdev->dev, res);
624 if (IS_ERR(mc->regs))
625 return PTR_ERR(mc->regs);
627 mc->clk = devm_clk_get(&pdev->dev, "mc");
628 if (IS_ERR(mc->clk)) {
629 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
631 return PTR_ERR(mc->clk);
634 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
635 if (mc->soc == &tegra20_mc_soc) {
636 isr = tegra20_mc_irq;
640 /* ensure that debug features are disabled */
641 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
643 err = tegra_mc_setup_latency_allowance(mc);
646 "failed to setup latency allowance: %d\n",
653 err = tegra_mc_setup_timings(mc);
655 dev_err(&pdev->dev, "failed to setup timings: %d\n",
661 mc->irq = platform_get_irq(pdev, 0);
663 dev_err(&pdev->dev, "interrupt not specified\n");
667 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
669 mc_writel(mc, mc->soc->intmask, MC_INTMASK);
671 err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
672 dev_name(&pdev->dev), mc);
674 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
679 err = tegra_mc_reset_setup(mc);
681 dev_err(&pdev->dev, "failed to register reset controller: %d\n",
684 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
685 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
686 if (IS_ERR(mc->smmu)) {
687 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
693 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
694 mc->gart = tegra_gart_probe(&pdev->dev, mc);
695 if (IS_ERR(mc->gart)) {
696 dev_err(&pdev->dev, "failed to probe GART: %ld\n",
705 static int tegra_mc_suspend(struct device *dev)
707 struct tegra_mc *mc = dev_get_drvdata(dev);
710 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
711 err = tegra_gart_suspend(mc->gart);
719 static int tegra_mc_resume(struct device *dev)
721 struct tegra_mc *mc = dev_get_drvdata(dev);
724 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
725 err = tegra_gart_resume(mc->gart);
733 static const struct dev_pm_ops tegra_mc_pm_ops = {
734 .suspend = tegra_mc_suspend,
735 .resume = tegra_mc_resume,
738 static struct platform_driver tegra_mc_driver = {
741 .of_match_table = tegra_mc_of_match,
742 .pm = &tegra_mc_pm_ops,
743 .suppress_bind_attrs = true,
745 .prevent_deferred_probe = true,
746 .probe = tegra_mc_probe,
749 static int tegra_mc_init(void)
751 return platform_driver_register(&tegra_mc_driver);
753 arch_initcall(tegra_mc_init);
755 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
756 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
757 MODULE_LICENSE("GPL v2");