drivers/memory/renesas-rpc-if.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RPC-IF core driver
   4  *
   5  * Copyright (C) 2018-2019 Renesas Solutions Corp.
   6  * Copyright (C) 2019 Macronix International Co., Ltd.
   7  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18
  19 #include <memory/renesas-rpc-if.h>
  20
  21 #define RPCIF_CMNCR             0x0000  /* R/W */
  22 #define RPCIF_CMNCR_MD          BIT(31)
  23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  27 #define RPCIF_CMNCR_MOIIO(val)  (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
  28                                  RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
  29 #define RPCIF_CMNCR_IO3FV(val)  (((val) & 0x3) << 14) /* documented for RZ/G2L */
  30 #define RPCIF_CMNCR_IO2FV(val)  (((val) & 0x3) << 12) /* documented for RZ/G2L */
  31 #define RPCIF_CMNCR_IO0FV(val)  (((val) & 0x3) << 8)
  32 #define RPCIF_CMNCR_IOFV(val)   (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
  33                                  RPCIF_CMNCR_IO3FV(val))
  34 #define RPCIF_CMNCR_BSZ(val)    (((val) & 0x3) << 0)
  35
  36 #define RPCIF_SSLDR             0x0004  /* R/W */
  37 #define RPCIF_SSLDR_SPNDL(d)    (((d) & 0x7) << 16)
  38 #define RPCIF_SSLDR_SLNDL(d)    (((d) & 0x7) << 8)
  39 #define RPCIF_SSLDR_SCKDL(d)    (((d) & 0x7) << 0)
  40
  41 #define RPCIF_DRCR              0x000C  /* R/W */
  42 #define RPCIF_DRCR_SSLN         BIT(24)
  43 #define RPCIF_DRCR_RBURST(v)    ((((v) - 1) & 0x1F) << 16)
  44 #define RPCIF_DRCR_RCF          BIT(9)
  45 #define RPCIF_DRCR_RBE          BIT(8)
  46 #define RPCIF_DRCR_SSLE         BIT(0)
  47
  48 #define RPCIF_DRCMR             0x0010  /* R/W */
  49 #define RPCIF_DRCMR_CMD(c)      (((c) & 0xFF) << 16)
  50 #define RPCIF_DRCMR_OCMD(c)     (((c) & 0xFF) << 0)
  51
  52 #define RPCIF_DREAR             0x0014  /* R/W */
  53 #define RPCIF_DREAR_EAV(c)      (((c) & 0xF) << 16)
  54 #define RPCIF_DREAR_EAC(c)      (((c) & 0x7) << 0)
  55
  56 #define RPCIF_DROPR             0x0018  /* R/W */
  57
  58 #define RPCIF_DRENR             0x001C  /* R/W */
  59 #define RPCIF_DRENR_CDB(o)      (u32)((((o) & 0x3) << 30))
  60 #define RPCIF_DRENR_OCDB(o)     (((o) & 0x3) << 28)
  61 #define RPCIF_DRENR_ADB(o)      (((o) & 0x3) << 24)
  62 #define RPCIF_DRENR_OPDB(o)     (((o) & 0x3) << 20)
  63 #define RPCIF_DRENR_DRDB(o)     (((o) & 0x3) << 16)
  64 #define RPCIF_DRENR_DME         BIT(15)
  65 #define RPCIF_DRENR_CDE         BIT(14)
  66 #define RPCIF_DRENR_OCDE        BIT(12)
  67 #define RPCIF_DRENR_ADE(v)      (((v) & 0xF) << 8)
  68 #define RPCIF_DRENR_OPDE(v)     (((v) & 0xF) << 4)
  69
  70 #define RPCIF_SMCR              0x0020  /* R/W */
  71 #define RPCIF_SMCR_SSLKP        BIT(8)
  72 #define RPCIF_SMCR_SPIRE        BIT(2)
  73 #define RPCIF_SMCR_SPIWE        BIT(1)
  74 #define RPCIF_SMCR_SPIE         BIT(0)
  75
  76 #define RPCIF_SMCMR             0x0024  /* R/W */
  77 #define RPCIF_SMCMR_CMD(c)      (((c) & 0xFF) << 16)
  78 #define RPCIF_SMCMR_OCMD(c)     (((c) & 0xFF) << 0)
  79
  80 #define RPCIF_SMADR             0x0028  /* R/W */
  81
  82 #define RPCIF_SMOPR             0x002C  /* R/W */
  83 #define RPCIF_SMOPR_OPD3(o)     (((o) & 0xFF) << 24)
  84 #define RPCIF_SMOPR_OPD2(o)     (((o) & 0xFF) << 16)
  85 #define RPCIF_SMOPR_OPD1(o)     (((o) & 0xFF) << 8)
  86 #define RPCIF_SMOPR_OPD0(o)     (((o) & 0xFF) << 0)
  87
  88 #define RPCIF_SMENR             0x0030  /* R/W */
  89 #define RPCIF_SMENR_CDB(o)      (((o) & 0x3) << 30)
  90 #define RPCIF_SMENR_OCDB(o)     (((o) & 0x3) << 28)
  91 #define RPCIF_SMENR_ADB(o)      (((o) & 0x3) << 24)
  92 #define RPCIF_SMENR_OPDB(o)     (((o) & 0x3) << 20)
  93 #define RPCIF_SMENR_SPIDB(o)    (((o) & 0x3) << 16)
  94 #define RPCIF_SMENR_DME         BIT(15)
  95 #define RPCIF_SMENR_CDE         BIT(14)
  96 #define RPCIF_SMENR_OCDE        BIT(12)
  97 #define RPCIF_SMENR_ADE(v)      (((v) & 0xF) << 8)
  98 #define RPCIF_SMENR_OPDE(v)     (((v) & 0xF) << 4)
  99 #define RPCIF_SMENR_SPIDE(v)    (((v) & 0xF) << 0)
 100
 101 #define RPCIF_SMRDR0            0x0038  /* R */
 102 #define RPCIF_SMRDR1            0x003C  /* R */
 103 #define RPCIF_SMWDR0            0x0040  /* W */
 104 #define RPCIF_SMWDR1            0x0044  /* W */
 105
 106 #define RPCIF_CMNSR             0x0048  /* R */
 107 #define RPCIF_CMNSR_SSLF        BIT(1)
 108 #define RPCIF_CMNSR_TEND        BIT(0)
 109
 110 #define RPCIF_DRDMCR            0x0058  /* R/W */
 111 #define RPCIF_DMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 112
 113 #define RPCIF_DRDRENR           0x005C  /* R/W */
 114 #define RPCIF_DRDRENR_HYPE(v)   (((v) & 0x7) << 12)
 115 #define RPCIF_DRDRENR_ADDRE     BIT(8)
 116 #define RPCIF_DRDRENR_OPDRE     BIT(4)
 117 #define RPCIF_DRDRENR_DRDRE     BIT(0)
 118
 119 #define RPCIF_SMDMCR            0x0060  /* R/W */
 120 #define RPCIF_SMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 121
 122 #define RPCIF_SMDRENR           0x0064  /* R/W */
 123 #define RPCIF_SMDRENR_HYPE(v)   (((v) & 0x7) << 12)
 124 #define RPCIF_SMDRENR_ADDRE     BIT(8)
 125 #define RPCIF_SMDRENR_OPDRE     BIT(4)
 126 #define RPCIF_SMDRENR_SPIDRE    BIT(0)
 127
 128 #define RPCIF_PHYADD            0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
 129 #define RPCIF_PHYWR             0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
 130
 131 #define RPCIF_PHYCNT            0x007C  /* R/W */
 132 #define RPCIF_PHYCNT_CAL        BIT(31)
 133 #define RPCIF_PHYCNT_OCTA(v)    (((v) & 0x3) << 22)
 134 #define RPCIF_PHYCNT_EXDS       BIT(21)
 135 #define RPCIF_PHYCNT_OCT        BIT(20)
 136 #define RPCIF_PHYCNT_DDRCAL     BIT(19)
 137 #define RPCIF_PHYCNT_HS         BIT(18)
 138 #define RPCIF_PHYCNT_CKSEL(v)   (((v) & 0x3) << 16) /* valid only for RZ/G2L */
 139 #define RPCIF_PHYCNT_STRTIM(v)  (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
 140 #define RPCIF_PHYCNT_WBUF2      BIT(4)
 141 #define RPCIF_PHYCNT_WBUF       BIT(2)
 142 #define RPCIF_PHYCNT_PHYMEM(v)  (((v) & 0x3) << 0)
 143 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
 144
 145 #define RPCIF_PHYOFFSET1        0x0080  /* R/W */
 146 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
 147
 148 #define RPCIF_PHYOFFSET2        0x0084  /* R/W */
 149 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
 150
 151 #define RPCIF_PHYINT            0x0088  /* R/W */
 152 #define RPCIF_PHYINT_WPVAL      BIT(1)
 153
 154 static const struct regmap_range rpcif_volatile_ranges[] = {
 155         regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
 156         regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
 157         regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
 158 };
 159
 160 static const struct regmap_access_table rpcif_volatile_table = {
 161         .yes_ranges     = rpcif_volatile_ranges,
 162         .n_yes_ranges   = ARRAY_SIZE(rpcif_volatile_ranges),
 163 };
 164
 165 struct rpcif_priv {
 166         struct device *dev;
 167         void __iomem *base;
 168         void __iomem *dirmap;
 169         struct regmap *regmap;
 170         struct reset_control *rstc;
 171         struct platform_device *vdev;
 172         size_t size;
 173         enum rpcif_type type;
 174         enum rpcif_data_dir dir;
 175         u8 bus_size;
 176         u8 xfer_size;
 177         void *buffer;
 178         u32 xferlen;
 179         u32 smcr;
 180         u32 smadr;
 181         u32 command;            /* DRCMR or SMCMR */
 182         u32 option;             /* DROPR or SMOPR */
 183         u32 enable;             /* DRENR or SMENR */
 184         u32 dummy;              /* DRDMCR or SMDMCR */
 185         u32 ddr;                /* DRDRENR or SMDRENR */
 186 };
 187
 188 /*
 189  * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
 190  * proper width.  Requires rpcif_priv.xfer_size to be correctly set before!
 191  */
 192 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
 193 {
 194         struct rpcif_priv *rpc = context;
 195
 196         switch (reg) {
 197         case RPCIF_SMRDR0:
 198         case RPCIF_SMWDR0:
 199                 switch (rpc->xfer_size) {
 200                 case 1:
 201                         *val = readb(rpc->base + reg);
 202                         return 0;
 203
 204                 case 2:
 205                         *val = readw(rpc->base + reg);
 206                         return 0;
 207
 208                 case 4:
 209                 case 8:
 210                         *val = readl(rpc->base + reg);
 211                         return 0;
 212
 213                 default:
 214                         return -EILSEQ;
 215                 }
 216
 217         case RPCIF_SMRDR1:
 218         case RPCIF_SMWDR1:
 219                 if (rpc->xfer_size != 8)
 220                         return -EILSEQ;
 221                 break;
 222         }
 223
 224         *val = readl(rpc->base + reg);
 225         return 0;
 226 }
 227
 228 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
 229 {
 230         struct rpcif_priv *rpc = context;
 231
 232         switch (reg) {
 233         case RPCIF_SMWDR0:
 234                 switch (rpc->xfer_size) {
 235                 case 1:
 236                         writeb(val, rpc->base + reg);
 237                         return 0;
 238
 239                 case 2:
 240                         writew(val, rpc->base + reg);
 241                         return 0;
 242
 243                 case 4:
 244                 case 8:
 245                         writel(val, rpc->base + reg);
 246                         return 0;
 247
 248                 default:
 249                         return -EILSEQ;
 250                 }
 251
 252         case RPCIF_SMWDR1:
 253                 if (rpc->xfer_size != 8)
 254                         return -EILSEQ;
 255                 break;
 256
 257         case RPCIF_SMRDR0:
 258         case RPCIF_SMRDR1:
 259                 return -EPERM;
 260         }
 261
 262         writel(val, rpc->base + reg);
 263         return 0;
 264 }
 265
 266 static const struct regmap_config rpcif_regmap_config = {
 267         .reg_bits       = 32,
 268         .val_bits       = 32,
 269         .reg_stride     = 4,
 270         .reg_read       = rpcif_reg_read,
 271         .reg_write      = rpcif_reg_write,
 272         .fast_io        = true,
 273         .max_register   = RPCIF_PHYINT,
 274         .volatile_table = &rpcif_volatile_table,
 275 };
 276
 277 int rpcif_sw_init(struct rpcif *rpcif, struct device *dev)
 278 {
 279         struct rpcif_priv *rpc = dev_get_drvdata(dev);
 280
 281         rpcif->dev = dev;
 282         rpcif->dirmap = rpc->dirmap;
 283         rpcif->size = rpc->size;
 284         return 0;
 285 }
 286 EXPORT_SYMBOL(rpcif_sw_init);
 287
 288 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc)
 289 {
 290         regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
 291         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
 292         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
 293         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
 294         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
 295         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
 296         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3),
 297                            RPCIF_PHYCNT_CKSEL(3));
 298         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
 299         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
 300 }
 301
 302 int rpcif_hw_init(struct rpcif *rpcif, bool hyperflash)
 303 {
 304         struct rpcif_priv *rpc = dev_get_drvdata(rpcif->dev);
 305         u32 dummy;
 306
 307         pm_runtime_get_sync(rpc->dev);
 308
 309         if (rpc->type == RPCIF_RZ_G2L) {
 310                 int ret;
 311
 312                 ret = reset_control_reset(rpc->rstc);
 313                 if (ret)
 314                         return ret;
 315                 usleep_range(200, 300);
 316                 rpcif_rzg2l_timing_adjust_sdr(rpc);
 317         }
 318
 319         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
 320                            RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
 321
 322         /* DMA Transfer is not supported */
 323         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
 324
 325         if (rpc->type == RPCIF_RCAR_GEN3)
 326                 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 327                                    RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
 328
 329         regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
 330                            RPCIF_PHYOFFSET1_DDRTMG(3));
 331         regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7),
 332                            RPCIF_PHYOFFSET2_OCTTMG(4));
 333
 334         if (hyperflash)
 335                 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
 336                                    RPCIF_PHYINT_WPVAL, 0);
 337
 338         if (rpc->type == RPCIF_RCAR_GEN3)
 339                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 340                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
 341                                    RPCIF_CMNCR_MOIIO(3) |
 342                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 343         else
 344                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 345                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
 346                                    RPCIF_CMNCR_BSZ(3),
 347                                    RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
 348                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 349
 350         /* Set RCF after BSZ update */
 351         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 352         /* Dummy read according to spec */
 353         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 354         regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
 355                      RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
 356
 357         pm_runtime_put(rpc->dev);
 358
 359         rpc->bus_size = hyperflash ? 2 : 1;
 360
 361         return 0;
 362 }
 363 EXPORT_SYMBOL(rpcif_hw_init);
 364
 365 static int wait_msg_xfer_end(struct rpcif_priv *rpc)
 366 {
 367         u32 sts;
 368
 369         return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
 370                                         sts & RPCIF_CMNSR_TEND, 0,
 371                                         USEC_PER_SEC);
 372 }
 373
 374 static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes)
 375 {
 376         if (rpc->bus_size == 2)
 377                 nbytes /= 2;
 378         nbytes = clamp(nbytes, 1U, 4U);
 379         return GENMASK(3, 4 - nbytes);
 380 }
 381
 382 static u8 rpcif_bit_size(u8 buswidth)
 383 {
 384         return buswidth > 4 ? 2 : ilog2(buswidth);
 385 }
 386
 387 void rpcif_prepare(struct rpcif *rpcif, const struct rpcif_op *op, u64 *offs,
 388                    size_t *len)
 389 {
 390         struct rpcif_priv *rpc = dev_get_drvdata(rpcif->dev);
 391
 392         rpc->smcr = 0;
 393         rpc->smadr = 0;
 394         rpc->enable = 0;
 395         rpc->command = 0;
 396         rpc->option = 0;
 397         rpc->dummy = 0;
 398         rpc->ddr = 0;
 399         rpc->xferlen = 0;
 400
 401         if (op->cmd.buswidth) {
 402                 rpc->enable  = RPCIF_SMENR_CDE |
 403                         RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
 404                 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
 405                 if (op->cmd.ddr)
 406                         rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
 407         }
 408         if (op->ocmd.buswidth) {
 409                 rpc->enable  |= RPCIF_SMENR_OCDE |
 410                         RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
 411                 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
 412         }
 413
 414         if (op->addr.buswidth) {
 415                 rpc->enable |=
 416                         RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
 417                 if (op->addr.nbytes == 4)
 418                         rpc->enable |= RPCIF_SMENR_ADE(0xF);
 419                 else
 420                         rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
 421                                                 2, 3 - op->addr.nbytes));
 422                 if (op->addr.ddr)
 423                         rpc->ddr |= RPCIF_SMDRENR_ADDRE;
 424
 425                 if (offs && len)
 426                         rpc->smadr = *offs;
 427                 else
 428                         rpc->smadr = op->addr.val;
 429         }
 430
 431         if (op->dummy.buswidth) {
 432                 rpc->enable |= RPCIF_SMENR_DME;
 433                 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
 434                                                 op->dummy.buswidth);
 435         }
 436
 437         if (op->option.buswidth) {
 438                 rpc->enable |= RPCIF_SMENR_OPDE(
 439                         rpcif_bits_set(rpc, op->option.nbytes)) |
 440                         RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
 441                 if (op->option.ddr)
 442                         rpc->ddr |= RPCIF_SMDRENR_OPDRE;
 443                 rpc->option = op->option.val;
 444         }
 445
 446         rpc->dir = op->data.dir;
 447         if (op->data.buswidth) {
 448                 u32 nbytes;
 449
 450                 rpc->buffer = op->data.buf.in;
 451                 switch (op->data.dir) {
 452                 case RPCIF_DATA_IN:
 453                         rpc->smcr = RPCIF_SMCR_SPIRE;
 454                         break;
 455                 case RPCIF_DATA_OUT:
 456                         rpc->smcr = RPCIF_SMCR_SPIWE;
 457                         break;
 458                 default:
 459                         break;
 460                 }
 461                 if (op->data.ddr)
 462                         rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
 463
 464                 if (offs && len)
 465                         nbytes = *len;
 466                 else
 467                         nbytes = op->data.nbytes;
 468                 rpc->xferlen = nbytes;
 469
 470                 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
 471         }
 472 }
 473 EXPORT_SYMBOL(rpcif_prepare);
 474
 475 int rpcif_manual_xfer(struct rpcif *rpcif)
 476 {
 477         struct rpcif_priv *rpc = dev_get_drvdata(rpcif->dev);
 478         u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
 479         int ret = 0;
 480
 481         pm_runtime_get_sync(rpc->dev);
 482
 483         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 484                            RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
 485         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 486                            RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
 487         regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
 488         regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
 489         regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
 490         regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
 491         regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
 492         smenr = rpc->enable;
 493
 494         switch (rpc->dir) {
 495         case RPCIF_DATA_OUT:
 496                 while (pos < rpc->xferlen) {
 497                         u32 bytes_left = rpc->xferlen - pos;
 498                         u32 nbytes, data[2], *p = data;
 499
 500                         smcr = rpc->smcr | RPCIF_SMCR_SPIE;
 501
 502                         /* nbytes may only be 1, 2, 4, or 8 */
 503                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 504                         if (bytes_left > nbytes)
 505                                 smcr |= RPCIF_SMCR_SSLKP;
 506
 507                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 508                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 509                         rpc->xfer_size = nbytes;
 510
 511                         memcpy(data, rpc->buffer + pos, nbytes);
 512                         if (nbytes == 8)
 513                                 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++);
 514                         regmap_write(rpc->regmap, RPCIF_SMWDR0, *p);
 515
 516                         regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
 517                         ret = wait_msg_xfer_end(rpc);
 518                         if (ret)
 519                                 goto err_out;
 520
 521                         pos += nbytes;
 522                         smenr = rpc->enable &
 523                                 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
 524                 }
 525                 break;
 526         case RPCIF_DATA_IN:
 527                 /*
 528                  * RPC-IF spoils the data for the commands without an address
 529                  * phase (like RDID) in the manual mode, so we'll have to work
 530                  * around this issue by using the external address space read
 531                  * mode instead.
 532                  */
 533                 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
 534                         u32 dummy;
 535
 536                         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 537                                            RPCIF_CMNCR_MD, 0);
 538                         regmap_write(rpc->regmap, RPCIF_DRCR,
 539                                      RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
 540                         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 541                         regmap_write(rpc->regmap, RPCIF_DREAR,
 542                                      RPCIF_DREAR_EAC(1));
 543                         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 544                         regmap_write(rpc->regmap, RPCIF_DRENR,
 545                                      smenr & ~RPCIF_SMENR_SPIDE(0xF));
 546                         regmap_write(rpc->regmap, RPCIF_DRDMCR,  rpc->dummy);
 547                         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 548                         memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
 549                         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 550                         /* Dummy read according to spec */
 551                         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 552                         break;
 553                 }
 554                 while (pos < rpc->xferlen) {
 555                         u32 bytes_left = rpc->xferlen - pos;
 556                         u32 nbytes, data[2], *p = data;
 557
 558                         /* nbytes may only be 1, 2, 4, or 8 */
 559                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 560
 561                         regmap_write(rpc->regmap, RPCIF_SMADR,
 562                                      rpc->smadr + pos);
 563                         smenr &= ~RPCIF_SMENR_SPIDE(0xF);
 564                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 565                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 566                         regmap_write(rpc->regmap, RPCIF_SMCR,
 567                                      rpc->smcr | RPCIF_SMCR_SPIE);
 568                         rpc->xfer_size = nbytes;
 569                         ret = wait_msg_xfer_end(rpc);
 570                         if (ret)
 571                                 goto err_out;
 572
 573                         if (nbytes == 8)
 574                                 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++);
 575                         regmap_read(rpc->regmap, RPCIF_SMRDR0, p);
 576                         memcpy(rpc->buffer + pos, data, nbytes);
 577
 578                         pos += nbytes;
 579                 }
 580                 break;
 581         default:
 582                 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
 583                 regmap_write(rpc->regmap, RPCIF_SMCR,
 584                              rpc->smcr | RPCIF_SMCR_SPIE);
 585                 ret = wait_msg_xfer_end(rpc);
 586                 if (ret)
 587                         goto err_out;
 588         }
 589
 590 exit:
 591         pm_runtime_put(rpc->dev);
 592         return ret;
 593
 594 err_out:
 595         if (reset_control_reset(rpc->rstc))
 596                 dev_err(rpc->dev, "Failed to reset HW\n");
 597         rpcif_hw_init(rpcif, rpc->bus_size == 2);
 598         goto exit;
 599 }
 600 EXPORT_SYMBOL(rpcif_manual_xfer);
 601
 602 static void memcpy_fromio_readw(void *to,
 603                                 const void __iomem *from,
 604                                 size_t count)
 605 {
 606         const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
 607         u8 buf[2];
 608
 609         if (count && ((unsigned long)from & 1)) {
 610                 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
 611                 *(u8 *)to = buf[1];
 612                 from++;
 613                 to++;
 614                 count--;
 615         }
 616         while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
 617                 *(u16 *)to = __raw_readw(from);
 618                 from += 2;
 619                 to += 2;
 620                 count -= 2;
 621         }
 622         while (count >= maxw) {
 623 #ifdef CONFIG_64BIT
 624                 *(u64 *)to = __raw_readq(from);
 625 #else
 626                 *(u32 *)to = __raw_readl(from);
 627 #endif
 628                 from += maxw;
 629                 to += maxw;
 630                 count -= maxw;
 631         }
 632         while (count >= 2) {
 633                 *(u16 *)to = __raw_readw(from);
 634                 from += 2;
 635                 to += 2;
 636                 count -= 2;
 637         }
 638         if (count) {
 639                 *(u16 *)buf = __raw_readw(from);
 640                 *(u8 *)to = buf[0];
 641         }
 642 }
 643
 644 ssize_t rpcif_dirmap_read(struct rpcif *rpcif, u64 offs, size_t len, void *buf)
 645 {
 646         struct rpcif_priv *rpc = dev_get_drvdata(rpcif->dev);
 647         loff_t from = offs & (rpc->size - 1);
 648         size_t size = rpc->size - from;
 649
 650         if (len > size)
 651                 len = size;
 652
 653         pm_runtime_get_sync(rpc->dev);
 654
 655         regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
 656         regmap_write(rpc->regmap, RPCIF_DRCR, 0);
 657         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 658         regmap_write(rpc->regmap, RPCIF_DREAR,
 659                      RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
 660         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 661         regmap_write(rpc->regmap, RPCIF_DRENR,
 662                      rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
 663         regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
 664         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 665
 666         if (rpc->bus_size == 2)
 667                 memcpy_fromio_readw(buf, rpc->dirmap + from, len);
 668         else
 669                 memcpy_fromio(buf, rpc->dirmap + from, len);
 670
 671         pm_runtime_put(rpc->dev);
 672
 673         return len;
 674 }
 675 EXPORT_SYMBOL(rpcif_dirmap_read);
 676
 677 static int rpcif_probe(struct platform_device *pdev)
 678 {
 679         struct device *dev = &pdev->dev;
 680         struct platform_device *vdev;
 681         struct device_node *flash;
 682         struct rpcif_priv *rpc;
 683         struct resource *res;
 684         const char *name;
 685         int ret;
 686
 687         flash = of_get_next_child(pdev->dev.of_node, NULL);
 688         if (!flash) {
 689                 dev_warn(&pdev->dev, "no flash node found\n");
 690                 return -ENODEV;
 691         }
 692
 693         if (of_device_is_compatible(flash, "jedec,spi-nor")) {
 694                 name = "rpc-if-spi";
 695         } else if (of_device_is_compatible(flash, "cfi-flash")) {
 696                 name = "rpc-if-hyperflash";
 697         } else  {
 698                 of_node_put(flash);
 699                 dev_warn(&pdev->dev, "unknown flash type\n");
 700                 return -ENODEV;
 701         }
 702         of_node_put(flash);
 703
 704         rpc = devm_kzalloc(&pdev->dev, sizeof(*rpc), GFP_KERNEL);
 705         if (!rpc)
 706                 return -ENOMEM;
 707
 708         rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs");
 709         if (IS_ERR(rpc->base))
 710                 return PTR_ERR(rpc->base);
 711
 712         rpc->regmap = devm_regmap_init(dev, NULL, rpc, &rpcif_regmap_config);
 713         if (IS_ERR(rpc->regmap)) {
 714                 dev_err(dev, "failed to init regmap for rpcif, error %ld\n",
 715                         PTR_ERR(rpc->regmap));
 716                 return  PTR_ERR(rpc->regmap);
 717         }
 718
 719         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
 720         rpc->dirmap = devm_ioremap_resource(dev, res);
 721         if (IS_ERR(rpc->dirmap))
 722                 return PTR_ERR(rpc->dirmap);
 723         rpc->size = resource_size(res);
 724
 725         rpc->type = (uintptr_t)of_device_get_match_data(dev);
 726         rpc->rstc = devm_reset_control_get_exclusive(dev, NULL);
 727         if (IS_ERR(rpc->rstc))
 728                 return PTR_ERR(rpc->rstc);
 729
 730         vdev = platform_device_alloc(name, pdev->id);
 731         if (!vdev)
 732                 return -ENOMEM;
 733         vdev->dev.parent = &pdev->dev;
 734
 735         rpc->dev = &pdev->dev;
 736         rpc->vdev = vdev;
 737         platform_set_drvdata(pdev, rpc);
 738
 739         ret = platform_device_add(vdev);
 740         if (ret) {
 741                 platform_device_put(vdev);
 742                 return ret;
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int rpcif_remove(struct platform_device *pdev)
 749 {
 750         struct rpcif_priv *rpc = platform_get_drvdata(pdev);
 751
 752         platform_device_unregister(rpc->vdev);
 753
 754         return 0;
 755 }
 756
 757 static const struct of_device_id rpcif_of_match[] = {
 758         { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
 759         { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
 760         {},
 761 };
 762 MODULE_DEVICE_TABLE(of, rpcif_of_match);
 763
 764 static struct platform_driver rpcif_driver = {
 765         .probe  = rpcif_probe,
 766         .remove = rpcif_remove,
 767         .driver = {
 768                 .name = "rpc-if",
 769                 .of_match_table = rpcif_of_match,
 770         },
 771 };
 772 module_platform_driver(rpcif_driver);
 773
 774 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
 775 MODULE_LICENSE("GPL v2");