1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPMC support functions
5 * Copyright (C) 2005-2006 Nokia Corporation
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/ioport.h>
18 #include <linux/spinlock.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
22 #include <linux/gpio/machine.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/platform_device.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/of_platform.h>
30 #include <linux/omap-gpmc.h>
31 #include <linux/pm_runtime.h>
33 #include <linux/platform_data/mtd-nand-omap2.h>
35 #include <asm/mach-types.h>
37 #define DEVICE_NAME "omap-gpmc"
39 /* GPMC register offsets */
40 #define GPMC_REVISION 0x00
41 #define GPMC_SYSCONFIG 0x10
42 #define GPMC_SYSSTATUS 0x14
43 #define GPMC_IRQSTATUS 0x18
44 #define GPMC_IRQENABLE 0x1c
45 #define GPMC_TIMEOUT_CONTROL 0x40
46 #define GPMC_ERR_ADDRESS 0x44
47 #define GPMC_ERR_TYPE 0x48
48 #define GPMC_CONFIG 0x50
49 #define GPMC_STATUS 0x54
50 #define GPMC_PREFETCH_CONFIG1 0x1e0
51 #define GPMC_PREFETCH_CONFIG2 0x1e4
52 #define GPMC_PREFETCH_CONTROL 0x1ec
53 #define GPMC_PREFETCH_STATUS 0x1f0
54 #define GPMC_ECC_CONFIG 0x1f4
55 #define GPMC_ECC_CONTROL 0x1f8
56 #define GPMC_ECC_SIZE_CONFIG 0x1fc
57 #define GPMC_ECC1_RESULT 0x200
58 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
59 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
60 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
66 /* GPMC ECC control settings */
67 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
68 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
69 #define GPMC_ECC_CTRL_ECCREG1 0x001
70 #define GPMC_ECC_CTRL_ECCREG2 0x002
71 #define GPMC_ECC_CTRL_ECCREG3 0x003
72 #define GPMC_ECC_CTRL_ECCREG4 0x004
73 #define GPMC_ECC_CTRL_ECCREG5 0x005
74 #define GPMC_ECC_CTRL_ECCREG6 0x006
75 #define GPMC_ECC_CTRL_ECCREG7 0x007
76 #define GPMC_ECC_CTRL_ECCREG8 0x008
77 #define GPMC_ECC_CTRL_ECCREG9 0x009
79 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
81 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
83 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
84 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
85 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
90 #define GPMC_CS0_OFFSET 0x60
91 #define GPMC_CS_SIZE 0x30
92 #define GPMC_BCH_SIZE 0x10
95 * The first 1MB of GPMC address space is typically mapped to
96 * the internal ROM. Never allocate the first page, to
97 * facilitate bug detection; even if we didn't boot from ROM.
98 * As GPMC minimum partition size is 16MB we can only start from
101 #define GPMC_MEM_START 0x1000000
102 #define GPMC_MEM_END 0x3FFFFFFF
104 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
105 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
107 #define CS_NUM_SHIFT 24
108 #define ENABLE_PREFETCH (0x1 << 7)
109 #define DMA_MPU_MODE 2
111 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
112 #define GPMC_REVISION_MINOR(l) (l & 0xf)
114 #define GPMC_HAS_WR_ACCESS 0x1
115 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
116 #define GPMC_HAS_MUX_AAD 0x4
118 #define GPMC_NR_WAITPINS 4
120 #define GPMC_CS_CONFIG1 0x00
121 #define GPMC_CS_CONFIG2 0x04
122 #define GPMC_CS_CONFIG3 0x08
123 #define GPMC_CS_CONFIG4 0x0c
124 #define GPMC_CS_CONFIG5 0x10
125 #define GPMC_CS_CONFIG6 0x14
126 #define GPMC_CS_CONFIG7 0x18
127 #define GPMC_CS_NAND_COMMAND 0x1c
128 #define GPMC_CS_NAND_ADDRESS 0x20
129 #define GPMC_CS_NAND_DATA 0x24
131 /* Control Commands */
132 #define GPMC_CONFIG_RDY_BSY 0x00000001
133 #define GPMC_CONFIG_DEV_SIZE 0x00000002
134 #define GPMC_CONFIG_DEV_TYPE 0x00000003
136 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
137 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
138 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
139 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
140 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
141 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
142 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
143 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
144 /** CLKACTIVATIONTIME Max Ticks */
145 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
146 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
147 /** ATTACHEDDEVICEPAGELENGTH Max Value */
148 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
149 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
150 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
151 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
152 /** WAITMONITORINGTIME Max Ticks */
153 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
154 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
155 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
156 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
157 /** DEVICESIZE Max Value */
158 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
159 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
160 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
161 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
162 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
163 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
164 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
165 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
166 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
167 #define GPMC_CONFIG7_CSVALID (1 << 6)
169 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
170 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
171 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
172 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
173 /* All CONFIG7 bits except reserved bits */
174 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
175 GPMC_CONFIG7_CSVALID_MASK | \
176 GPMC_CONFIG7_MASKADDRESS_MASK)
178 #define GPMC_DEVICETYPE_NOR 0
179 #define GPMC_DEVICETYPE_NAND 2
180 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
181 #define WR_RD_PIN_MONITORING 0x00600000
184 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
185 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
186 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
188 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
190 enum gpmc_clk_domain {
195 struct gpmc_cs_data {
198 #define GPMC_CS_RESERVED (1 << 0)
204 /* Structure to save gpmc cs context */
205 struct gpmc_cs_config {
217 * Structure to save/restore gpmc context
218 * to support core off on OMAP3
220 struct omap3_gpmc_regs {
225 u32 prefetch_config1;
226 u32 prefetch_config2;
227 u32 prefetch_control;
228 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
234 struct irq_chip irq_chip;
235 struct gpio_chip gpio_chip;
239 static struct irq_domain *gpmc_irq_domain;
241 static struct resource gpmc_mem_root;
242 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
243 static DEFINE_SPINLOCK(gpmc_mem_lock);
244 /* Define chip-selects as reserved by default until probe completes */
245 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
246 static unsigned int gpmc_nr_waitpins;
247 static resource_size_t phys_base, mem_size;
248 static unsigned gpmc_capability;
249 static void __iomem *gpmc_base;
251 static struct clk *gpmc_l3_clk;
253 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
255 static void gpmc_write_reg(int idx, u32 val)
257 writel_relaxed(val, gpmc_base + idx);
260 static u32 gpmc_read_reg(int idx)
262 return readl_relaxed(gpmc_base + idx);
265 void gpmc_cs_write_reg(int cs, int idx, u32 val)
267 void __iomem *reg_addr;
269 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
270 writel_relaxed(val, reg_addr);
273 static u32 gpmc_cs_read_reg(int cs, int idx)
275 void __iomem *reg_addr;
277 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
278 return readl_relaxed(reg_addr);
281 /* TODO: Add support for gpmc_fck to clock framework and use it */
282 static unsigned long gpmc_get_fclk_period(void)
284 unsigned long rate = clk_get_rate(gpmc_l3_clk);
287 rate = 1000000000 / rate; /* In picoseconds */
293 * gpmc_get_clk_period - get period of selected clock domain in ps
294 * @cs Chip Select Region.
297 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
298 * prior to calling this function with GPMC_CD_CLK.
300 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303 unsigned long tick_ps = gpmc_get_fclk_period();
309 /* get current clk divider */
310 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
311 div = (l & 0x03) + 1;
312 /* get GPMC_CLK period */
325 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
326 enum gpmc_clk_domain cd)
328 unsigned long tick_ps;
330 /* Calculate in picosecs to yield more exact results */
331 tick_ps = gpmc_get_clk_period(cs, cd);
333 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
336 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
338 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
341 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
343 unsigned long tick_ps;
345 /* Calculate in picosecs to yield more exact results */
346 tick_ps = gpmc_get_fclk_period();
348 return (time_ps + tick_ps - 1) / tick_ps;
351 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
352 enum gpmc_clk_domain cd)
354 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
357 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
359 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
362 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
364 return ticks * gpmc_get_fclk_period();
367 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
369 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
371 return ticks * gpmc_get_fclk_period();
374 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
378 l = gpmc_cs_read_reg(cs, reg);
383 gpmc_cs_write_reg(cs, reg, l);
386 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
388 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
389 GPMC_CONFIG1_TIME_PARA_GRAN,
390 p->time_para_granularity);
391 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
392 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
393 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
394 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
395 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
396 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
397 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
398 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
399 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
400 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
401 p->cycle2cyclesamecsen);
402 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
403 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
404 p->cycle2cyclediffcsen);
407 #ifdef CONFIG_OMAP_GPMC_DEBUG
409 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
410 * @cs: Chip Select Region
411 * @reg: GPMC_CS_CONFIGn register offset.
413 * @end_bit: End Bit. Must be >= @st_bit.
414 * @ma:x Maximum parameter value (before optional @shift).
415 * If 0, maximum is as high as @st_bit and @end_bit allow.
416 * @name: DTS node name, w/o "gpmc,"
417 * @cd: Clock Domain of timing parameter.
418 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
419 * @raw: Raw Format Option.
420 * raw format: gpmc,name = <value>
421 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
422 * Where x ns -- y ns result in the same tick value.
423 * When @max is exceeded, "invalid" is printed inside comment.
424 * @noval: Parameter values equal to 0 are not printed.
425 * @return: Specified timing parameter (after optional @shift).
428 static int get_gpmc_timing_reg(
429 /* timing specifiers */
430 int cs, int reg, int st_bit, int end_bit, int max,
431 const char *name, const enum gpmc_clk_domain cd,
432 /* value transform */
434 /* format specifiers */
435 bool raw, bool noval)
442 l = gpmc_cs_read_reg(cs, reg);
443 nr_bits = end_bit - st_bit + 1;
444 mask = (1 << nr_bits) - 1;
445 l = (l >> st_bit) & mask;
451 if (noval && (l == 0))
454 /* DTS tick format for timings in ns */
455 unsigned int time_ns;
456 unsigned int time_ns_min = 0;
459 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
460 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
461 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
462 name, time_ns, time_ns_min, time_ns, l,
463 invalid ? "; invalid " : " ");
466 pr_info("gpmc,%s = <%u>;%s\n", name, l,
467 invalid ? " /* invalid */" : "");
473 #define GPMC_PRINT_CONFIG(cs, config) \
474 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
475 gpmc_cs_read_reg(cs, config))
476 #define GPMC_GET_RAW(reg, st, end, field) \
477 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
478 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
479 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
480 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
481 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
482 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
483 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
484 #define GPMC_GET_TICKS(reg, st, end, field) \
485 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
486 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
488 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
489 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
491 static void gpmc_show_regs(int cs, const char *desc)
493 pr_info("gpmc cs%i %s:\n", cs, desc);
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
503 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
504 * see commit c9fb809.
506 static void gpmc_cs_show_timings(int cs, const char *desc)
508 gpmc_show_regs(cs, desc);
510 pr_info("gpmc cs%i access configuration:\n", cs);
511 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
512 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
513 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
514 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
515 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
517 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
518 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
519 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
532 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
537 pr_info("gpmc cs%i timings configuration:\n", cs);
538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
545 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
547 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
548 "adv-aad-mux-rd-off-ns");
549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
550 "adv-aad-mux-wr-off-ns");
553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
554 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
555 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
557 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
560 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
568 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
569 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
571 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
572 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
573 "wait-monitoring-ns", GPMC_CD_CLK);
574 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
575 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
576 "clk-activation-ns", GPMC_CD_FCLK);
578 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
579 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
582 static inline void gpmc_cs_show_timings(int cs, const char *desc)
588 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
589 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
590 * prior to calling this function with @cd equal to GPMC_CD_CLK.
592 * @cs: Chip Select Region.
593 * @reg: GPMC_CS_CONFIGn register offset.
595 * @end_bit: End Bit. Must be >= @st_bit.
596 * @max: Maximum parameter value.
597 * If 0, maximum is as high as @st_bit and @end_bit allow.
598 * @time: Timing parameter in ns.
599 * @cd: Timing parameter clock domain.
600 * @name: Timing parameter name.
601 * @return: 0 on success, -1 on error.
603 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
604 int time, enum gpmc_clk_domain cd, const char *name)
607 int ticks, mask, nr_bits;
612 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
613 nr_bits = end_bit - st_bit + 1;
614 mask = (1 << nr_bits) - 1;
620 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
621 __func__, cs, name, time, ticks, max);
626 l = gpmc_cs_read_reg(cs, reg);
627 #ifdef CONFIG_OMAP_GPMC_DEBUG
629 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
630 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
631 (l >> st_bit) & mask, time);
633 l &= ~(mask << st_bit);
634 l |= ticks << st_bit;
635 gpmc_cs_write_reg(cs, reg, l);
640 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
641 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
642 t->field, (cd), #field) < 0) \
645 #define GPMC_SET_ONE(reg, st, end, field) \
646 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
649 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
650 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
651 * read --> don't sample bus too early
652 * write --> data is longer on bus
655 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
656 * / waitmonitoring_ticks)
657 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
660 * @wait_monitoring: WAITMONITORINGTIME in ns.
661 * @return: -1 on failure to scale, else proper divider > 0.
663 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
666 int div = gpmc_ns_to_ticks(wait_monitoring);
668 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
669 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
681 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
682 * @sync_clk: GPMC_CLK period in ps.
683 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
686 int gpmc_calc_divider(unsigned int sync_clk)
688 int div = gpmc_ps_to_ticks(sync_clk);
699 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
700 * @cs: Chip Select Region.
701 * @t: GPMC timing parameters.
702 * @s: GPMC timing settings.
703 * @return: 0 on success, -1 on error.
705 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
706 const struct gpmc_settings *s)
711 div = gpmc_calc_divider(t->sync_clk);
716 * See if we need to change the divider for waitmonitoringtime.
718 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
719 * pure asynchronous accesses, i.e. both read and write asynchronous.
720 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
721 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
723 * This statement must not change div to scale async WAITMONITORINGTIME
724 * to protect mixed synchronous and asynchronous accesses.
726 * We raise an error later if WAITMONITORINGTIME does not fit.
728 if (!s->sync_read && !s->sync_write &&
729 (s->wait_on_read || s->wait_on_write)
732 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
734 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
742 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
743 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
744 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
746 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
747 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
748 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
749 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
751 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
752 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
755 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
756 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
757 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
759 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
762 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
764 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
765 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
766 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
768 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
770 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
771 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
773 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
774 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
775 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
776 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
778 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
781 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
783 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
784 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
785 wait_monitoring, GPMC_CD_CLK);
786 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
787 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
788 clk_activation, GPMC_CD_FCLK);
790 #ifdef CONFIG_OMAP_GPMC_DEBUG
791 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
792 cs, (div * gpmc_get_fclk_period()) / 1000, div);
795 gpmc_cs_bool_timings(cs, &t->bool_timings);
796 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
801 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
807 * Ensure that base address is aligned on a
808 * boundary equal to or greater than size.
810 if (base & (size - 1))
813 base >>= GPMC_CHUNK_SHIFT;
814 mask = (1 << GPMC_SECTION_SHIFT) - size;
815 mask >>= GPMC_CHUNK_SHIFT;
816 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
818 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
819 l &= ~GPMC_CONFIG7_MASK;
820 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
821 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
822 l |= GPMC_CONFIG7_CSVALID;
823 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
828 static void gpmc_cs_enable_mem(int cs)
832 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
833 l |= GPMC_CONFIG7_CSVALID;
834 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
837 static void gpmc_cs_disable_mem(int cs)
841 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
842 l &= ~GPMC_CONFIG7_CSVALID;
843 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
846 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
851 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
852 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
853 mask = (l >> 8) & 0x0f;
854 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
857 static int gpmc_cs_mem_enabled(int cs)
861 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
862 return l & GPMC_CONFIG7_CSVALID;
865 static void gpmc_cs_set_reserved(int cs, int reserved)
867 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
869 gpmc->flags |= GPMC_CS_RESERVED;
872 static bool gpmc_cs_reserved(int cs)
874 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
876 return gpmc->flags & GPMC_CS_RESERVED;
879 static void gpmc_cs_set_name(int cs, const char *name)
881 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
886 static const char *gpmc_cs_get_name(int cs)
888 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
893 static unsigned long gpmc_mem_align(unsigned long size)
897 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
898 order = GPMC_CHUNK_SHIFT - 1;
907 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
909 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
910 struct resource *res = &gpmc->mem;
913 size = gpmc_mem_align(size);
914 spin_lock(&gpmc_mem_lock);
916 res->end = base + size - 1;
917 r = request_resource(&gpmc_mem_root, res);
918 spin_unlock(&gpmc_mem_lock);
923 static int gpmc_cs_delete_mem(int cs)
925 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
926 struct resource *res = &gpmc->mem;
929 spin_lock(&gpmc_mem_lock);
930 r = release_resource(res);
933 spin_unlock(&gpmc_mem_lock);
939 * gpmc_cs_remap - remaps a chip-select physical base address
940 * @cs: chip-select to remap
941 * @base: physical base address to re-map chip-select to
943 * Re-maps a chip-select to a new physical base address specified by
944 * "base". Returns 0 on success and appropriate negative error code
947 static int gpmc_cs_remap(int cs, u32 base)
952 if (cs >= gpmc_cs_num) {
953 pr_err("%s: requested chip-select is disabled\n", __func__);
958 * Make sure we ignore any device offsets from the GPMC partition
959 * allocated for the chip select and that the new base confirms
960 * to the GPMC 16MB minimum granularity.
962 base &= ~(SZ_16M - 1);
964 gpmc_cs_get_memconf(cs, &old_base, &size);
965 if (base == old_base)
968 ret = gpmc_cs_delete_mem(cs);
972 ret = gpmc_cs_insert_mem(cs, base, size);
976 ret = gpmc_cs_set_memconf(cs, base, size);
981 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
983 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
984 struct resource *res = &gpmc->mem;
987 if (cs >= gpmc_cs_num) {
988 pr_err("%s: requested chip-select is disabled\n", __func__);
991 size = gpmc_mem_align(size);
992 if (size > (1 << GPMC_SECTION_SHIFT))
995 spin_lock(&gpmc_mem_lock);
996 if (gpmc_cs_reserved(cs)) {
1000 if (gpmc_cs_mem_enabled(cs))
1001 r = adjust_resource(res, res->start & ~(size - 1), size);
1003 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1008 /* Disable CS while changing base address and size mask */
1009 gpmc_cs_disable_mem(cs);
1011 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1013 release_resource(res);
1018 gpmc_cs_enable_mem(cs);
1020 gpmc_cs_set_reserved(cs, 1);
1022 spin_unlock(&gpmc_mem_lock);
1025 EXPORT_SYMBOL(gpmc_cs_request);
1027 void gpmc_cs_free(int cs)
1029 struct gpmc_cs_data *gpmc;
1030 struct resource *res;
1032 spin_lock(&gpmc_mem_lock);
1033 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1034 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1036 spin_unlock(&gpmc_mem_lock);
1039 gpmc = &gpmc_cs[cs];
1042 gpmc_cs_disable_mem(cs);
1044 release_resource(res);
1045 gpmc_cs_set_reserved(cs, 0);
1046 spin_unlock(&gpmc_mem_lock);
1048 EXPORT_SYMBOL(gpmc_cs_free);
1051 * gpmc_configure - write request to configure gpmc
1052 * @cmd: command type
1053 * @wval: value to write
1054 * @return status of the operation
1056 int gpmc_configure(int cmd, int wval)
1061 case GPMC_CONFIG_WP:
1062 regval = gpmc_read_reg(GPMC_CONFIG);
1064 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1066 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1067 gpmc_write_reg(GPMC_CONFIG, regval);
1071 pr_err("%s: command not supported\n", __func__);
1077 EXPORT_SYMBOL(gpmc_configure);
1079 static bool gpmc_nand_writebuffer_empty(void)
1081 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1087 static struct gpmc_nand_ops nand_ops = {
1088 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1092 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1093 * @regs: the GPMC NAND register map exclusive for NAND use.
1094 * @cs: GPMC chip select number on which the NAND sits. The
1095 * register map returned will be specific to this chip select.
1097 * Returns NULL on error e.g. invalid cs.
1099 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1103 if (cs >= gpmc_cs_num)
1106 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1107 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1108 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1109 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1110 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1111 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1112 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1113 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1114 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1115 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1116 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1117 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1118 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1119 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1121 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1122 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1124 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1126 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1128 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1130 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1132 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1134 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1140 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1142 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1143 struct gpmc_settings *s,
1144 int freq, int latency)
1146 struct gpmc_device_timings dev_t;
1147 const int t_cer = 15;
1148 const int t_avdp = 12;
1149 const int t_cez = 20; /* max of t_cez, t_oez */
1150 const int t_wpl = 40;
1151 const int t_wph = 30;
1152 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1156 min_gpmc_clk_period = 9600; /* 104 MHz */
1165 min_gpmc_clk_period = 12000; /* 83 MHz */
1174 min_gpmc_clk_period = 15000; /* 66 MHz */
1183 min_gpmc_clk_period = 18500; /* 54 MHz */
1193 /* Set synchronous read timings */
1194 memset(&dev_t, 0, sizeof(dev_t));
1196 if (!s->sync_write) {
1197 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1198 dev_t.t_wpl = t_wpl * 1000;
1199 dev_t.t_wph = t_wph * 1000;
1200 dev_t.t_aavdh = t_aavdh * 1000;
1202 dev_t.ce_xdelay = true;
1203 dev_t.avd_xdelay = true;
1204 dev_t.oe_xdelay = true;
1205 dev_t.we_xdelay = true;
1206 dev_t.clk = min_gpmc_clk_period;
1207 dev_t.t_bacc = dev_t.clk;
1208 dev_t.t_ces = t_ces * 1000;
1209 dev_t.t_avds = t_avds * 1000;
1210 dev_t.t_avdh = t_avdh * 1000;
1211 dev_t.t_ach = t_ach * 1000;
1212 dev_t.cyc_iaa = (latency + 1);
1213 dev_t.t_cez_r = t_cez * 1000;
1214 dev_t.t_cez_w = dev_t.t_cez_r;
1215 dev_t.cyc_aavdh_oe = 1;
1216 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1218 gpmc_calc_timings(t, s, &dev_t);
1221 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1223 struct gpmc_onenand_info *info)
1226 struct gpmc_timings gpmc_t;
1227 struct gpmc_settings gpmc_s;
1229 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1231 info->sync_read = gpmc_s.sync_read;
1232 info->sync_write = gpmc_s.sync_write;
1233 info->burst_len = gpmc_s.burst_len;
1235 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1238 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1240 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1244 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1246 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1248 int gpmc_get_client_irq(unsigned irq_config)
1250 if (!gpmc_irq_domain) {
1251 pr_warn("%s called before GPMC IRQ domain available\n",
1256 /* we restrict this to NAND IRQs only */
1257 if (irq_config >= GPMC_NR_NAND_IRQS)
1260 return irq_create_mapping(gpmc_irq_domain, irq_config);
1263 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1267 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1268 if (hwirq >= GPMC_NR_NAND_IRQS)
1269 hwirq += 8 - GPMC_NR_NAND_IRQS;
1271 regval = gpmc_read_reg(GPMC_IRQENABLE);
1273 regval |= BIT(hwirq);
1275 regval &= ~BIT(hwirq);
1276 gpmc_write_reg(GPMC_IRQENABLE, regval);
1281 static void gpmc_irq_disable(struct irq_data *p)
1283 gpmc_irq_endis(p->hwirq, false);
1286 static void gpmc_irq_enable(struct irq_data *p)
1288 gpmc_irq_endis(p->hwirq, true);
1291 static void gpmc_irq_mask(struct irq_data *d)
1293 gpmc_irq_endis(d->hwirq, false);
1296 static void gpmc_irq_unmask(struct irq_data *d)
1298 gpmc_irq_endis(d->hwirq, true);
1301 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1305 /* NAND IRQs polarity is not configurable */
1306 if (hwirq < GPMC_NR_NAND_IRQS)
1309 /* WAITPIN starts at BIT 8 */
1310 hwirq += 8 - GPMC_NR_NAND_IRQS;
1312 regval = gpmc_read_reg(GPMC_CONFIG);
1314 regval &= ~BIT(hwirq);
1316 regval |= BIT(hwirq);
1318 gpmc_write_reg(GPMC_CONFIG, regval);
1321 static void gpmc_irq_ack(struct irq_data *d)
1323 unsigned int hwirq = d->hwirq;
1325 /* skip reserved bits */
1326 if (hwirq >= GPMC_NR_NAND_IRQS)
1327 hwirq += 8 - GPMC_NR_NAND_IRQS;
1329 /* Setting bit to 1 clears (or Acks) the interrupt */
1330 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1333 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1335 /* can't set type for NAND IRQs */
1336 if (d->hwirq < GPMC_NR_NAND_IRQS)
1339 /* We can support either rising or falling edge at a time */
1340 if (trigger == IRQ_TYPE_EDGE_FALLING)
1341 gpmc_irq_edge_config(d->hwirq, false);
1342 else if (trigger == IRQ_TYPE_EDGE_RISING)
1343 gpmc_irq_edge_config(d->hwirq, true);
1350 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1353 struct gpmc_device *gpmc = d->host_data;
1355 irq_set_chip_data(virq, gpmc);
1356 if (hw < GPMC_NR_NAND_IRQS) {
1357 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1358 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1361 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1368 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1369 .map = gpmc_irq_map,
1370 .xlate = irq_domain_xlate_twocell,
1373 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1376 u32 regval, regvalx;
1377 struct gpmc_device *gpmc = data;
1379 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1385 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1386 /* skip reserved status bits */
1387 if (hwirq == GPMC_NR_NAND_IRQS)
1388 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1390 if (regvalx & BIT(hwirq)) {
1391 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1394 "spurious irq detected hwirq %d, virq %d\n",
1398 generic_handle_irq(virq);
1402 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1407 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1412 /* Disable interrupts */
1413 gpmc_write_reg(GPMC_IRQENABLE, 0);
1415 /* clear interrupts */
1416 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1417 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1419 gpmc->irq_chip.name = "gpmc";
1420 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1421 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1422 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1423 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1424 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1425 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1427 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1429 &gpmc_irq_domain_ops,
1431 if (!gpmc_irq_domain) {
1432 dev_err(gpmc->dev, "IRQ domain add failed\n");
1436 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1438 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1440 irq_domain_remove(gpmc_irq_domain);
1441 gpmc_irq_domain = NULL;
1447 static int gpmc_free_irq(struct gpmc_device *gpmc)
1451 free_irq(gpmc->irq, gpmc);
1453 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1454 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1456 irq_domain_remove(gpmc_irq_domain);
1457 gpmc_irq_domain = NULL;
1462 static void gpmc_mem_exit(void)
1466 for (cs = 0; cs < gpmc_cs_num; cs++) {
1467 if (!gpmc_cs_mem_enabled(cs))
1469 gpmc_cs_delete_mem(cs);
1474 static void gpmc_mem_init(void)
1478 gpmc_mem_root.start = GPMC_MEM_START;
1479 gpmc_mem_root.end = GPMC_MEM_END;
1481 /* Reserve all regions that has been set up by bootloader */
1482 for (cs = 0; cs < gpmc_cs_num; cs++) {
1485 if (!gpmc_cs_mem_enabled(cs))
1487 gpmc_cs_get_memconf(cs, &base, &size);
1488 if (gpmc_cs_insert_mem(cs, base, size)) {
1489 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1490 __func__, cs, base, base + size);
1491 gpmc_cs_disable_mem(cs);
1496 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1501 div = gpmc_calc_divider(sync_clk);
1502 temp = gpmc_ps_to_ticks(time_ps);
1503 temp = (temp + div - 1) / div;
1504 return gpmc_ticks_to_ps(temp * div);
1507 /* XXX: can the cycles be avoided ? */
1508 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1509 struct gpmc_device_timings *dev_t,
1515 temp = dev_t->t_avdp_r;
1516 /* XXX: mux check required ? */
1518 /* XXX: t_avdp not to be required for sync, only added for tusb
1519 * this indirectly necessitates requirement of t_avdp_r and
1520 * t_avdp_w instead of having a single t_avdp
1522 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1523 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1525 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1528 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1530 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1531 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1532 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1534 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1537 /* XXX: any scope for improvement ?, by combining oe_on
1538 * and clk_activation, need to check whether
1539 * access = clk_activation + round to sync clk ?
1541 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1542 temp += gpmc_t->clk_activation;
1544 temp = max_t(u32, temp, gpmc_t->oe_on +
1545 gpmc_ticks_to_ps(dev_t->cyc_oe));
1546 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1548 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1549 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1552 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1553 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1555 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1556 if (dev_t->t_ce_rdyz)
1557 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1558 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1563 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1564 struct gpmc_device_timings *dev_t,
1570 temp = dev_t->t_avdp_w;
1572 temp = max_t(u32, temp,
1573 gpmc_t->clk_activation + dev_t->t_avdh);
1574 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1576 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1578 /* wr_data_mux_bus */
1579 temp = max_t(u32, dev_t->t_weasu,
1580 gpmc_t->clk_activation + dev_t->t_rdyo);
1581 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1582 * and in that case remember to handle we_on properly
1585 temp = max_t(u32, temp,
1586 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1587 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1588 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1590 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1593 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1594 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1596 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1599 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1600 gpmc_t->wr_access = gpmc_t->access;
1603 temp = gpmc_t->we_on + dev_t->t_wpl;
1604 temp = max_t(u32, temp,
1605 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1606 temp = max_t(u32, temp,
1607 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1608 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1610 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1614 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1615 temp += gpmc_t->wr_access;
1616 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1617 if (dev_t->t_ce_rdyz)
1618 temp = max_t(u32, temp,
1619 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1620 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1625 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1626 struct gpmc_device_timings *dev_t,
1632 temp = dev_t->t_avdp_r;
1634 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1635 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1638 temp = dev_t->t_oeasu;
1640 temp = max_t(u32, temp,
1641 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1642 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1645 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1646 gpmc_t->oe_on + dev_t->t_oe);
1647 temp = max_t(u32, temp,
1648 gpmc_t->cs_on + dev_t->t_ce);
1649 temp = max_t(u32, temp,
1650 gpmc_t->adv_on + dev_t->t_aa);
1651 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1653 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1654 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1657 temp = max_t(u32, dev_t->t_rd_cycle,
1658 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1659 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1660 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1665 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1666 struct gpmc_device_timings *dev_t,
1672 temp = dev_t->t_avdp_w;
1674 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1675 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1677 /* wr_data_mux_bus */
1678 temp = dev_t->t_weasu;
1680 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1681 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1682 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1684 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1687 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1688 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1690 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1693 temp = gpmc_t->we_on + dev_t->t_wpl;
1694 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1696 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1700 temp = max_t(u32, dev_t->t_wr_cycle,
1701 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1702 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1707 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1708 struct gpmc_device_timings *dev_t)
1712 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1713 gpmc_get_fclk_period();
1715 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1719 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1720 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1722 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1725 if (dev_t->ce_xdelay)
1726 gpmc_t->bool_timings.cs_extra_delay = true;
1727 if (dev_t->avd_xdelay)
1728 gpmc_t->bool_timings.adv_extra_delay = true;
1729 if (dev_t->oe_xdelay)
1730 gpmc_t->bool_timings.oe_extra_delay = true;
1731 if (dev_t->we_xdelay)
1732 gpmc_t->bool_timings.we_extra_delay = true;
1737 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1738 struct gpmc_device_timings *dev_t,
1744 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1747 temp = dev_t->t_avdasu;
1748 if (dev_t->t_ce_avd)
1749 temp = max_t(u32, temp,
1750 gpmc_t->cs_on + dev_t->t_ce_avd);
1751 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1754 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1759 /* TODO: remove this function once all peripherals are confirmed to
1760 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1761 * has to be modified to handle timings in ps instead of ns
1763 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1766 t->cs_rd_off /= 1000;
1767 t->cs_wr_off /= 1000;
1769 t->adv_rd_off /= 1000;
1770 t->adv_wr_off /= 1000;
1775 t->page_burst_access /= 1000;
1777 t->rd_cycle /= 1000;
1778 t->wr_cycle /= 1000;
1779 t->bus_turnaround /= 1000;
1780 t->cycle2cycle_delay /= 1000;
1781 t->wait_monitoring /= 1000;
1782 t->clk_activation /= 1000;
1783 t->wr_access /= 1000;
1784 t->wr_data_mux_bus /= 1000;
1787 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1788 struct gpmc_settings *gpmc_s,
1789 struct gpmc_device_timings *dev_t)
1791 bool mux = false, sync = false;
1794 mux = gpmc_s->mux_add_data ? true : false;
1795 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1798 memset(gpmc_t, 0, sizeof(*gpmc_t));
1800 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1802 if (gpmc_s && gpmc_s->sync_read)
1803 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1805 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1807 if (gpmc_s && gpmc_s->sync_write)
1808 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1810 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1812 /* TODO: remove, see function definition */
1813 gpmc_convert_ps_to_ns(gpmc_t);
1819 * gpmc_cs_program_settings - programs non-timing related settings
1820 * @cs: GPMC chip-select to program
1821 * @p: pointer to GPMC settings structure
1823 * Programs non-timing related settings for a GPMC chip-select, such as
1824 * bus-width, burst configuration, etc. Function should be called once
1825 * for each chip-select that is being used and must be called before
1826 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1827 * register will be initialised to zero by this function. Returns 0 on
1828 * success and appropriate negative error code on failure.
1830 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1834 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1835 pr_err("%s: invalid width %d!", __func__, p->device_width);
1839 /* Address-data multiplexing not supported for NAND devices */
1840 if (p->device_nand && p->mux_add_data) {
1841 pr_err("%s: invalid configuration!\n", __func__);
1845 if ((p->mux_add_data > GPMC_MUX_AD) ||
1846 ((p->mux_add_data == GPMC_MUX_AAD) &&
1847 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1848 pr_err("%s: invalid multiplex configuration!\n", __func__);
1852 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1853 if (p->burst_read || p->burst_write) {
1854 switch (p->burst_len) {
1860 pr_err("%s: invalid page/burst-length (%d)\n",
1861 __func__, p->burst_len);
1866 if (p->wait_pin > gpmc_nr_waitpins) {
1867 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1871 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1874 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1876 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1877 if (p->wait_on_read)
1878 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1879 if (p->wait_on_write)
1880 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1881 if (p->wait_on_read || p->wait_on_write)
1882 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1884 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1885 if (p->mux_add_data)
1886 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1888 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1890 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1891 if (p->burst_read || p->burst_write) {
1892 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1893 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1896 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1902 static const struct of_device_id gpmc_dt_ids[] = {
1903 { .compatible = "ti,omap2420-gpmc" },
1904 { .compatible = "ti,omap2430-gpmc" },
1905 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1906 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1907 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1912 * gpmc_read_settings_dt - read gpmc settings from device-tree
1913 * @np: pointer to device-tree node for a gpmc child device
1914 * @p: pointer to gpmc settings structure
1916 * Reads the GPMC settings for a GPMC child device from device-tree and
1917 * stores them in the GPMC settings structure passed. The GPMC settings
1918 * structure is initialised to zero by this function and so any
1919 * previously stored settings will be cleared.
1921 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1923 memset(p, 0, sizeof(struct gpmc_settings));
1925 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1926 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1927 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1928 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1930 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1931 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1932 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1933 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1934 if (!p->burst_read && !p->burst_write)
1935 pr_warn("%s: page/burst-length set but not used!\n",
1939 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1940 p->wait_on_read = of_property_read_bool(np,
1941 "gpmc,wait-on-read");
1942 p->wait_on_write = of_property_read_bool(np,
1943 "gpmc,wait-on-write");
1944 if (!p->wait_on_read && !p->wait_on_write)
1945 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1950 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1951 struct gpmc_timings *gpmc_t)
1953 struct gpmc_bool_timings *p;
1958 memset(gpmc_t, 0, sizeof(*gpmc_t));
1960 /* minimum clock period for syncronous mode */
1961 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1963 /* chip select timtings */
1964 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1965 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1966 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1968 /* ADV signal timings */
1969 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1970 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1971 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1972 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1973 &gpmc_t->adv_aad_mux_on);
1974 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1975 &gpmc_t->adv_aad_mux_rd_off);
1976 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1977 &gpmc_t->adv_aad_mux_wr_off);
1979 /* WE signal timings */
1980 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1981 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1983 /* OE signal timings */
1984 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1985 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1986 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1987 &gpmc_t->oe_aad_mux_on);
1988 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1989 &gpmc_t->oe_aad_mux_off);
1991 /* access and cycle timings */
1992 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1993 &gpmc_t->page_burst_access);
1994 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1995 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1996 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1997 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1998 &gpmc_t->bus_turnaround);
1999 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2000 &gpmc_t->cycle2cycle_delay);
2001 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2002 &gpmc_t->wait_monitoring);
2003 of_property_read_u32(np, "gpmc,clk-activation-ns",
2004 &gpmc_t->clk_activation);
2006 /* only applicable to OMAP3+ */
2007 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2008 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2009 &gpmc_t->wr_data_mux_bus);
2011 /* bool timing parameters */
2012 p = &gpmc_t->bool_timings;
2014 p->cycle2cyclediffcsen =
2015 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2016 p->cycle2cyclesamecsen =
2017 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2018 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2019 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2020 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2021 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2022 p->time_para_granularity =
2023 of_property_read_bool(np, "gpmc,time-para-granularity");
2027 * gpmc_probe_generic_child - configures the gpmc for a child device
2028 * @pdev: pointer to gpmc platform device
2029 * @child: pointer to device-tree node for child device
2031 * Allocates and configures a GPMC chip-select for a child device.
2032 * Returns 0 on success and appropriate negative error code on failure.
2034 static int gpmc_probe_generic_child(struct platform_device *pdev,
2035 struct device_node *child)
2037 struct gpmc_settings gpmc_s;
2038 struct gpmc_timings gpmc_t;
2039 struct resource res;
2044 struct gpio_desc *waitpin_desc = NULL;
2045 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2047 if (of_property_read_u32(child, "reg", &cs) < 0) {
2048 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2053 if (of_address_to_resource(child, 0, &res) < 0) {
2054 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2060 * Check if we have multiple instances of the same device
2061 * on a single chip select. If so, use the already initialized
2064 name = gpmc_cs_get_name(cs);
2065 if (name && of_node_name_eq(child, name))
2068 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2070 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2073 gpmc_cs_set_name(cs, child->full_name);
2075 gpmc_read_settings_dt(child, &gpmc_s);
2076 gpmc_read_timings_dt(child, &gpmc_t);
2079 * For some GPMC devices we still need to rely on the bootloader
2080 * timings because the devices can be connected via FPGA.
2081 * REVISIT: Add timing support from slls644g.pdf.
2083 if (!gpmc_t.cs_rd_off) {
2084 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2086 gpmc_cs_show_timings(cs,
2087 "please add GPMC bootloader timings to .dts");
2091 /* CS must be disabled while making changes to gpmc configuration */
2092 gpmc_cs_disable_mem(cs);
2095 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2096 * location in the gpmc address space. When booting with
2097 * device-tree we want the NOR flash to be mapped to the
2098 * location specified in the device-tree blob. So remap the
2099 * CS to this location. Once DT migration is complete should
2100 * just make gpmc_cs_request() map a specific address.
2102 ret = gpmc_cs_remap(cs, res.start);
2104 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2106 if (res.start < GPMC_MEM_START) {
2107 dev_info(&pdev->dev,
2108 "GPMC CS %d start cannot be lesser than 0x%x\n",
2109 cs, GPMC_MEM_START);
2110 } else if (res.end > GPMC_MEM_END) {
2111 dev_info(&pdev->dev,
2112 "GPMC CS %d end cannot be greater than 0x%x\n",
2118 if (of_node_name_eq(child, "nand")) {
2119 /* Warn about older DT blobs with no compatible property */
2120 if (!of_property_read_bool(child, "compatible")) {
2121 dev_warn(&pdev->dev,
2122 "Incompatible NAND node: missing compatible");
2128 if (of_node_name_eq(child, "onenand")) {
2129 /* Warn about older DT blobs with no compatible property */
2130 if (!of_property_read_bool(child, "compatible")) {
2131 dev_warn(&pdev->dev,
2132 "Incompatible OneNAND node: missing compatible");
2138 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2139 /* NAND specific setup */
2141 of_property_read_u32(child, "nand-bus-width", &val);
2144 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2147 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2150 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2156 /* disable write protect */
2157 gpmc_configure(GPMC_CONFIG_WP, 0);
2158 gpmc_s.device_nand = true;
2160 ret = of_property_read_u32(child, "bank-width",
2161 &gpmc_s.device_width);
2162 if (ret < 0 && !gpmc_s.device_width) {
2164 "%pOF has no 'gpmc,device-width' property\n",
2170 /* Reserve wait pin if it is required and valid */
2171 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2172 unsigned int wait_pin = gpmc_s.wait_pin;
2174 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2175 wait_pin, "WAITPIN",
2178 if (IS_ERR(waitpin_desc)) {
2179 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2180 ret = PTR_ERR(waitpin_desc);
2185 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2187 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2191 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2193 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2198 /* Clear limited address i.e. enable A26-A11 */
2199 val = gpmc_read_reg(GPMC_CONFIG);
2200 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2201 gpmc_write_reg(GPMC_CONFIG, val);
2203 /* Enable CS region */
2204 gpmc_cs_enable_mem(cs);
2208 /* create platform device, NULL on error or when disabled */
2209 if (!of_platform_device_create(child, NULL, &pdev->dev))
2210 goto err_child_fail;
2212 /* is child a common bus? */
2213 if (of_match_node(of_default_bus_match_table, child))
2214 /* create children and other common bus children */
2215 if (of_platform_default_populate(child, NULL, &pdev->dev))
2216 goto err_child_fail;
2222 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2226 gpiochip_free_own_desc(waitpin_desc);
2233 static int gpmc_probe_dt(struct platform_device *pdev)
2236 const struct of_device_id *of_id =
2237 of_match_device(gpmc_dt_ids, &pdev->dev);
2242 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2245 pr_err("%s: number of chip-selects not defined\n", __func__);
2247 } else if (gpmc_cs_num < 1) {
2248 pr_err("%s: all chip-selects are disabled\n", __func__);
2250 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2251 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2252 __func__, GPMC_CS_NUM);
2256 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2259 pr_err("%s: number of wait pins not found!\n", __func__);
2266 static void gpmc_probe_dt_children(struct platform_device *pdev)
2269 struct device_node *child;
2271 for_each_available_child_of_node(pdev->dev.of_node, child) {
2272 ret = gpmc_probe_generic_child(pdev, child);
2274 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2280 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2282 memset(p, 0, sizeof(*p));
2284 static int gpmc_probe_dt(struct platform_device *pdev)
2289 static void gpmc_probe_dt_children(struct platform_device *pdev)
2292 #endif /* CONFIG_OF */
2294 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2296 return 1; /* we're input only */
2299 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2300 unsigned int offset)
2302 return 0; /* we're input only */
2305 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2306 unsigned int offset, int value)
2308 return -EINVAL; /* we're input only */
2311 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2316 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2322 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2327 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2331 gpmc->gpio_chip.parent = gpmc->dev;
2332 gpmc->gpio_chip.owner = THIS_MODULE;
2333 gpmc->gpio_chip.label = DEVICE_NAME;
2334 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2335 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2336 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2337 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2338 gpmc->gpio_chip.set = gpmc_gpio_set;
2339 gpmc->gpio_chip.get = gpmc_gpio_get;
2340 gpmc->gpio_chip.base = -1;
2342 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2344 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2351 static int gpmc_probe(struct platform_device *pdev)
2355 struct resource *res;
2356 struct gpmc_device *gpmc;
2358 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2362 gpmc->dev = &pdev->dev;
2363 platform_set_drvdata(pdev, gpmc);
2365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2369 phys_base = res->start;
2370 mem_size = resource_size(res);
2372 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2373 if (IS_ERR(gpmc_base))
2374 return PTR_ERR(gpmc_base);
2376 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2378 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2382 gpmc->irq = res->start;
2384 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2385 if (IS_ERR(gpmc_l3_clk)) {
2386 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2387 return PTR_ERR(gpmc_l3_clk);
2390 if (!clk_get_rate(gpmc_l3_clk)) {
2391 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2395 if (pdev->dev.of_node) {
2396 rc = gpmc_probe_dt(pdev);
2400 gpmc_cs_num = GPMC_CS_NUM;
2401 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2404 pm_runtime_enable(&pdev->dev);
2405 pm_runtime_get_sync(&pdev->dev);
2407 l = gpmc_read_reg(GPMC_REVISION);
2410 * FIXME: Once device-tree migration is complete the below flags
2411 * should be populated based upon the device-tree compatible
2412 * string. For now just use the IP revision. OMAP3+ devices have
2413 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2414 * devices support the addr-addr-data multiplex protocol.
2416 * GPMC IP revisions:
2419 * - OMAP44xx/54xx/AM335x = 6.0
2421 if (GPMC_REVISION_MAJOR(l) > 0x4)
2422 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2423 if (GPMC_REVISION_MAJOR(l) > 0x5)
2424 gpmc_capability |= GPMC_HAS_MUX_AAD;
2425 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2426 GPMC_REVISION_MINOR(l));
2429 rc = gpmc_gpio_init(gpmc);
2431 goto gpio_init_failed;
2433 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2434 rc = gpmc_setup_irq(gpmc);
2436 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2437 goto gpio_init_failed;
2440 gpmc_probe_dt_children(pdev);
2446 pm_runtime_put_sync(&pdev->dev);
2447 pm_runtime_disable(&pdev->dev);
2452 static int gpmc_remove(struct platform_device *pdev)
2454 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2456 gpmc_free_irq(gpmc);
2458 pm_runtime_put_sync(&pdev->dev);
2459 pm_runtime_disable(&pdev->dev);
2464 #ifdef CONFIG_PM_SLEEP
2465 static int gpmc_suspend(struct device *dev)
2467 omap3_gpmc_save_context();
2468 pm_runtime_put_sync(dev);
2472 static int gpmc_resume(struct device *dev)
2474 pm_runtime_get_sync(dev);
2475 omap3_gpmc_restore_context();
2480 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2482 static struct platform_driver gpmc_driver = {
2483 .probe = gpmc_probe,
2484 .remove = gpmc_remove,
2486 .name = DEVICE_NAME,
2487 .of_match_table = of_match_ptr(gpmc_dt_ids),
2492 static __init int gpmc_init(void)
2494 return platform_driver_register(&gpmc_driver);
2496 postcore_initcall(gpmc_init);
2498 static struct omap3_gpmc_regs gpmc_context;
2500 void omap3_gpmc_save_context(void)
2507 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2508 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2509 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2510 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2511 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2512 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2513 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2514 for (i = 0; i < gpmc_cs_num; i++) {
2515 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2516 if (gpmc_context.cs_context[i].is_valid) {
2517 gpmc_context.cs_context[i].config1 =
2518 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2519 gpmc_context.cs_context[i].config2 =
2520 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2521 gpmc_context.cs_context[i].config3 =
2522 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2523 gpmc_context.cs_context[i].config4 =
2524 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2525 gpmc_context.cs_context[i].config5 =
2526 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2527 gpmc_context.cs_context[i].config6 =
2528 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2529 gpmc_context.cs_context[i].config7 =
2530 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2535 void omap3_gpmc_restore_context(void)
2542 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2543 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2544 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2545 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2546 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2547 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2548 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2549 for (i = 0; i < gpmc_cs_num; i++) {
2550 if (gpmc_context.cs_context[i].is_valid) {
2551 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2552 gpmc_context.cs_context[i].config1);
2553 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2554 gpmc_context.cs_context[i].config2);
2555 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2556 gpmc_context.cs_context[i].config3);
2557 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2558 gpmc_context.cs_context[i].config4);
2559 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2560 gpmc_context.cs_context[i].config5);
2561 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2562 gpmc_context.cs_context[i].config6);
2563 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2564 gpmc_context.cs_context[i].config7);