drivers/memory/fsl_ifc.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc
   3  *
   4  * Freescale Integrated Flash Controller
   5  *
   6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/compiler.h>
  25 #include <linux/sched.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/fsl_ifc.h>
  34 #include <linux/irqdomain.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37
  38 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
  39 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
  40
  41 /*
  42  * convert_ifc_address - convert the base address
  43  * @addr_base:  base address of the memory bank
  44  */
  45 unsigned int convert_ifc_address(phys_addr_t addr_base)
  46 {
  47         return addr_base & CSPR_BA;
  48 }
  49 EXPORT_SYMBOL(convert_ifc_address);
  50
  51 /*
  52  * fsl_ifc_find - find IFC bank
  53  * @addr_base:  base address of the memory bank
  54  *
  55  * This function walks IFC banks comparing "Base address" field of the CSPR
  56  * registers with the supplied addr_base argument. When bases match this
  57  * function returns bank number (starting with 0), otherwise it returns
  58  * appropriate errno value.
  59  */
  60 int fsl_ifc_find(phys_addr_t addr_base)
  61 {
  62         int i = 0;
  63
  64         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
  65                 return -ENODEV;
  66
  67         for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
  68                 u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
  69                 if (cspr & CSPR_V && (cspr & CSPR_BA) ==
  70                                 convert_ifc_address(addr_base))
  71                         return i;
  72         }
  73
  74         return -ENOENT;
  75 }
  76 EXPORT_SYMBOL(fsl_ifc_find);
  77
  78 static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
  79 {
  80         struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
  81
  82         /*
  83          * Clear all the common status and event registers
  84          */
  85         if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
  86                 ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
  87
  88         /* enable all error and events */
  89         ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
  90
  91         /* enable all error and event interrupts */
  92         ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
  93         ifc_out32(0x0, &ifc->cm_erattr0);
  94         ifc_out32(0x0, &ifc->cm_erattr1);
  95
  96         return 0;
  97 }
  98
  99 static int fsl_ifc_ctrl_remove(struct platform_device *dev)
 100 {
 101         struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
 102
 103         free_irq(ctrl->nand_irq, ctrl);
 104         free_irq(ctrl->irq, ctrl);
 105
 106         irq_dispose_mapping(ctrl->nand_irq);
 107         irq_dispose_mapping(ctrl->irq);
 108
 109         iounmap(ctrl->gregs);
 110
 111         dev_set_drvdata(&dev->dev, NULL);
 112
 113         return 0;
 114 }
 115
 116 /*
 117  * NAND events are split between an operational interrupt which only
 118  * receives OPC, and an error interrupt that receives everything else,
 119  * including non-NAND errors.  Whichever interrupt gets to it first
 120  * records the status and wakes the wait queue.
 121  */
 122 static DEFINE_SPINLOCK(nand_irq_lock);
 123
 124 static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
 125 {
 126         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 127         unsigned long flags;
 128         u32 stat;
 129
 130         spin_lock_irqsave(&nand_irq_lock, flags);
 131
 132         stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 133         if (stat) {
 134                 ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
 135                 ctrl->nand_stat = stat;
 136                 wake_up(&ctrl->nand_wait);
 137         }
 138
 139         spin_unlock_irqrestore(&nand_irq_lock, flags);
 140
 141         return stat;
 142 }
 143
 144 static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
 145 {
 146         struct fsl_ifc_ctrl *ctrl = data;
 147
 148         if (check_nand_stat(ctrl))
 149                 return IRQ_HANDLED;
 150
 151         return IRQ_NONE;
 152 }
 153
 154 /*
 155  * NOTE: This interrupt is used to report ifc events of various kinds,
 156  * such as transaction errors on the chipselects.
 157  */
 158 static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
 159 {
 160         struct fsl_ifc_ctrl *ctrl = data;
 161         struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
 162         u32 err_axiid, err_srcid, status, cs_err, err_addr;
 163         irqreturn_t ret = IRQ_NONE;
 164
 165         /* read for chip select error */
 166         cs_err = ifc_in32(&ifc->cm_evter_stat);
 167         if (cs_err) {
 168                 dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
 169                                 "any memory bank 0x%08X\n", cs_err);
 170                 /* clear the chip select error */
 171                 ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
 172
 173                 /* read error attribute registers print the error information */
 174                 status = ifc_in32(&ifc->cm_erattr0);
 175                 err_addr = ifc_in32(&ifc->cm_erattr1);
 176
 177                 if (status & IFC_CM_ERATTR0_ERTYP_READ)
 178                         dev_err(ctrl->dev, "Read transaction error"
 179                                 "CM_ERATTR0 0x%08X\n", status);
 180                 else
 181                         dev_err(ctrl->dev, "Write transaction error"
 182                                 "CM_ERATTR0 0x%08X\n", status);
 183
 184                 err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
 185                                         IFC_CM_ERATTR0_ERAID_SHIFT;
 186                 dev_err(ctrl->dev, "AXI ID of the error"
 187                                         "transaction 0x%08X\n", err_axiid);
 188
 189                 err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
 190                                         IFC_CM_ERATTR0_ESRCID_SHIFT;
 191                 dev_err(ctrl->dev, "SRC ID of the error"
 192                                         "transaction 0x%08X\n", err_srcid);
 193
 194                 dev_err(ctrl->dev, "Transaction Address corresponding to error"
 195                                         "ERADDR 0x%08X\n", err_addr);
 196
 197                 ret = IRQ_HANDLED;
 198         }
 199
 200         if (check_nand_stat(ctrl))
 201                 ret = IRQ_HANDLED;
 202
 203         return ret;
 204 }
 205
 206 /*
 207  * fsl_ifc_ctrl_probe
 208  *
 209  * called by device layer when it finds a device matching
 210  * one our driver can handled. This code allocates all of
 211  * the resources needed for the controller only.  The
 212  * resources for the NAND banks themselves are allocated
 213  * in the chip probe function.
 214 */
 215 static int fsl_ifc_ctrl_probe(struct platform_device *dev)
 216 {
 217         int ret = 0;
 218         int version, banks;
 219         void __iomem *addr;
 220
 221         dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
 222
 223         fsl_ifc_ctrl_dev = devm_kzalloc(&dev->dev, sizeof(*fsl_ifc_ctrl_dev),
 224                                         GFP_KERNEL);
 225         if (!fsl_ifc_ctrl_dev)
 226                 return -ENOMEM;
 227
 228         dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
 229
 230         /* IOMAP the entire IFC region */
 231         fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
 232         if (!fsl_ifc_ctrl_dev->gregs) {
 233                 dev_err(&dev->dev, "failed to get memory region\n");
 234                 return -ENODEV;
 235         }
 236
 237         if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
 238                 fsl_ifc_ctrl_dev->little_endian = true;
 239                 dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
 240         } else {
 241                 fsl_ifc_ctrl_dev->little_endian = false;
 242                 dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
 243         }
 244
 245         version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
 246                         FSL_IFC_VERSION_MASK;
 247
 248         banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
 249         dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
 250                 version >> 24, (version >> 16) & 0xf, banks);
 251
 252         fsl_ifc_ctrl_dev->version = version;
 253         fsl_ifc_ctrl_dev->banks = banks;
 254
 255         addr = fsl_ifc_ctrl_dev->gregs;
 256         if (version >= FSL_IFC_VERSION_2_0_0)
 257                 addr += PGOFFSET_64K;
 258         else
 259                 addr += PGOFFSET_4K;
 260         fsl_ifc_ctrl_dev->rregs = addr;
 261
 262         /* get the Controller level irq */
 263         fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
 264         if (fsl_ifc_ctrl_dev->irq == 0) {
 265                 dev_err(&dev->dev, "failed to get irq resource "
 266                                                         "for IFC\n");
 267                 ret = -ENODEV;
 268                 goto err;
 269         }
 270
 271         /* get the nand machine irq */
 272         fsl_ifc_ctrl_dev->nand_irq =
 273                         irq_of_parse_and_map(dev->dev.of_node, 1);
 274
 275         fsl_ifc_ctrl_dev->dev = &dev->dev;
 276
 277         ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
 278         if (ret < 0)
 279                 goto err_unmap_nandirq;
 280
 281         init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
 282
 283         ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
 284                           "fsl-ifc", fsl_ifc_ctrl_dev);
 285         if (ret != 0) {
 286                 dev_err(&dev->dev, "failed to install irq (%d)\n",
 287                         fsl_ifc_ctrl_dev->irq);
 288                 goto err_unmap_nandirq;
 289         }
 290
 291         if (fsl_ifc_ctrl_dev->nand_irq) {
 292                 ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
 293                                 0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
 294                 if (ret != 0) {
 295                         dev_err(&dev->dev, "failed to install irq (%d)\n",
 296                                 fsl_ifc_ctrl_dev->nand_irq);
 297                         goto err_free_irq;
 298                 }
 299         }
 300
 301         return 0;
 302
 303 err_free_irq:
 304         free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
 305 err_unmap_nandirq:
 306         irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
 307         irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
 308 err:
 309         iounmap(fsl_ifc_ctrl_dev->gregs);
 310         return ret;
 311 }
 312
 313 static const struct of_device_id fsl_ifc_match[] = {
 314         {
 315                 .compatible = "fsl,ifc",
 316         },
 317         {},
 318 };
 319
 320 static struct platform_driver fsl_ifc_ctrl_driver = {
 321         .driver = {
 322                 .name   = "fsl-ifc",
 323                 .of_match_table = fsl_ifc_match,
 324         },
 325         .probe       = fsl_ifc_ctrl_probe,
 326         .remove      = fsl_ifc_ctrl_remove,
 327 };
 328
 329 static int __init fsl_ifc_init(void)
 330 {
 331         return platform_driver_register(&fsl_ifc_ctrl_driver);
 332 }
 333 subsys_initcall(fsl_ifc_init);
 334
 335 MODULE_LICENSE("GPL");
 336 MODULE_AUTHOR("Freescale Semiconductor");
 337 MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");