drivers/memory/emif.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * EMIF driver
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  */
  10 #include <linux/err.h>
  11 #include <linux/kernel.h>
  12 #include <linux/reboot.h>
  13 #include <linux/platform_data/emif_plat.h>
  14 #include <linux/io.h>
  15 #include <linux/device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/of.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/module.h>
  23 #include <linux/list.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/pm.h>
  26
  27 #include "emif.h"
  28 #include "jedec_ddr.h"
  29 #include "of_memory.h"
  30
  31 /**
  32  * struct emif_data - Per device static data for driver's use
  33  * @duplicate:                  Whether the DDR devices attached to this EMIF
  34  *                              instance are exactly same as that on EMIF1. In
  35  *                              this case we can save some memory and processing
  36  * @temperature_level:          Maximum temperature of LPDDR2 devices attached
  37  *                              to this EMIF - read from MR4 register. If there
  38  *                              are two devices attached to this EMIF, this
  39  *                              value is the maximum of the two temperature
  40  *                              levels.
  41  * @node:                       node in the device list
  42  * @base:                       base address of memory-mapped IO registers.
  43  * @dev:                        device pointer.
  44  * @addressing                  table with addressing information from the spec
  45  * @regs_cache:                 An array of 'struct emif_regs' that stores
  46  *                              calculated register values for different
  47  *                              frequencies, to avoid re-calculating them on
  48  *                              each DVFS transition.
  49  * @curr_regs:                  The set of register values used in the last
  50  *                              frequency change (i.e. corresponding to the
  51  *                              frequency in effect at the moment)
  52  * @plat_data:                  Pointer to saved platform data.
  53  * @debugfs_root:               dentry to the root folder for EMIF in debugfs
  54  * @np_ddr:                     Pointer to ddr device tree node
  55  */
  56 struct emif_data {
  57         u8                              duplicate;
  58         u8                              temperature_level;
  59         u8                              lpmode;
  60         struct list_head                node;
  61         unsigned long                   irq_state;
  62         void __iomem                    *base;
  63         struct device                   *dev;
  64         const struct lpddr2_addressing  *addressing;
  65         struct emif_regs                *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
  66         struct emif_regs                *curr_regs;
  67         struct emif_platform_data       *plat_data;
  68         struct dentry                   *debugfs_root;
  69         struct device_node              *np_ddr;
  70 };
  71
  72 static struct emif_data *emif1;
  73 static spinlock_t       emif_lock;
  74 static unsigned long    irq_state;
  75 static u32              t_ck; /* DDR clock period in ps */
  76 static LIST_HEAD(device_list);
  77
  78 #ifdef CONFIG_DEBUG_FS
  79 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
  80         struct emif_regs *regs)
  81 {
  82         u32 type = emif->plat_data->device_info->type;
  83         u32 ip_rev = emif->plat_data->ip_rev;
  84
  85         seq_printf(s, "EMIF register cache dump for %dMHz\n",
  86                 regs->freq/1000000);
  87
  88         seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
  89         seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
  90         seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
  91         seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
  92
  93         if (ip_rev == EMIF_4D) {
  94                 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
  95                         regs->read_idle_ctrl_shdw_normal);
  96                 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
  97                         regs->read_idle_ctrl_shdw_volt_ramp);
  98         } else if (ip_rev == EMIF_4D5) {
  99                 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
 100                         regs->dll_calib_ctrl_shdw_normal);
 101                 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
 102                         regs->dll_calib_ctrl_shdw_volt_ramp);
 103         }
 104
 105         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
 106                 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
 107                         regs->ref_ctrl_shdw_derated);
 108                 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
 109                         regs->sdram_tim1_shdw_derated);
 110                 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
 111                         regs->sdram_tim3_shdw_derated);
 112         }
 113 }
 114
 115 static int emif_regdump_show(struct seq_file *s, void *unused)
 116 {
 117         struct emif_data        *emif   = s->private;
 118         struct emif_regs        **regs_cache;
 119         int                     i;
 120
 121         if (emif->duplicate)
 122                 regs_cache = emif1->regs_cache;
 123         else
 124                 regs_cache = emif->regs_cache;
 125
 126         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
 127                 do_emif_regdump_show(s, emif, regs_cache[i]);
 128                 seq_putc(s, '\n');
 129         }
 130
 131         return 0;
 132 }
 133
 134 static int emif_regdump_open(struct inode *inode, struct file *file)
 135 {
 136         return single_open(file, emif_regdump_show, inode->i_private);
 137 }
 138
 139 static const struct file_operations emif_regdump_fops = {
 140         .open                   = emif_regdump_open,
 141         .read                   = seq_read,
 142         .release                = single_release,
 143 };
 144
 145 static int emif_mr4_show(struct seq_file *s, void *unused)
 146 {
 147         struct emif_data *emif = s->private;
 148
 149         seq_printf(s, "MR4=%d\n", emif->temperature_level);
 150         return 0;
 151 }
 152
 153 static int emif_mr4_open(struct inode *inode, struct file *file)
 154 {
 155         return single_open(file, emif_mr4_show, inode->i_private);
 156 }
 157
 158 static const struct file_operations emif_mr4_fops = {
 159         .open                   = emif_mr4_open,
 160         .read                   = seq_read,
 161         .release                = single_release,
 162 };
 163
 164 static int __init_or_module emif_debugfs_init(struct emif_data *emif)
 165 {
 166         emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
 167         debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
 168                             &emif_regdump_fops);
 169         debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,
 170                             &emif_mr4_fops);
 171         return 0;
 172 }
 173
 174 static void __exit emif_debugfs_exit(struct emif_data *emif)
 175 {
 176         debugfs_remove_recursive(emif->debugfs_root);
 177         emif->debugfs_root = NULL;
 178 }
 179 #else
 180 static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
 181 {
 182         return 0;
 183 }
 184
 185 static inline void __exit emif_debugfs_exit(struct emif_data *emif)
 186 {
 187 }
 188 #endif
 189
 190 /*
 191  * Calculate the period of DDR clock from frequency value
 192  */
 193 static void set_ddr_clk_period(u32 freq)
 194 {
 195         /* Divide 10^12 by frequency to get period in ps */
 196         t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
 197 }
 198
 199 /*
 200  * Get bus width used by EMIF. Note that this may be different from the
 201  * bus width of the DDR devices used. For instance two 16-bit DDR devices
 202  * may be connected to a given CS of EMIF. In this case bus width as far
 203  * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
 204  */
 205 static u32 get_emif_bus_width(struct emif_data *emif)
 206 {
 207         u32             width;
 208         void __iomem    *base = emif->base;
 209
 210         width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
 211                         >> NARROW_MODE_SHIFT;
 212         width = width == 0 ? 32 : 16;
 213
 214         return width;
 215 }
 216
 217 /*
 218  * Get the CL from SDRAM_CONFIG register
 219  */
 220 static u32 get_cl(struct emif_data *emif)
 221 {
 222         u32             cl;
 223         void __iomem    *base = emif->base;
 224
 225         cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
 226
 227         return cl;
 228 }
 229
 230 static void set_lpmode(struct emif_data *emif, u8 lpmode)
 231 {
 232         u32 temp;
 233         void __iomem *base = emif->base;
 234
 235         /*
 236          * Workaround for errata i743 - LPDDR2 Power-Down State is Not
 237          * Efficient
 238          *
 239          * i743 DESCRIPTION:
 240          * The EMIF supports power-down state for low power. The EMIF
 241          * automatically puts the SDRAM into power-down after the memory is
 242          * not accessed for a defined number of cycles and the
 243          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
 244          * As the EMIF supports automatic output impedance calibration, a ZQ
 245          * calibration long command is issued every time it exits active
 246          * power-down and precharge power-down modes. The EMIF waits and
 247          * blocks any other command during this calibration.
 248          * The EMIF does not allow selective disabling of ZQ calibration upon
 249          * exit of power-down mode. Due to very short periods of power-down
 250          * cycles, ZQ calibration overhead creates bandwidth issues and
 251          * increases overall system power consumption. On the other hand,
 252          * issuing ZQ calibration long commands when exiting self-refresh is
 253          * still required.
 254          *
 255          * WORKAROUND
 256          * Because there is no power consumption benefit of the power-down due
 257          * to the calibration and there is a performance risk, the guideline
 258          * is to not allow power-down state and, therefore, to not have set
 259          * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
 260          */
 261         if ((emif->plat_data->ip_rev == EMIF_4D) &&
 262             (EMIF_LP_MODE_PWR_DN == lpmode)) {
 263                 WARN_ONCE(1,
 264                           "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by"
 265                           "erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
 266                 /* rollback LP_MODE to Self-refresh mode */
 267                 lpmode = EMIF_LP_MODE_SELF_REFRESH;
 268         }
 269
 270         temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
 271         temp &= ~LP_MODE_MASK;
 272         temp |= (lpmode << LP_MODE_SHIFT);
 273         writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
 274 }
 275
 276 static void do_freq_update(void)
 277 {
 278         struct emif_data *emif;
 279
 280         /*
 281          * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
 282          *
 283          * i728 DESCRIPTION:
 284          * The EMIF automatically puts the SDRAM into self-refresh mode
 285          * after the EMIF has not performed accesses during
 286          * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
 287          * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
 288          * to 0x2. If during a small window the following three events
 289          * occur:
 290          * - The SR_TIMING counter expires
 291          * - And frequency change is requested
 292          * - And OCP access is requested
 293          * Then it causes instable clock on the DDR interface.
 294          *
 295          * WORKAROUND
 296          * To avoid the occurrence of the three events, the workaround
 297          * is to disable the self-refresh when requesting a frequency
 298          * change. Before requesting a frequency change the software must
 299          * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
 300          * frequency change has been done, the software can reprogram
 301          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
 302          */
 303         list_for_each_entry(emif, &device_list, node) {
 304                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 305                         set_lpmode(emif, EMIF_LP_MODE_DISABLE);
 306         }
 307
 308         /*
 309          * TODO: Do FREQ_UPDATE here when an API
 310          * is available for this as part of the new
 311          * clock framework
 312          */
 313
 314         list_for_each_entry(emif, &device_list, node) {
 315                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 316                         set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
 317         }
 318 }
 319
 320 /* Find addressing table entry based on the device's type and density */
 321 static const struct lpddr2_addressing *get_addressing_table(
 322         const struct ddr_device_info *device_info)
 323 {
 324         u32             index, type, density;
 325
 326         type = device_info->type;
 327         density = device_info->density;
 328
 329         switch (type) {
 330         case DDR_TYPE_LPDDR2_S4:
 331                 index = density - 1;
 332                 break;
 333         case DDR_TYPE_LPDDR2_S2:
 334                 switch (density) {
 335                 case DDR_DENSITY_1Gb:
 336                 case DDR_DENSITY_2Gb:
 337                         index = density + 3;
 338                         break;
 339                 default:
 340                         index = density - 1;
 341                 }
 342                 break;
 343         default:
 344                 return NULL;
 345         }
 346
 347         return &lpddr2_jedec_addressing_table[index];
 348 }
 349
 350 /*
 351  * Find the the right timing table from the array of timing
 352  * tables of the device using DDR clock frequency
 353  */
 354 static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
 355                 u32 freq)
 356 {
 357         u32                             i, min, max, freq_nearest;
 358         const struct lpddr2_timings     *timings = NULL;
 359         const struct lpddr2_timings     *timings_arr = emif->plat_data->timings;
 360         struct                          device *dev = emif->dev;
 361
 362         /* Start with a very high frequency - 1GHz */
 363         freq_nearest = 1000000000;
 364
 365         /*
 366          * Find the timings table such that:
 367          *  1. the frequency range covers the required frequency(safe) AND
 368          *  2. the max_freq is closest to the required frequency(optimal)
 369          */
 370         for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
 371                 max = timings_arr[i].max_freq;
 372                 min = timings_arr[i].min_freq;
 373                 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
 374                         freq_nearest = max;
 375                         timings = &timings_arr[i];
 376                 }
 377         }
 378
 379         if (!timings)
 380                 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
 381                         __func__, freq);
 382
 383         dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
 384                 __func__, freq, freq_nearest);
 385
 386         return timings;
 387 }
 388
 389 static u32 get_sdram_ref_ctrl_shdw(u32 freq,
 390                 const struct lpddr2_addressing *addressing)
 391 {
 392         u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
 393
 394         /* Scale down frequency and t_refi to avoid overflow */
 395         freq_khz = freq / 1000;
 396         t_refi = addressing->tREFI_ns / 100;
 397
 398         /*
 399          * refresh rate to be set is 'tREFI(in us) * freq in MHz
 400          * division by 10000 to account for change in units
 401          */
 402         val = t_refi * freq_khz / 10000;
 403         ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
 404
 405         return ref_ctrl_shdw;
 406 }
 407
 408 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
 409                 const struct lpddr2_min_tck *min_tck,
 410                 const struct lpddr2_addressing *addressing)
 411 {
 412         u32 tim1 = 0, val = 0;
 413
 414         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 415         tim1 |= val << T_WTR_SHIFT;
 416
 417         if (addressing->num_banks == B8)
 418                 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
 419         else
 420                 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
 421         tim1 |= (val - 1) << T_RRD_SHIFT;
 422
 423         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
 424         tim1 |= val << T_RC_SHIFT;
 425
 426         val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
 427         tim1 |= (val - 1) << T_RAS_SHIFT;
 428
 429         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 430         tim1 |= val << T_WR_SHIFT;
 431
 432         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
 433         tim1 |= val << T_RCD_SHIFT;
 434
 435         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
 436         tim1 |= val << T_RP_SHIFT;
 437
 438         return tim1;
 439 }
 440
 441 static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
 442                 const struct lpddr2_min_tck *min_tck,
 443                 const struct lpddr2_addressing *addressing)
 444 {
 445         u32 tim1 = 0, val = 0;
 446
 447         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 448         tim1 = val << T_WTR_SHIFT;
 449
 450         /*
 451          * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
 452          * to tFAW for de-rating
 453          */
 454         if (addressing->num_banks == B8) {
 455                 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
 456         } else {
 457                 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
 458                 val = max(min_tck->tRRD, val) - 1;
 459         }
 460         tim1 |= val << T_RRD_SHIFT;
 461
 462         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
 463         tim1 |= (val - 1) << T_RC_SHIFT;
 464
 465         val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
 466         val = max(min_tck->tRASmin, val) - 1;
 467         tim1 |= val << T_RAS_SHIFT;
 468
 469         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 470         tim1 |= val << T_WR_SHIFT;
 471
 472         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
 473         tim1 |= (val - 1) << T_RCD_SHIFT;
 474
 475         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
 476         tim1 |= (val - 1) << T_RP_SHIFT;
 477
 478         return tim1;
 479 }
 480
 481 static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
 482                 const struct lpddr2_min_tck *min_tck,
 483                 const struct lpddr2_addressing *addressing,
 484                 u32 type)
 485 {
 486         u32 tim2 = 0, val = 0;
 487
 488         val = min_tck->tCKE - 1;
 489         tim2 |= val << T_CKE_SHIFT;
 490
 491         val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
 492         tim2 |= val << T_RTP_SHIFT;
 493
 494         /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
 495         val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
 496         tim2 |= val << T_XSNR_SHIFT;
 497
 498         /* XSRD same as XSNR for LPDDR2 */
 499         tim2 |= val << T_XSRD_SHIFT;
 500
 501         val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
 502         tim2 |= val << T_XP_SHIFT;
 503
 504         return tim2;
 505 }
 506
 507 static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 508                 const struct lpddr2_min_tck *min_tck,
 509                 const struct lpddr2_addressing *addressing,
 510                 u32 type, u32 ip_rev, u32 derated)
 511 {
 512         u32 tim3 = 0, val = 0, t_dqsck;
 513
 514         val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
 515         val = val > 0xF ? 0xF : val;
 516         tim3 |= val << T_RAS_MAX_SHIFT;
 517
 518         val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
 519         tim3 |= val << T_RFC_SHIFT;
 520
 521         t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
 522                 timings->tDQSCK_max_derated : timings->tDQSCK_max;
 523         if (ip_rev == EMIF_4D5)
 524                 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
 525         else
 526                 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
 527
 528         tim3 |= val << T_TDQSCKMAX_SHIFT;
 529
 530         val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
 531         tim3 |= val << ZQ_ZQCS_SHIFT;
 532
 533         val = DIV_ROUND_UP(timings->tCKESR, t_ck);
 534         val = max(min_tck->tCKESR, val) - 1;
 535         tim3 |= val << T_CKESR_SHIFT;
 536
 537         if (ip_rev == EMIF_4D5) {
 538                 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
 539
 540                 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
 541                 tim3 |= val << T_PDLL_UL_SHIFT;
 542         }
 543
 544         return tim3;
 545 }
 546
 547 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
 548                 bool cs1_used, bool cal_resistors_per_cs)
 549 {
 550         u32 zq = 0, val = 0;
 551
 552         val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
 553         zq |= val << ZQ_REFINTERVAL_SHIFT;
 554
 555         val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
 556         zq |= val << ZQ_ZQCL_MULT_SHIFT;
 557
 558         val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
 559         zq |= val << ZQ_ZQINIT_MULT_SHIFT;
 560
 561         zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
 562
 563         if (cal_resistors_per_cs)
 564                 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
 565         else
 566                 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
 567
 568         zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
 569
 570         val = cs1_used ? 1 : 0;
 571         zq |= val << ZQ_CS1EN_SHIFT;
 572
 573         return zq;
 574 }
 575
 576 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
 577                 const struct emif_custom_configs *custom_configs, bool cs1_used,
 578                 u32 sdram_io_width, u32 emif_bus_width)
 579 {
 580         u32 alert = 0, interval, devcnt;
 581
 582         if (custom_configs && (custom_configs->mask &
 583                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
 584                 interval = custom_configs->temp_alert_poll_interval_ms;
 585         else
 586                 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
 587
 588         interval *= 1000000;                    /* Convert to ns */
 589         interval /= addressing->tREFI_ns;       /* Convert to refresh cycles */
 590         alert |= (interval << TA_REFINTERVAL_SHIFT);
 591
 592         /*
 593          * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
 594          * also to this form and subtract to get TA_DEVCNT, which is
 595          * in log2(x) form.
 596          */
 597         emif_bus_width = __fls(emif_bus_width) - 1;
 598         devcnt = emif_bus_width - sdram_io_width;
 599         alert |= devcnt << TA_DEVCNT_SHIFT;
 600
 601         /* DEVWDT is in 'log2(x) - 3' form */
 602         alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
 603
 604         alert |= 1 << TA_SFEXITEN_SHIFT;
 605         alert |= 1 << TA_CS0EN_SHIFT;
 606         alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
 607
 608         return alert;
 609 }
 610
 611 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 612 {
 613         u32 idle = 0, val = 0;
 614
 615         /*
 616          * Maximum value in normal conditions and increased frequency
 617          * when voltage is ramping
 618          */
 619         if (volt_ramp)
 620                 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
 621         else
 622                 val = 0x1FF;
 623
 624         /*
 625          * READ_IDLE_CTRL register in EMIF4D has same offset and fields
 626          * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
 627          */
 628         idle |= val << DLL_CALIB_INTERVAL_SHIFT;
 629         idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
 630
 631         return idle;
 632 }
 633
 634 static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
 635 {
 636         u32 calib = 0, val = 0;
 637
 638         if (volt_ramp == DDR_VOLTAGE_RAMPING)
 639                 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
 640         else
 641                 val = 0; /* Disabled when voltage is stable */
 642
 643         calib |= val << DLL_CALIB_INTERVAL_SHIFT;
 644         calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
 645
 646         return calib;
 647 }
 648
 649 static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
 650         u32 freq, u8 RL)
 651 {
 652         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
 653
 654         val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
 655         phy |= val << READ_LATENCY_SHIFT_4D;
 656
 657         if (freq <= 100000000)
 658                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
 659         else if (freq <= 200000000)
 660                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
 661         else
 662                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
 663
 664         phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
 665
 666         return phy;
 667 }
 668
 669 static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
 670 {
 671         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
 672
 673         /*
 674          * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
 675          * half-delay is not needed else set half-delay
 676          */
 677         if (freq >= 265000000 && freq < 267000000)
 678                 half_delay = 0;
 679         else
 680                 half_delay = 1;
 681
 682         phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
 683         phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
 684                         t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
 685
 686         return phy;
 687 }
 688
 689 static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
 690 {
 691         u32 fifo_we_slave_ratio;
 692
 693         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 694                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 695
 696         return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
 697                 fifo_we_slave_ratio << 22;
 698 }
 699
 700 static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
 701 {
 702         u32 fifo_we_slave_ratio;
 703
 704         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 705                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 706
 707         return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
 708                 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
 709 }
 710
 711 static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
 712 {
 713         u32 fifo_we_slave_ratio;
 714
 715         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 716                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 717
 718         return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
 719                 fifo_we_slave_ratio << 13;
 720 }
 721
 722 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 723 {
 724         u32 pwr_mgmt_ctrl       = 0, timeout;
 725         u32 lpmode              = EMIF_LP_MODE_SELF_REFRESH;
 726         u32 timeout_perf        = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
 727         u32 timeout_pwr         = EMIF_LP_MODE_TIMEOUT_POWER;
 728         u32 freq_threshold      = EMIF_LP_MODE_FREQ_THRESHOLD;
 729         u32 mask;
 730         u8 shift;
 731
 732         struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
 733
 734         if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
 735                 lpmode          = cust_cfgs->lpmode;
 736                 timeout_perf    = cust_cfgs->lpmode_timeout_performance;
 737                 timeout_pwr     = cust_cfgs->lpmode_timeout_power;
 738                 freq_threshold  = cust_cfgs->lpmode_freq_threshold;
 739         }
 740
 741         /* Timeout based on DDR frequency */
 742         timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
 743
 744         /*
 745          * The value to be set in register is "log2(timeout) - 3"
 746          * if timeout < 16 load 0 in register
 747          * if timeout is not a power of 2, round to next highest power of 2
 748          */
 749         if (timeout < 16) {
 750                 timeout = 0;
 751         } else {
 752                 if (timeout & (timeout - 1))
 753                         timeout <<= 1;
 754                 timeout = __fls(timeout) - 3;
 755         }
 756
 757         switch (lpmode) {
 758         case EMIF_LP_MODE_CLOCK_STOP:
 759                 shift = CS_TIM_SHIFT;
 760                 mask = CS_TIM_MASK;
 761                 break;
 762         case EMIF_LP_MODE_SELF_REFRESH:
 763                 /* Workaround for errata i735 */
 764                 if (timeout < 6)
 765                         timeout = 6;
 766
 767                 shift = SR_TIM_SHIFT;
 768                 mask = SR_TIM_MASK;
 769                 break;
 770         case EMIF_LP_MODE_PWR_DN:
 771                 shift = PD_TIM_SHIFT;
 772                 mask = PD_TIM_MASK;
 773                 break;
 774         case EMIF_LP_MODE_DISABLE:
 775         default:
 776                 mask = 0;
 777                 shift = 0;
 778                 break;
 779         }
 780         /* Round to maximum in case of overflow, BUT warn! */
 781         if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
 782                 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
 783                        lpmode,
 784                        timeout_perf,
 785                        timeout_pwr,
 786                        freq_threshold);
 787                 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
 788                      timeout, mask >> shift);
 789                 timeout = mask >> shift;
 790         }
 791
 792         /* Setup required timing */
 793         pwr_mgmt_ctrl = (timeout << shift) & mask;
 794         /* setup a default mask for rest of the modes */
 795         pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
 796                           ~mask;
 797
 798         /* No CS_TIM in EMIF_4D5 */
 799         if (ip_rev == EMIF_4D5)
 800                 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
 801
 802         pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
 803
 804         return pwr_mgmt_ctrl;
 805 }
 806
 807 /*
 808  * Get the temperature level of the EMIF instance:
 809  * Reads the MR4 register of attached SDRAM parts to find out the temperature
 810  * level. If there are two parts attached(one on each CS), then the temperature
 811  * level for the EMIF instance is the higher of the two temperatures.
 812  */
 813 static void get_temperature_level(struct emif_data *emif)
 814 {
 815         u32             temp, temperature_level;
 816         void __iomem    *base;
 817
 818         base = emif->base;
 819
 820         /* Read mode register 4 */
 821         writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 822         temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 823         temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
 824                                 MR4_SDRAM_REF_RATE_SHIFT;
 825
 826         if (emif->plat_data->device_info->cs1_used) {
 827                 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 828                 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 829                 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
 830                                 >> MR4_SDRAM_REF_RATE_SHIFT;
 831                 temperature_level = max(temp, temperature_level);
 832         }
 833
 834         /* treat everything less than nominal(3) in MR4 as nominal */
 835         if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
 836                 temperature_level = SDRAM_TEMP_NOMINAL;
 837
 838         /* if we get reserved value in MR4 persist with the existing value */
 839         if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
 840                 emif->temperature_level = temperature_level;
 841 }
 842
 843 /*
 844  * Program EMIF shadow registers that are not dependent on temperature
 845  * or voltage
 846  */
 847 static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
 848 {
 849         void __iomem    *base = emif->base;
 850
 851         writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
 852         writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 853         writel(regs->pwr_mgmt_ctrl_shdw,
 854                base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
 855
 856         /* Settings specific for EMIF4D5 */
 857         if (emif->plat_data->ip_rev != EMIF_4D5)
 858                 return;
 859         writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
 860         writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
 861         writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
 862 }
 863
 864 /*
 865  * When voltage ramps dll calibration and forced read idle should
 866  * happen more often
 867  */
 868 static void setup_volt_sensitive_regs(struct emif_data *emif,
 869                 struct emif_regs *regs, u32 volt_state)
 870 {
 871         u32             calib_ctrl;
 872         void __iomem    *base = emif->base;
 873
 874         /*
 875          * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
 876          * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
 877          * is an alias of the respective read_idle_ctrl_shdw_* (members of
 878          * a union). So, the below code takes care of both cases
 879          */
 880         if (volt_state == DDR_VOLTAGE_RAMPING)
 881                 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
 882         else
 883                 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
 884
 885         writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
 886 }
 887
 888 /*
 889  * setup_temperature_sensitive_regs() - set the timings for temperature
 890  * sensitive registers. This happens once at initialisation time based
 891  * on the temperature at boot time and subsequently based on the temperature
 892  * alert interrupt. Temperature alert can happen when the temperature
 893  * increases or drops. So this function can have the effect of either
 894  * derating the timings or going back to nominal values.
 895  */
 896 static void setup_temperature_sensitive_regs(struct emif_data *emif,
 897                 struct emif_regs *regs)
 898 {
 899         u32             tim1, tim3, ref_ctrl, type;
 900         void __iomem    *base = emif->base;
 901         u32             temperature;
 902
 903         type = emif->plat_data->device_info->type;
 904
 905         tim1 = regs->sdram_tim1_shdw;
 906         tim3 = regs->sdram_tim3_shdw;
 907         ref_ctrl = regs->ref_ctrl_shdw;
 908
 909         /* No de-rating for non-lpddr2 devices */
 910         if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
 911                 goto out;
 912
 913         temperature = emif->temperature_level;
 914         if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 915                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 916         } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
 917                 tim1 = regs->sdram_tim1_shdw_derated;
 918                 tim3 = regs->sdram_tim3_shdw_derated;
 919                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 920         }
 921
 922 out:
 923         writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
 924         writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
 925         writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 926 }
 927
 928 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
 929 {
 930         u32             old_temp_level;
 931         irqreturn_t     ret = IRQ_HANDLED;
 932         struct emif_custom_configs *custom_configs;
 933
 934         spin_lock_irqsave(&emif_lock, irq_state);
 935         old_temp_level = emif->temperature_level;
 936         get_temperature_level(emif);
 937
 938         if (unlikely(emif->temperature_level == old_temp_level)) {
 939                 goto out;
 940         } else if (!emif->curr_regs) {
 941                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 942                 goto out;
 943         }
 944
 945         custom_configs = emif->plat_data->custom_configs;
 946
 947         /*
 948          * IF we detect higher than "nominal rating" from DDR sensor
 949          * on an unsupported DDR part, shutdown system
 950          */
 951         if (custom_configs && !(custom_configs->mask &
 952                                 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
 953                 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 954                         dev_err(emif->dev,
 955                                 "%s:NOT Extended temperature capable memory."
 956                                 "Converting MR4=0x%02x as shutdown event\n",
 957                                 __func__, emif->temperature_level);
 958                         /*
 959                          * Temperature far too high - do kernel_power_off()
 960                          * from thread context
 961                          */
 962                         emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
 963                         ret = IRQ_WAKE_THREAD;
 964                         goto out;
 965                 }
 966         }
 967
 968         if (emif->temperature_level < old_temp_level ||
 969                 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 970                 /*
 971                  * Temperature coming down - defer handling to thread OR
 972                  * Temperature far too high - do kernel_power_off() from
 973                  * thread context
 974                  */
 975                 ret = IRQ_WAKE_THREAD;
 976         } else {
 977                 /* Temperature is going up - handle immediately */
 978                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
 979                 do_freq_update();
 980         }
 981
 982 out:
 983         spin_unlock_irqrestore(&emif_lock, irq_state);
 984         return ret;
 985 }
 986
 987 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
 988 {
 989         u32                     interrupts;
 990         struct emif_data        *emif = dev_id;
 991         void __iomem            *base = emif->base;
 992         struct device           *dev = emif->dev;
 993         irqreturn_t             ret = IRQ_HANDLED;
 994
 995         /* Save the status and clear it */
 996         interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 997         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 998
 999         /*
1000          * Handle temperature alert
1001          * Temperature alert should be same for all ports
1002          * So, it's enough to process it only for one of the ports
1003          */
1004         if (interrupts & TA_SYS_MASK)
1005                 ret = handle_temp_alert(base, emif);
1006
1007         if (interrupts & ERR_SYS_MASK)
1008                 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
1009
1010         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1011                 /* Save the status and clear it */
1012                 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
1013                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
1014
1015                 if (interrupts & ERR_LL_MASK)
1016                         dev_err(dev, "Access error from LL port - %x\n",
1017                                 interrupts);
1018         }
1019
1020         return ret;
1021 }
1022
1023 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
1024 {
1025         struct emif_data        *emif = dev_id;
1026
1027         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
1028                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1029
1030                 /* If we have Power OFF ability, use it, else try restarting */
1031                 if (pm_power_off) {
1032                         kernel_power_off();
1033                 } else {
1034                         WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
1035                         kernel_restart("SDRAM Over-temp Emergency restart");
1036                 }
1037                 return IRQ_HANDLED;
1038         }
1039
1040         spin_lock_irqsave(&emif_lock, irq_state);
1041
1042         if (emif->curr_regs) {
1043                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1044                 do_freq_update();
1045         } else {
1046                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
1047         }
1048
1049         spin_unlock_irqrestore(&emif_lock, irq_state);
1050
1051         return IRQ_HANDLED;
1052 }
1053
1054 static void clear_all_interrupts(struct emif_data *emif)
1055 {
1056         void __iomem    *base = emif->base;
1057
1058         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
1059                 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1060         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1061                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
1062                         base + EMIF_LL_OCP_INTERRUPT_STATUS);
1063 }
1064
1065 static void disable_and_clear_all_interrupts(struct emif_data *emif)
1066 {
1067         void __iomem            *base = emif->base;
1068
1069         /* Disable all interrupts */
1070         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1071                 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1072         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1073                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1074                         base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1075
1076         /* Clear all interrupts */
1077         clear_all_interrupts(emif);
1078 }
1079
1080 static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1081 {
1082         u32             interrupts, type;
1083         void __iomem    *base = emif->base;
1084
1085         type = emif->plat_data->device_info->type;
1086
1087         clear_all_interrupts(emif);
1088
1089         /* Enable interrupts for SYS interface */
1090         interrupts = EN_ERR_SYS_MASK;
1091         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1092                 interrupts |= EN_TA_SYS_MASK;
1093         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1094
1095         /* Enable interrupts for LL interface */
1096         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1097                 /* TA need not be enabled for LL */
1098                 interrupts = EN_ERR_LL_MASK;
1099                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1100         }
1101
1102         /* setup IRQ handlers */
1103         return devm_request_threaded_irq(emif->dev, irq,
1104                                     emif_interrupt_handler,
1105                                     emif_threaded_isr,
1106                                     0, dev_name(emif->dev),
1107                                     emif);
1108
1109 }
1110
1111 static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1112 {
1113         u32                             pwr_mgmt_ctrl, zq, temp_alert_cfg;
1114         void __iomem                    *base = emif->base;
1115         const struct lpddr2_addressing  *addressing;
1116         const struct ddr_device_info    *device_info;
1117
1118         device_info = emif->plat_data->device_info;
1119         addressing = get_addressing_table(device_info);
1120
1121         /*
1122          * Init power management settings
1123          * We don't know the frequency yet. Use a high frequency
1124          * value for a conservative timeout setting
1125          */
1126         pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1127                         emif->plat_data->ip_rev);
1128         emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1129         writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1130
1131         /* Init ZQ calibration settings */
1132         zq = get_zq_config_reg(addressing, device_info->cs1_used,
1133                 device_info->cal_resistors_per_cs);
1134         writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1135
1136         /* Check temperature level temperature level*/
1137         get_temperature_level(emif);
1138         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1139                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1140
1141         /* Init temperature polling */
1142         temp_alert_cfg = get_temp_alert_config(addressing,
1143                 emif->plat_data->custom_configs, device_info->cs1_used,
1144                 device_info->io_width, get_emif_bus_width(emif));
1145         writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1146
1147         /*
1148          * Program external PHY control registers that are not frequency
1149          * dependent
1150          */
1151         if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1152                 return;
1153         writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1154         writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1155         writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1156         writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1157         writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1158         writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1159         writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1160         writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1161         writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1162         writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1163         writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1164         writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1165         writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1166         writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1167         writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1168         writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1169         writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1170         writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1171         writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1172         writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1173         writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1174 }
1175
1176 static void get_default_timings(struct emif_data *emif)
1177 {
1178         struct emif_platform_data *pd = emif->plat_data;
1179
1180         pd->timings             = lpddr2_jedec_timings;
1181         pd->timings_arr_size    = ARRAY_SIZE(lpddr2_jedec_timings);
1182
1183         dev_warn(emif->dev, "%s: using default timings\n", __func__);
1184 }
1185
1186 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1187                 u32 ip_rev, struct device *dev)
1188 {
1189         int valid;
1190
1191         valid = (type == DDR_TYPE_LPDDR2_S4 ||
1192                         type == DDR_TYPE_LPDDR2_S2)
1193                 && (density >= DDR_DENSITY_64Mb
1194                         && density <= DDR_DENSITY_8Gb)
1195                 && (io_width >= DDR_IO_WIDTH_8
1196                         && io_width <= DDR_IO_WIDTH_32);
1197
1198         /* Combinations of EMIF and PHY revisions that we support today */
1199         switch (ip_rev) {
1200         case EMIF_4D:
1201                 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1202                 break;
1203         case EMIF_4D5:
1204                 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1205                 break;
1206         default:
1207                 valid = 0;
1208         }
1209
1210         if (!valid)
1211                 dev_err(dev, "%s: invalid DDR details\n", __func__);
1212         return valid;
1213 }
1214
1215 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1216                 struct device *dev)
1217 {
1218         int valid = 1;
1219
1220         if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1221                 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1222                 valid = cust_cfgs->lpmode_freq_threshold &&
1223                         cust_cfgs->lpmode_timeout_performance &&
1224                         cust_cfgs->lpmode_timeout_power;
1225
1226         if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1227                 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1228
1229         if (!valid)
1230                 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1231
1232         return valid;
1233 }
1234
1235 #if defined(CONFIG_OF)
1236 static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1237                 struct emif_data *emif)
1238 {
1239         struct emif_custom_configs      *cust_cfgs = NULL;
1240         int                             len;
1241         const __be32                    *lpmode, *poll_intvl;
1242
1243         lpmode = of_get_property(np_emif, "low-power-mode", &len);
1244         poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1245
1246         if (lpmode || poll_intvl)
1247                 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1248                         GFP_KERNEL);
1249
1250         if (!cust_cfgs)
1251                 return;
1252
1253         if (lpmode) {
1254                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1255                 cust_cfgs->lpmode = be32_to_cpup(lpmode);
1256                 of_property_read_u32(np_emif,
1257                                 "low-power-mode-timeout-performance",
1258                                 &cust_cfgs->lpmode_timeout_performance);
1259                 of_property_read_u32(np_emif,
1260                                 "low-power-mode-timeout-power",
1261                                 &cust_cfgs->lpmode_timeout_power);
1262                 of_property_read_u32(np_emif,
1263                                 "low-power-mode-freq-threshold",
1264                                 &cust_cfgs->lpmode_freq_threshold);
1265         }
1266
1267         if (poll_intvl) {
1268                 cust_cfgs->mask |=
1269                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1270                 cust_cfgs->temp_alert_poll_interval_ms =
1271                                                 be32_to_cpup(poll_intvl);
1272         }
1273
1274         if (of_find_property(np_emif, "extended-temp-part", &len))
1275                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
1276
1277         if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1278                 devm_kfree(emif->dev, cust_cfgs);
1279                 return;
1280         }
1281
1282         emif->plat_data->custom_configs = cust_cfgs;
1283 }
1284
1285 static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1286                 struct device_node *np_ddr,
1287                 struct ddr_device_info *dev_info)
1288 {
1289         u32 density = 0, io_width = 0;
1290         int len;
1291
1292         if (of_find_property(np_emif, "cs1-used", &len))
1293                 dev_info->cs1_used = true;
1294
1295         if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1296                 dev_info->cal_resistors_per_cs = true;
1297
1298         if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
1299                 dev_info->type = DDR_TYPE_LPDDR2_S4;
1300         else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
1301                 dev_info->type = DDR_TYPE_LPDDR2_S2;
1302
1303         of_property_read_u32(np_ddr, "density", &density);
1304         of_property_read_u32(np_ddr, "io-width", &io_width);
1305
1306         /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1307         if (density & (density - 1))
1308                 dev_info->density = 0;
1309         else
1310                 dev_info->density = __fls(density) - 5;
1311
1312         /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1313         if (io_width & (io_width - 1))
1314                 dev_info->io_width = 0;
1315         else
1316                 dev_info->io_width = __fls(io_width) - 1;
1317 }
1318
1319 static struct emif_data * __init_or_module of_get_memory_device_details(
1320                 struct device_node *np_emif, struct device *dev)
1321 {
1322         struct emif_data                *emif = NULL;
1323         struct ddr_device_info          *dev_info = NULL;
1324         struct emif_platform_data       *pd = NULL;
1325         struct device_node              *np_ddr;
1326         int                             len;
1327
1328         np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1329         if (!np_ddr)
1330                 goto error;
1331         emif    = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1332         pd      = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1333         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1334
1335         if (!emif || !pd || !dev_info) {
1336                 dev_err(dev, "%s: Out of memory!!\n",
1337                         __func__);
1338                 goto error;
1339         }
1340
1341         emif->plat_data         = pd;
1342         pd->device_info         = dev_info;
1343         emif->dev               = dev;
1344         emif->np_ddr            = np_ddr;
1345         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1346
1347         if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1348                 emif->plat_data->ip_rev = EMIF_4D;
1349         else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1350                 emif->plat_data->ip_rev = EMIF_4D5;
1351
1352         of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1353
1354         if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1355                 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1356
1357         of_get_ddr_info(np_emif, np_ddr, dev_info);
1358         if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1359                         pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1360                         emif->dev)) {
1361                 dev_err(dev, "%s: invalid device data!!\n", __func__);
1362                 goto error;
1363         }
1364         /*
1365          * For EMIF instances other than EMIF1 see if the devices connected
1366          * are exactly same as on EMIF1(which is typically the case). If so,
1367          * mark it as a duplicate of EMIF1. This will save some memory and
1368          * computation.
1369          */
1370         if (emif1 && emif1->np_ddr == np_ddr) {
1371                 emif->duplicate = true;
1372                 goto out;
1373         } else if (emif1) {
1374                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1375                         __func__);
1376         }
1377
1378         of_get_custom_configs(np_emif, emif);
1379         emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1380                                         emif->plat_data->device_info->type,
1381                                         &emif->plat_data->timings_arr_size);
1382
1383         emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1384         goto out;
1385
1386 error:
1387         return NULL;
1388 out:
1389         return emif;
1390 }
1391
1392 #else
1393
1394 static struct emif_data * __init_or_module of_get_memory_device_details(
1395                 struct device_node *np_emif, struct device *dev)
1396 {
1397         return NULL;
1398 }
1399 #endif
1400
1401 static struct emif_data *__init_or_module get_device_details(
1402                 struct platform_device *pdev)
1403 {
1404         u32                             size;
1405         struct emif_data                *emif = NULL;
1406         struct ddr_device_info          *dev_info;
1407         struct emif_custom_configs      *cust_cfgs;
1408         struct emif_platform_data       *pd;
1409         struct device                   *dev;
1410         void                            *temp;
1411
1412         pd = pdev->dev.platform_data;
1413         dev = &pdev->dev;
1414
1415         if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1416                         pd->device_info->density, pd->device_info->io_width,
1417                         pd->phy_type, pd->ip_rev, dev))) {
1418                 dev_err(dev, "%s: invalid device data\n", __func__);
1419                 goto error;
1420         }
1421
1422         emif    = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1423         temp    = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1424         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1425
1426         if (!emif || !temp || !dev_info) {
1427                 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1428                 goto error;
1429         }
1430
1431         memcpy(temp, pd, sizeof(*pd));
1432         pd = temp;
1433         memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1434
1435         pd->device_info         = dev_info;
1436         emif->plat_data         = pd;
1437         emif->dev               = dev;
1438         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1439
1440         /*
1441          * For EMIF instances other than EMIF1 see if the devices connected
1442          * are exactly same as on EMIF1(which is typically the case). If so,
1443          * mark it as a duplicate of EMIF1 and skip copying timings data.
1444          * This will save some memory and some computation later.
1445          */
1446         emif->duplicate = emif1 && (memcmp(dev_info,
1447                 emif1->plat_data->device_info,
1448                 sizeof(struct ddr_device_info)) == 0);
1449
1450         if (emif->duplicate) {
1451                 pd->timings = NULL;
1452                 pd->min_tck = NULL;
1453                 goto out;
1454         } else if (emif1) {
1455                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1456                         __func__);
1457         }
1458
1459         /*
1460          * Copy custom configs - ignore allocation error, if any, as
1461          * custom_configs is not very critical
1462          */
1463         cust_cfgs = pd->custom_configs;
1464         if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1465                 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1466                 if (temp)
1467                         memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1468                 else
1469                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1470                                 __LINE__);
1471                 pd->custom_configs = temp;
1472         }
1473
1474         /*
1475          * Copy timings and min-tck values from platform data. If it is not
1476          * available or if memory allocation fails, use JEDEC defaults
1477          */
1478         size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1479         if (pd->timings) {
1480                 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1481                 if (temp) {
1482                         memcpy(temp, pd->timings, size);
1483                         pd->timings = temp;
1484                 } else {
1485                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1486                                 __LINE__);
1487                         get_default_timings(emif);
1488                 }
1489         } else {
1490                 get_default_timings(emif);
1491         }
1492
1493         if (pd->min_tck) {
1494                 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1495                 if (temp) {
1496                         memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1497                         pd->min_tck = temp;
1498                 } else {
1499                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1500                                 __LINE__);
1501                         pd->min_tck = &lpddr2_jedec_min_tck;
1502                 }
1503         } else {
1504                 pd->min_tck = &lpddr2_jedec_min_tck;
1505         }
1506
1507 out:
1508         return emif;
1509
1510 error:
1511         return NULL;
1512 }
1513
1514 static int __init_or_module emif_probe(struct platform_device *pdev)
1515 {
1516         struct emif_data        *emif;
1517         struct resource         *res;
1518         int                     irq, ret;
1519
1520         if (pdev->dev.of_node)
1521                 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1522         else
1523                 emif = get_device_details(pdev);
1524
1525         if (!emif) {
1526                 pr_err("%s: error getting device data\n", __func__);
1527                 goto error;
1528         }
1529
1530         list_add(&emif->node, &device_list);
1531         emif->addressing = get_addressing_table(emif->plat_data->device_info);
1532
1533         /* Save pointers to each other in emif and device structures */
1534         emif->dev = &pdev->dev;
1535         platform_set_drvdata(pdev, emif);
1536
1537         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1538         emif->base = devm_ioremap_resource(emif->dev, res);
1539         if (IS_ERR(emif->base))
1540                 goto error;
1541
1542         irq = platform_get_irq(pdev, 0);
1543         if (irq < 0) {
1544                 dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
1545                         __func__, irq);
1546                 goto error;
1547         }
1548
1549         emif_onetime_settings(emif);
1550         emif_debugfs_init(emif);
1551         disable_and_clear_all_interrupts(emif);
1552         ret = setup_interrupts(emif, irq);
1553         if (ret)
1554                 goto error;
1555
1556         /* One-time actions taken on probing the first device */
1557         if (!emif1) {
1558                 emif1 = emif;
1559                 spin_lock_init(&emif_lock);
1560
1561                 /*
1562                  * TODO: register notifiers for frequency and voltage
1563                  * change here once the respective frameworks are
1564                  * available
1565                  */
1566         }
1567
1568         dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1569                 __func__, emif->base, irq);
1570
1571         return 0;
1572 error:
1573         return -ENODEV;
1574 }
1575
1576 static int __exit emif_remove(struct platform_device *pdev)
1577 {
1578         struct emif_data *emif = platform_get_drvdata(pdev);
1579
1580         emif_debugfs_exit(emif);
1581
1582         return 0;
1583 }
1584
1585 static void emif_shutdown(struct platform_device *pdev)
1586 {
1587         struct emif_data        *emif = platform_get_drvdata(pdev);
1588
1589         disable_and_clear_all_interrupts(emif);
1590 }
1591
1592 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1593                 struct emif_regs *regs)
1594 {
1595         u32                             cs1_used, ip_rev, phy_type;
1596         u32                             cl, type;
1597         const struct lpddr2_timings     *timings;
1598         const struct lpddr2_min_tck     *min_tck;
1599         const struct ddr_device_info    *device_info;
1600         const struct lpddr2_addressing  *addressing;
1601         struct emif_data                *emif_for_calc;
1602         struct device                   *dev;
1603         const struct emif_custom_configs *custom_configs;
1604
1605         dev = emif->dev;
1606         /*
1607          * If the devices on this EMIF instance is duplicate of EMIF1,
1608          * use EMIF1 details for the calculation
1609          */
1610         emif_for_calc   = emif->duplicate ? emif1 : emif;
1611         timings         = get_timings_table(emif_for_calc, freq);
1612         addressing      = emif_for_calc->addressing;
1613         if (!timings || !addressing) {
1614                 dev_err(dev, "%s: not enough data available for %dHz",
1615                         __func__, freq);
1616                 return -1;
1617         }
1618
1619         device_info     = emif_for_calc->plat_data->device_info;
1620         type            = device_info->type;
1621         cs1_used        = device_info->cs1_used;
1622         ip_rev          = emif_for_calc->plat_data->ip_rev;
1623         phy_type        = emif_for_calc->plat_data->phy_type;
1624
1625         min_tck         = emif_for_calc->plat_data->min_tck;
1626         custom_configs  = emif_for_calc->plat_data->custom_configs;
1627
1628         set_ddr_clk_period(freq);
1629
1630         regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1631         regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1632                         addressing);
1633         regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1634                         addressing, type);
1635         regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1636                 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1637
1638         cl = get_cl(emif);
1639
1640         if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1641                 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1642                         timings, freq, cl);
1643         } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1644                 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1645                 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1646                 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1647                 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1648         } else {
1649                 return -1;
1650         }
1651
1652         /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1653         regs->pwr_mgmt_ctrl_shdw =
1654                 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1655                 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1656
1657         if (ip_rev & EMIF_4D) {
1658                 regs->read_idle_ctrl_shdw_normal =
1659                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1660
1661                 regs->read_idle_ctrl_shdw_volt_ramp =
1662                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1663         } else if (ip_rev & EMIF_4D5) {
1664                 regs->dll_calib_ctrl_shdw_normal =
1665                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1666
1667                 regs->dll_calib_ctrl_shdw_volt_ramp =
1668                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1669         }
1670
1671         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1672                 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1673                         addressing);
1674
1675                 regs->sdram_tim1_shdw_derated =
1676                         get_sdram_tim_1_shdw_derated(timings, min_tck,
1677                                 addressing);
1678
1679                 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1680                         min_tck, addressing, type, ip_rev,
1681                         EMIF_DERATED_TIMINGS);
1682         }
1683
1684         regs->freq = freq;
1685
1686         return 0;
1687 }
1688
1689 /*
1690  * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1691  * given frequency(freq):
1692  *
1693  * As an optimisation, every EMIF instance other than EMIF1 shares the
1694  * register cache with EMIF1 if the devices connected on this instance
1695  * are same as that on EMIF1(indicated by the duplicate flag)
1696  *
1697  * If we do not have an entry corresponding to the frequency given, we
1698  * allocate a new entry and calculate the values
1699  *
1700  * Upon finding the right reg dump, save it in curr_regs. It can be
1701  * directly used for thermal de-rating and voltage ramping changes.
1702  */
1703 static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1704 {
1705         int                     i;
1706         struct emif_regs        **regs_cache;
1707         struct emif_regs        *regs = NULL;
1708         struct device           *dev;
1709
1710         dev = emif->dev;
1711         if (emif->curr_regs && emif->curr_regs->freq == freq) {
1712                 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1713                 return emif->curr_regs;
1714         }
1715
1716         if (emif->duplicate)
1717                 regs_cache = emif1->regs_cache;
1718         else
1719                 regs_cache = emif->regs_cache;
1720
1721         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1722                 if (regs_cache[i]->freq == freq) {
1723                         regs = regs_cache[i];
1724                         dev_dbg(dev,
1725                                 "%s: reg dump found in reg cache for %u Hz\n",
1726                                 __func__, freq);
1727                         break;
1728                 }
1729         }
1730
1731         /*
1732          * If we don't have an entry for this frequency in the cache create one
1733          * and calculate the values
1734          */
1735         if (!regs) {
1736                 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1737                 if (!regs)
1738                         return NULL;
1739
1740                 if (get_emif_reg_values(emif, freq, regs)) {
1741                         devm_kfree(emif->dev, regs);
1742                         return NULL;
1743                 }
1744
1745                 /*
1746                  * Now look for an un-used entry in the cache and save the
1747                  * newly created struct. If there are no free entries
1748                  * over-write the last entry
1749                  */
1750                 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1751                         ;
1752
1753                 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1754                         dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1755                                 __func__);
1756                         i = EMIF_MAX_NUM_FREQUENCIES - 1;
1757                         devm_kfree(emif->dev, regs_cache[i]);
1758                 }
1759                 regs_cache[i] = regs;
1760         }
1761
1762         return regs;
1763 }
1764
1765 static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1766 {
1767         dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1768                 volt_state);
1769
1770         if (!emif->curr_regs) {
1771                 dev_err(emif->dev,
1772                         "%s: volt-notify before registers are ready: %d\n",
1773                         __func__, volt_state);
1774                 return;
1775         }
1776
1777         setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1778 }
1779
1780 /*
1781  * TODO: voltage notify handling should be hooked up to
1782  * regulator framework as soon as the necessary support
1783  * is available in mainline kernel. This function is un-used
1784  * right now.
1785  */
1786 static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1787 {
1788         struct emif_data *emif;
1789
1790         spin_lock_irqsave(&emif_lock, irq_state);
1791
1792         list_for_each_entry(emif, &device_list, node)
1793                 do_volt_notify_handling(emif, volt_state);
1794         do_freq_update();
1795
1796         spin_unlock_irqrestore(&emif_lock, irq_state);
1797 }
1798
1799 static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1800 {
1801         struct emif_regs *regs;
1802
1803         regs = get_regs(emif, new_freq);
1804         if (!regs)
1805                 return;
1806
1807         emif->curr_regs = regs;
1808
1809         /*
1810          * Update the shadow registers:
1811          * Temperature and voltage-ramp sensitive settings are also configured
1812          * in terms of DDR cycles. So, we need to update them too when there
1813          * is a freq change
1814          */
1815         dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1816                 __func__, new_freq);
1817         setup_registers(emif, regs);
1818         setup_temperature_sensitive_regs(emif, regs);
1819         setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1820
1821         /*
1822          * Part of workaround for errata i728. See do_freq_update()
1823          * for more details
1824          */
1825         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1826                 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1827 }
1828
1829 /*
1830  * TODO: frequency notify handling should be hooked up to
1831  * clock framework as soon as the necessary support is
1832  * available in mainline kernel. This function is un-used
1833  * right now.
1834  */
1835 static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1836 {
1837         struct emif_data *emif;
1838
1839         /*
1840          * NOTE: we are taking the spin-lock here and releases it
1841          * only in post-notifier. This doesn't look good and
1842          * Sparse complains about it, but this seems to be
1843          * un-avoidable. We need to lock a sequence of events
1844          * that is split between EMIF and clock framework.
1845          *
1846          * 1. EMIF driver updates EMIF timings in shadow registers in the
1847          *    frequency pre-notify callback from clock framework
1848          * 2. clock framework sets up the registers for the new frequency
1849          * 3. clock framework initiates a hw-sequence that updates
1850          *    the frequency EMIF timings synchronously.
1851          *
1852          * All these 3 steps should be performed as an atomic operation
1853          * vis-a-vis similar sequence in the EMIF interrupt handler
1854          * for temperature events. Otherwise, there could be race
1855          * conditions that could result in incorrect EMIF timings for
1856          * a given frequency
1857          */
1858         spin_lock_irqsave(&emif_lock, irq_state);
1859
1860         list_for_each_entry(emif, &device_list, node)
1861                 do_freq_pre_notify_handling(emif, new_freq);
1862 }
1863
1864 static void do_freq_post_notify_handling(struct emif_data *emif)
1865 {
1866         /*
1867          * Part of workaround for errata i728. See do_freq_update()
1868          * for more details
1869          */
1870         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1871                 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1872 }
1873
1874 /*
1875  * TODO: frequency notify handling should be hooked up to
1876  * clock framework as soon as the necessary support is
1877  * available in mainline kernel. This function is un-used
1878  * right now.
1879  */
1880 static void __attribute__((unused)) freq_post_notify_handling(void)
1881 {
1882         struct emif_data *emif;
1883
1884         list_for_each_entry(emif, &device_list, node)
1885                 do_freq_post_notify_handling(emif);
1886
1887         /*
1888          * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1889          * for more details
1890          */
1891         spin_unlock_irqrestore(&emif_lock, irq_state);
1892 }
1893
1894 #if defined(CONFIG_OF)
1895 static const struct of_device_id emif_of_match[] = {
1896                 { .compatible = "ti,emif-4d" },
1897                 { .compatible = "ti,emif-4d5" },
1898                 {},
1899 };
1900 MODULE_DEVICE_TABLE(of, emif_of_match);
1901 #endif
1902
1903 static struct platform_driver emif_driver = {
1904         .remove         = __exit_p(emif_remove),
1905         .shutdown       = emif_shutdown,
1906         .driver = {
1907                 .name = "emif",
1908                 .of_match_table = of_match_ptr(emif_of_match),
1909         },
1910 };
1911
1912 module_platform_driver_probe(emif_driver, emif_probe);
1913
1914 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1915 MODULE_LICENSE("GPL");
1916 MODULE_ALIAS("platform:emif");
1917 MODULE_AUTHOR("Texas Instruments Inc");