drivers/media/usb/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include <media/tuner.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41 #include "pvrusb2-cx2584x-v4l.h"
  42 #include "pvrusb2-cs53l32a.h"
  43 #include "pvrusb2-audio.h"
  44
  45 #define TV_MIN_FREQ     55250000L
  46 #define TV_MAX_FREQ    850000000L
  47
  48 /* This defines a minimum interval that the decoder must remain quiet
  49    before we are allowed to start it running. */
  50 #define TIME_MSEC_DECODER_WAIT 50
  51
  52 /* This defines a minimum interval that the decoder must be allowed to run
  53    before we can safely begin using its streaming output. */
  54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  55
  56 /* This defines a minimum interval that the encoder must remain quiet
  57    before we are allowed to configure it. */
  58 #define TIME_MSEC_ENCODER_WAIT 50
  59
  60 /* This defines the minimum interval that the encoder must successfully run
  61    before we consider that the encoder has run at least once since its
  62    firmware has been loaded.  This measurement is in important for cases
  63    where we can't do something until we know that the encoder has been run
  64    at least once. */
  65 #define TIME_MSEC_ENCODER_OK 250
  66
  67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  68 static DEFINE_MUTEX(pvr2_unit_mtx);
  69
  70 static int ctlchg;
  71 static int procreload;
  72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  75 static int init_pause_msec;
  76
  77 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  81 module_param(procreload, int, S_IRUGO|S_IWUSR);
  82 MODULE_PARM_DESC(procreload,
  83                  "Attempt init failure recovery with firmware reload");
  84 module_param_array(tuner,    int, NULL, 0444);
  85 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  86 module_param_array(video_std,    int, NULL, 0444);
  87 MODULE_PARM_DESC(video_std,"specify initial video standard");
  88 module_param_array(tolerance,    int, NULL, 0444);
  89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  90
  91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  92 static int default_tv_freq    = 61250000L;
  93 /* 104.3 MHz, a usable FM station for my area */
  94 static int default_radio_freq = 104300000L;
  95
  96 module_param_named(tv_freq, default_tv_freq, int, 0444);
  97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  98 module_param_named(radio_freq, default_radio_freq, int, 0444);
  99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
 100
 101 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 102 #define PVR2_CTL_READ_ENDPOINT   0x81
 103
 104 #define PVR2_GPIO_IN 0x9008
 105 #define PVR2_GPIO_OUT 0x900c
 106 #define PVR2_GPIO_DIR 0x9020
 107
 108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 109
 110 #define PVR2_FIRMWARE_ENDPOINT   0x02
 111
 112 /* size of a firmware chunk */
 113 #define FIRMWARE_CHUNK_SIZE 0x2000
 114
 115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 116                                         struct v4l2_subdev *);
 117
 118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 119         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 120         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 121         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 122         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 123         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 124 };
 125
 126 static const char *module_names[] = {
 127         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 128         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 129         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 130         [PVR2_CLIENT_ID_TUNER] = "tuner",
 131         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 132         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 133         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 134 };
 135
 136
 137 static const unsigned char *module_i2c_addresses[] = {
 138         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 139         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 140         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 141         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 142         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 143         [PVR2_CLIENT_ID_CX25840] = "\x44",
 144         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 145 };
 146
 147
 148 static const char *ir_scheme_names[] = {
 149         [PVR2_IR_SCHEME_NONE] = "none",
 150         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 151         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 152         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 153         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 154 };
 155
 156
 157 /* Define the list of additional controls we'll dynamically construct based
 158    on query of the cx2341x module. */
 159 struct pvr2_mpeg_ids {
 160         const char *strid;
 161         int id;
 162 };
 163 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 164         {
 165                 .strid = "audio_layer",
 166                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 167         },{
 168                 .strid = "audio_bitrate",
 169                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 170         },{
 171                 /* Already using audio_mode elsewhere :-( */
 172                 .strid = "mpeg_audio_mode",
 173                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 174         },{
 175                 .strid = "mpeg_audio_mode_extension",
 176                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 177         },{
 178                 .strid = "audio_emphasis",
 179                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 180         },{
 181                 .strid = "audio_crc",
 182                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 183         },{
 184                 .strid = "video_aspect",
 185                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 186         },{
 187                 .strid = "video_b_frames",
 188                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 189         },{
 190                 .strid = "video_gop_size",
 191                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 192         },{
 193                 .strid = "video_gop_closure",
 194                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 195         },{
 196                 .strid = "video_bitrate_mode",
 197                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 198         },{
 199                 .strid = "video_bitrate",
 200                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 201         },{
 202                 .strid = "video_bitrate_peak",
 203                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 204         },{
 205                 .strid = "video_temporal_decimation",
 206                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 207         },{
 208                 .strid = "stream_type",
 209                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 210         },{
 211                 .strid = "video_spatial_filter_mode",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 213         },{
 214                 .strid = "video_spatial_filter",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 216         },{
 217                 .strid = "video_luma_spatial_filter_type",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 219         },{
 220                 .strid = "video_chroma_spatial_filter_type",
 221                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 222         },{
 223                 .strid = "video_temporal_filter_mode",
 224                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 225         },{
 226                 .strid = "video_temporal_filter",
 227                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 228         },{
 229                 .strid = "video_median_filter_type",
 230                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 231         },{
 232                 .strid = "video_luma_median_filter_top",
 233                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 234         },{
 235                 .strid = "video_luma_median_filter_bottom",
 236                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 237         },{
 238                 .strid = "video_chroma_median_filter_top",
 239                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 240         },{
 241                 .strid = "video_chroma_median_filter_bottom",
 242                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 243         }
 244 };
 245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 246
 247
 248 static const char *control_values_srate[] = {
 249         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 250         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 251         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 252 };
 253
 254
 255
 256 static const char *control_values_input[] = {
 257         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 258         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 259         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 260         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 261         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 262 };
 263
 264
 265 static const char *control_values_audiomode[] = {
 266         [V4L2_TUNER_MODE_MONO]   = "Mono",
 267         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 268         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 269         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 270         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 271 };
 272
 273
 274 static const char *control_values_hsm[] = {
 275         [PVR2_CVAL_HSM_FAIL] = "Fail",
 276         [PVR2_CVAL_HSM_HIGH] = "High",
 277         [PVR2_CVAL_HSM_FULL] = "Full",
 278 };
 279
 280
 281 static const char *pvr2_state_names[] = {
 282         [PVR2_STATE_NONE] =    "none",
 283         [PVR2_STATE_DEAD] =    "dead",
 284         [PVR2_STATE_COLD] =    "cold",
 285         [PVR2_STATE_WARM] =    "warm",
 286         [PVR2_STATE_ERROR] =   "error",
 287         [PVR2_STATE_READY] =   "ready",
 288         [PVR2_STATE_RUN] =     "run",
 289 };
 290
 291
 292 struct pvr2_fx2cmd_descdef {
 293         unsigned char id;
 294         unsigned char *desc;
 295 };
 296
 297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 298         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 299         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 300         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 301         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 302         {FX2CMD_REG_WRITE, "write encoder register"},
 303         {FX2CMD_REG_READ, "read encoder register"},
 304         {FX2CMD_MEMSEL, "encoder memsel"},
 305         {FX2CMD_I2C_WRITE, "i2c write"},
 306         {FX2CMD_I2C_READ, "i2c read"},
 307         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 308         {FX2CMD_STREAMING_ON, "stream on"},
 309         {FX2CMD_STREAMING_OFF, "stream off"},
 310         {FX2CMD_FWPOST1, "fwpost1"},
 311         {FX2CMD_POWER_OFF, "power off"},
 312         {FX2CMD_POWER_ON, "power on"},
 313         {FX2CMD_DEEP_RESET, "deep reset"},
 314         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 315         {FX2CMD_GET_IR_CODE, "get IR code"},
 316         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 317         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 318         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 319         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 320         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 321         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 322         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 323 };
 324
 325
 326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 327 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 328 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 330 static void pvr2_hdw_worker_poll(struct work_struct *work);
 331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 337 static void pvr2_hdw_quiescent_timeout(unsigned long);
 338 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 339 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 340 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 341 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 342 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 343                                 unsigned int timeout,int probe_fl,
 344                                 void *write_data,unsigned int write_len,
 345                                 void *read_data,unsigned int read_len);
 346 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 347 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
 348
 349 static void trace_stbit(const char *name,int val)
 350 {
 351         pvr2_trace(PVR2_TRACE_STBITS,
 352                    "State bit %s <-- %s",
 353                    name,(val ? "true" : "false"));
 354 }
 355
 356 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         struct pvr2_hdw *hdw = cptr->hdw;
 359         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 360                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 361         } else {
 362                 *vp = 0;
 363         }
 364         return 0;
 365 }
 366
 367 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 368 {
 369         struct pvr2_hdw *hdw = cptr->hdw;
 370         unsigned int slotId = hdw->freqProgSlot;
 371         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 372                 hdw->freqTable[slotId-1] = v;
 373                 /* Handle side effects correctly - if we're tuned to this
 374                    slot, then forgot the slot id relation since the stored
 375                    frequency has been changed. */
 376                 if (hdw->freqSelector) {
 377                         if (hdw->freqSlotRadio == slotId) {
 378                                 hdw->freqSlotRadio = 0;
 379                         }
 380                 } else {
 381                         if (hdw->freqSlotTelevision == slotId) {
 382                                 hdw->freqSlotTelevision = 0;
 383                         }
 384                 }
 385         }
 386         return 0;
 387 }
 388
 389 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 390 {
 391         *vp = cptr->hdw->freqProgSlot;
 392         return 0;
 393 }
 394
 395 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 396 {
 397         struct pvr2_hdw *hdw = cptr->hdw;
 398         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 399                 hdw->freqProgSlot = v;
 400         }
 401         return 0;
 402 }
 403
 404 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 405 {
 406         struct pvr2_hdw *hdw = cptr->hdw;
 407         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 408         return 0;
 409 }
 410
 411 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 412 {
 413         unsigned freq = 0;
 414         struct pvr2_hdw *hdw = cptr->hdw;
 415         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 416         if (slotId > 0) {
 417                 freq = hdw->freqTable[slotId-1];
 418                 if (!freq) return 0;
 419                 pvr2_hdw_set_cur_freq(hdw,freq);
 420         }
 421         if (hdw->freqSelector) {
 422                 hdw->freqSlotRadio = slotId;
 423         } else {
 424                 hdw->freqSlotTelevision = slotId;
 425         }
 426         return 0;
 427 }
 428
 429 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 430 {
 431         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 432         return 0;
 433 }
 434
 435 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 436 {
 437         return cptr->hdw->freqDirty != 0;
 438 }
 439
 440 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 441 {
 442         cptr->hdw->freqDirty = 0;
 443 }
 444
 445 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 446 {
 447         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 448         return 0;
 449 }
 450
 451 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 452 {
 453         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 454         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 455         if (stat != 0) {
 456                 return stat;
 457         }
 458         *left = cap->bounds.left;
 459         return 0;
 460 }
 461
 462 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 463 {
 464         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 465         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 466         if (stat != 0) {
 467                 return stat;
 468         }
 469         *left = cap->bounds.left;
 470         if (cap->bounds.width > cptr->hdw->cropw_val) {
 471                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 472         }
 473         return 0;
 474 }
 475
 476 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 477 {
 478         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 479         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 480         if (stat != 0) {
 481                 return stat;
 482         }
 483         *top = cap->bounds.top;
 484         return 0;
 485 }
 486
 487 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 488 {
 489         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 490         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 491         if (stat != 0) {
 492                 return stat;
 493         }
 494         *top = cap->bounds.top;
 495         if (cap->bounds.height > cptr->hdw->croph_val) {
 496                 *top += cap->bounds.height - cptr->hdw->croph_val;
 497         }
 498         return 0;
 499 }
 500
 501 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 502 {
 503         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 504         int stat, bleftend, cleft;
 505
 506         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 507         if (stat != 0) {
 508                 return stat;
 509         }
 510         bleftend = cap->bounds.left+cap->bounds.width;
 511         cleft = cptr->hdw->cropl_val;
 512
 513         *width = cleft < bleftend ? bleftend-cleft : 0;
 514         return 0;
 515 }
 516
 517 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 518 {
 519         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 520         int stat, btopend, ctop;
 521
 522         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 523         if (stat != 0) {
 524                 return stat;
 525         }
 526         btopend = cap->bounds.top+cap->bounds.height;
 527         ctop = cptr->hdw->cropt_val;
 528
 529         *height = ctop < btopend ? btopend-ctop : 0;
 530         return 0;
 531 }
 532
 533 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 534 {
 535         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 536         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 537         if (stat != 0) {
 538                 return stat;
 539         }
 540         *val = cap->bounds.left;
 541         return 0;
 542 }
 543
 544 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 545 {
 546         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 547         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 548         if (stat != 0) {
 549                 return stat;
 550         }
 551         *val = cap->bounds.top;
 552         return 0;
 553 }
 554
 555 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 556 {
 557         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 558         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 559         if (stat != 0) {
 560                 return stat;
 561         }
 562         *val = cap->bounds.width;
 563         return 0;
 564 }
 565
 566 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 567 {
 568         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 569         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 570         if (stat != 0) {
 571                 return stat;
 572         }
 573         *val = cap->bounds.height;
 574         return 0;
 575 }
 576
 577 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 578 {
 579         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 580         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 581         if (stat != 0) {
 582                 return stat;
 583         }
 584         *val = cap->defrect.left;
 585         return 0;
 586 }
 587
 588 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 589 {
 590         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 591         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 592         if (stat != 0) {
 593                 return stat;
 594         }
 595         *val = cap->defrect.top;
 596         return 0;
 597 }
 598
 599 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 600 {
 601         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 602         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 603         if (stat != 0) {
 604                 return stat;
 605         }
 606         *val = cap->defrect.width;
 607         return 0;
 608 }
 609
 610 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 611 {
 612         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 613         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 614         if (stat != 0) {
 615                 return stat;
 616         }
 617         *val = cap->defrect.height;
 618         return 0;
 619 }
 620
 621 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 622 {
 623         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 624         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 625         if (stat != 0) {
 626                 return stat;
 627         }
 628         *val = cap->pixelaspect.numerator;
 629         return 0;
 630 }
 631
 632 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 633 {
 634         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 635         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 636         if (stat != 0) {
 637                 return stat;
 638         }
 639         *val = cap->pixelaspect.denominator;
 640         return 0;
 641 }
 642
 643 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 644 {
 645         /* Actual maximum depends on the video standard in effect. */
 646         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 647                 *vp = 480;
 648         } else {
 649                 *vp = 576;
 650         }
 651         return 0;
 652 }
 653
 654 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 655 {
 656         /* Actual minimum depends on device digitizer type. */
 657         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 658                 *vp = 75;
 659         } else {
 660                 *vp = 17;
 661         }
 662         return 0;
 663 }
 664
 665 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 666 {
 667         *vp = cptr->hdw->input_val;
 668         return 0;
 669 }
 670
 671 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 672 {
 673         if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
 674                 return 0;
 675         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 676 }
 677
 678 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 679 {
 680         return pvr2_hdw_set_input(cptr->hdw,v);
 681 }
 682
 683 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 684 {
 685         return cptr->hdw->input_dirty != 0;
 686 }
 687
 688 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 689 {
 690         cptr->hdw->input_dirty = 0;
 691 }
 692
 693
 694 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 695 {
 696         unsigned long fv;
 697         struct pvr2_hdw *hdw = cptr->hdw;
 698         if (hdw->tuner_signal_stale) {
 699                 pvr2_hdw_status_poll(hdw);
 700         }
 701         fv = hdw->tuner_signal_info.rangehigh;
 702         if (!fv) {
 703                 /* Safety fallback */
 704                 *vp = TV_MAX_FREQ;
 705                 return 0;
 706         }
 707         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 708                 fv = (fv * 125) / 2;
 709         } else {
 710                 fv = fv * 62500;
 711         }
 712         *vp = fv;
 713         return 0;
 714 }
 715
 716 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 717 {
 718         unsigned long fv;
 719         struct pvr2_hdw *hdw = cptr->hdw;
 720         if (hdw->tuner_signal_stale) {
 721                 pvr2_hdw_status_poll(hdw);
 722         }
 723         fv = hdw->tuner_signal_info.rangelow;
 724         if (!fv) {
 725                 /* Safety fallback */
 726                 *vp = TV_MIN_FREQ;
 727                 return 0;
 728         }
 729         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 730                 fv = (fv * 125) / 2;
 731         } else {
 732                 fv = fv * 62500;
 733         }
 734         *vp = fv;
 735         return 0;
 736 }
 737
 738 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 739 {
 740         return cptr->hdw->enc_stale != 0;
 741 }
 742
 743 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 744 {
 745         cptr->hdw->enc_stale = 0;
 746         cptr->hdw->enc_unsafe_stale = 0;
 747 }
 748
 749 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 750 {
 751         int ret;
 752         struct v4l2_ext_controls cs;
 753         struct v4l2_ext_control c1;
 754         memset(&cs,0,sizeof(cs));
 755         memset(&c1,0,sizeof(c1));
 756         cs.controls = &c1;
 757         cs.count = 1;
 758         c1.id = cptr->info->v4l_id;
 759         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 760                                 VIDIOC_G_EXT_CTRLS);
 761         if (ret) return ret;
 762         *vp = c1.value;
 763         return 0;
 764 }
 765
 766 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 767 {
 768         int ret;
 769         struct pvr2_hdw *hdw = cptr->hdw;
 770         struct v4l2_ext_controls cs;
 771         struct v4l2_ext_control c1;
 772         memset(&cs,0,sizeof(cs));
 773         memset(&c1,0,sizeof(c1));
 774         cs.controls = &c1;
 775         cs.count = 1;
 776         c1.id = cptr->info->v4l_id;
 777         c1.value = v;
 778         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 779                                 hdw->state_encoder_run, &cs,
 780                                 VIDIOC_S_EXT_CTRLS);
 781         if (ret == -EBUSY) {
 782                 /* Oops.  cx2341x is telling us it's not safe to change
 783                    this control while we're capturing.  Make a note of this
 784                    fact so that the pipeline will be stopped the next time
 785                    controls are committed.  Then go on ahead and store this
 786                    change anyway. */
 787                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 788                                         0, &cs,
 789                                         VIDIOC_S_EXT_CTRLS);
 790                 if (!ret) hdw->enc_unsafe_stale = !0;
 791         }
 792         if (ret) return ret;
 793         hdw->enc_stale = !0;
 794         return 0;
 795 }
 796
 797 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 798 {
 799         struct v4l2_queryctrl qctrl;
 800         struct pvr2_ctl_info *info;
 801         qctrl.id = cptr->info->v4l_id;
 802         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 803         /* Strip out the const so we can adjust a function pointer.  It's
 804            OK to do this here because we know this is a dynamically created
 805            control, so the underlying storage for the info pointer is (a)
 806            private to us, and (b) not in read-only storage.  Either we do
 807            this or we significantly complicate the underlying control
 808            implementation. */
 809         info = (struct pvr2_ctl_info *)(cptr->info);
 810         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 811                 if (info->set_value) {
 812                         info->set_value = NULL;
 813                 }
 814         } else {
 815                 if (!(info->set_value)) {
 816                         info->set_value = ctrl_cx2341x_set;
 817                 }
 818         }
 819         return qctrl.flags;
 820 }
 821
 822 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 823 {
 824         *vp = cptr->hdw->state_pipeline_req;
 825         return 0;
 826 }
 827
 828 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 829 {
 830         *vp = cptr->hdw->master_state;
 831         return 0;
 832 }
 833
 834 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 835 {
 836         int result = pvr2_hdw_is_hsm(cptr->hdw);
 837         *vp = PVR2_CVAL_HSM_FULL;
 838         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 839         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 840         return 0;
 841 }
 842
 843 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
 844 {
 845         *vp = pvr2_hdw_get_detected_std(cptr->hdw);
 846         return 0;
 847 }
 848
 849 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 850 {
 851         *vp = cptr->hdw->std_mask_avail;
 852         return 0;
 853 }
 854
 855 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 856 {
 857         struct pvr2_hdw *hdw = cptr->hdw;
 858         v4l2_std_id ns;
 859         ns = hdw->std_mask_avail;
 860         ns = (ns & ~m) | (v & m);
 861         if (ns == hdw->std_mask_avail) return 0;
 862         hdw->std_mask_avail = ns;
 863         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
 864         return 0;
 865 }
 866
 867 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 868                                char *bufPtr,unsigned int bufSize,
 869                                unsigned int *len)
 870 {
 871         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 872         return 0;
 873 }
 874
 875 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 876                                const char *bufPtr,unsigned int bufSize,
 877                                int *mskp,int *valp)
 878 {
 879         int ret;
 880         v4l2_std_id id;
 881         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 882         if (ret < 0) return ret;
 883         if (mskp) *mskp = id;
 884         if (valp) *valp = id;
 885         return 0;
 886 }
 887
 888 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 889 {
 890         *vp = cptr->hdw->std_mask_cur;
 891         return 0;
 892 }
 893
 894 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 895 {
 896         struct pvr2_hdw *hdw = cptr->hdw;
 897         v4l2_std_id ns;
 898         ns = hdw->std_mask_cur;
 899         ns = (ns & ~m) | (v & m);
 900         if (ns == hdw->std_mask_cur) return 0;
 901         hdw->std_mask_cur = ns;
 902         hdw->std_dirty = !0;
 903         return 0;
 904 }
 905
 906 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 907 {
 908         return cptr->hdw->std_dirty != 0;
 909 }
 910
 911 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 912 {
 913         cptr->hdw->std_dirty = 0;
 914 }
 915
 916 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 917 {
 918         struct pvr2_hdw *hdw = cptr->hdw;
 919         pvr2_hdw_status_poll(hdw);
 920         *vp = hdw->tuner_signal_info.signal;
 921         return 0;
 922 }
 923
 924 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 925 {
 926         int val = 0;
 927         unsigned int subchan;
 928         struct pvr2_hdw *hdw = cptr->hdw;
 929         pvr2_hdw_status_poll(hdw);
 930         subchan = hdw->tuner_signal_info.rxsubchans;
 931         if (subchan & V4L2_TUNER_SUB_MONO) {
 932                 val |= (1 << V4L2_TUNER_MODE_MONO);
 933         }
 934         if (subchan & V4L2_TUNER_SUB_STEREO) {
 935                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 936         }
 937         if (subchan & V4L2_TUNER_SUB_LANG1) {
 938                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 939         }
 940         if (subchan & V4L2_TUNER_SUB_LANG2) {
 941                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 942         }
 943         *vp = val;
 944         return 0;
 945 }
 946
 947
 948 #define DEFINT(vmin,vmax) \
 949         .type = pvr2_ctl_int, \
 950         .def.type_int.min_value = vmin, \
 951         .def.type_int.max_value = vmax
 952
 953 #define DEFENUM(tab) \
 954         .type = pvr2_ctl_enum, \
 955         .def.type_enum.count = ARRAY_SIZE(tab), \
 956         .def.type_enum.value_names = tab
 957
 958 #define DEFBOOL \
 959         .type = pvr2_ctl_bool
 960
 961 #define DEFMASK(msk,tab) \
 962         .type = pvr2_ctl_bitmask, \
 963         .def.type_bitmask.valid_bits = msk, \
 964         .def.type_bitmask.bit_names = tab
 965
 966 #define DEFREF(vname) \
 967         .set_value = ctrl_set_##vname, \
 968         .get_value = ctrl_get_##vname, \
 969         .is_dirty = ctrl_isdirty_##vname, \
 970         .clear_dirty = ctrl_cleardirty_##vname
 971
 972
 973 #define VCREATE_FUNCS(vname) \
 974 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 975 {*vp = cptr->hdw->vname##_val; return 0;} \
 976 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 977 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 978 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 979 {return cptr->hdw->vname##_dirty != 0;} \
 980 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 981 {cptr->hdw->vname##_dirty = 0;}
 982
 983 VCREATE_FUNCS(brightness)
 984 VCREATE_FUNCS(contrast)
 985 VCREATE_FUNCS(saturation)
 986 VCREATE_FUNCS(hue)
 987 VCREATE_FUNCS(volume)
 988 VCREATE_FUNCS(balance)
 989 VCREATE_FUNCS(bass)
 990 VCREATE_FUNCS(treble)
 991 VCREATE_FUNCS(mute)
 992 VCREATE_FUNCS(cropl)
 993 VCREATE_FUNCS(cropt)
 994 VCREATE_FUNCS(cropw)
 995 VCREATE_FUNCS(croph)
 996 VCREATE_FUNCS(audiomode)
 997 VCREATE_FUNCS(res_hor)
 998 VCREATE_FUNCS(res_ver)
 999 VCREATE_FUNCS(srate)
1000
1001 /* Table definition of all controls which can be manipulated */
1002 static const struct pvr2_ctl_info control_defs[] = {
1003         {
1004                 .v4l_id = V4L2_CID_BRIGHTNESS,
1005                 .desc = "Brightness",
1006                 .name = "brightness",
1007                 .default_value = 128,
1008                 DEFREF(brightness),
1009                 DEFINT(0,255),
1010         },{
1011                 .v4l_id = V4L2_CID_CONTRAST,
1012                 .desc = "Contrast",
1013                 .name = "contrast",
1014                 .default_value = 68,
1015                 DEFREF(contrast),
1016                 DEFINT(0,127),
1017         },{
1018                 .v4l_id = V4L2_CID_SATURATION,
1019                 .desc = "Saturation",
1020                 .name = "saturation",
1021                 .default_value = 64,
1022                 DEFREF(saturation),
1023                 DEFINT(0,127),
1024         },{
1025                 .v4l_id = V4L2_CID_HUE,
1026                 .desc = "Hue",
1027                 .name = "hue",
1028                 .default_value = 0,
1029                 DEFREF(hue),
1030                 DEFINT(-128,127),
1031         },{
1032                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1033                 .desc = "Volume",
1034                 .name = "volume",
1035                 .default_value = 62000,
1036                 DEFREF(volume),
1037                 DEFINT(0,65535),
1038         },{
1039                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1040                 .desc = "Balance",
1041                 .name = "balance",
1042                 .default_value = 0,
1043                 DEFREF(balance),
1044                 DEFINT(-32768,32767),
1045         },{
1046                 .v4l_id = V4L2_CID_AUDIO_BASS,
1047                 .desc = "Bass",
1048                 .name = "bass",
1049                 .default_value = 0,
1050                 DEFREF(bass),
1051                 DEFINT(-32768,32767),
1052         },{
1053                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1054                 .desc = "Treble",
1055                 .name = "treble",
1056                 .default_value = 0,
1057                 DEFREF(treble),
1058                 DEFINT(-32768,32767),
1059         },{
1060                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1061                 .desc = "Mute",
1062                 .name = "mute",
1063                 .default_value = 0,
1064                 DEFREF(mute),
1065                 DEFBOOL,
1066         }, {
1067                 .desc = "Capture crop left margin",
1068                 .name = "crop_left",
1069                 .internal_id = PVR2_CID_CROPL,
1070                 .default_value = 0,
1071                 DEFREF(cropl),
1072                 DEFINT(-129, 340),
1073                 .get_min_value = ctrl_cropl_min_get,
1074                 .get_max_value = ctrl_cropl_max_get,
1075                 .get_def_value = ctrl_get_cropcapdl,
1076         }, {
1077                 .desc = "Capture crop top margin",
1078                 .name = "crop_top",
1079                 .internal_id = PVR2_CID_CROPT,
1080                 .default_value = 0,
1081                 DEFREF(cropt),
1082                 DEFINT(-35, 544),
1083                 .get_min_value = ctrl_cropt_min_get,
1084                 .get_max_value = ctrl_cropt_max_get,
1085                 .get_def_value = ctrl_get_cropcapdt,
1086         }, {
1087                 .desc = "Capture crop width",
1088                 .name = "crop_width",
1089                 .internal_id = PVR2_CID_CROPW,
1090                 .default_value = 720,
1091                 DEFREF(cropw),
1092                 DEFINT(0, 864),
1093                 .get_max_value = ctrl_cropw_max_get,
1094                 .get_def_value = ctrl_get_cropcapdw,
1095         }, {
1096                 .desc = "Capture crop height",
1097                 .name = "crop_height",
1098                 .internal_id = PVR2_CID_CROPH,
1099                 .default_value = 480,
1100                 DEFREF(croph),
1101                 DEFINT(0, 576),
1102                 .get_max_value = ctrl_croph_max_get,
1103                 .get_def_value = ctrl_get_cropcapdh,
1104         }, {
1105                 .desc = "Capture capability pixel aspect numerator",
1106                 .name = "cropcap_pixel_numerator",
1107                 .internal_id = PVR2_CID_CROPCAPPAN,
1108                 .get_value = ctrl_get_cropcappan,
1109         }, {
1110                 .desc = "Capture capability pixel aspect denominator",
1111                 .name = "cropcap_pixel_denominator",
1112                 .internal_id = PVR2_CID_CROPCAPPAD,
1113                 .get_value = ctrl_get_cropcappad,
1114         }, {
1115                 .desc = "Capture capability bounds top",
1116                 .name = "cropcap_bounds_top",
1117                 .internal_id = PVR2_CID_CROPCAPBT,
1118                 .get_value = ctrl_get_cropcapbt,
1119         }, {
1120                 .desc = "Capture capability bounds left",
1121                 .name = "cropcap_bounds_left",
1122                 .internal_id = PVR2_CID_CROPCAPBL,
1123                 .get_value = ctrl_get_cropcapbl,
1124         }, {
1125                 .desc = "Capture capability bounds width",
1126                 .name = "cropcap_bounds_width",
1127                 .internal_id = PVR2_CID_CROPCAPBW,
1128                 .get_value = ctrl_get_cropcapbw,
1129         }, {
1130                 .desc = "Capture capability bounds height",
1131                 .name = "cropcap_bounds_height",
1132                 .internal_id = PVR2_CID_CROPCAPBH,
1133                 .get_value = ctrl_get_cropcapbh,
1134         },{
1135                 .desc = "Video Source",
1136                 .name = "input",
1137                 .internal_id = PVR2_CID_INPUT,
1138                 .default_value = PVR2_CVAL_INPUT_TV,
1139                 .check_value = ctrl_check_input,
1140                 DEFREF(input),
1141                 DEFENUM(control_values_input),
1142         },{
1143                 .desc = "Audio Mode",
1144                 .name = "audio_mode",
1145                 .internal_id = PVR2_CID_AUDIOMODE,
1146                 .default_value = V4L2_TUNER_MODE_STEREO,
1147                 DEFREF(audiomode),
1148                 DEFENUM(control_values_audiomode),
1149         },{
1150                 .desc = "Horizontal capture resolution",
1151                 .name = "resolution_hor",
1152                 .internal_id = PVR2_CID_HRES,
1153                 .default_value = 720,
1154                 DEFREF(res_hor),
1155                 DEFINT(19,720),
1156         },{
1157                 .desc = "Vertical capture resolution",
1158                 .name = "resolution_ver",
1159                 .internal_id = PVR2_CID_VRES,
1160                 .default_value = 480,
1161                 DEFREF(res_ver),
1162                 DEFINT(17,576),
1163                 /* Hook in check for video standard and adjust maximum
1164                    depending on the standard. */
1165                 .get_max_value = ctrl_vres_max_get,
1166                 .get_min_value = ctrl_vres_min_get,
1167         },{
1168                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1169                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1170                 .desc = "Audio Sampling Frequency",
1171                 .name = "srate",
1172                 DEFREF(srate),
1173                 DEFENUM(control_values_srate),
1174         },{
1175                 .desc = "Tuner Frequency (Hz)",
1176                 .name = "frequency",
1177                 .internal_id = PVR2_CID_FREQUENCY,
1178                 .default_value = 0,
1179                 .set_value = ctrl_freq_set,
1180                 .get_value = ctrl_freq_get,
1181                 .is_dirty = ctrl_freq_is_dirty,
1182                 .clear_dirty = ctrl_freq_clear_dirty,
1183                 DEFINT(0,0),
1184                 /* Hook in check for input value (tv/radio) and adjust
1185                    max/min values accordingly */
1186                 .get_max_value = ctrl_freq_max_get,
1187                 .get_min_value = ctrl_freq_min_get,
1188         },{
1189                 .desc = "Channel",
1190                 .name = "channel",
1191                 .set_value = ctrl_channel_set,
1192                 .get_value = ctrl_channel_get,
1193                 DEFINT(0,FREQTABLE_SIZE),
1194         },{
1195                 .desc = "Channel Program Frequency",
1196                 .name = "freq_table_value",
1197                 .set_value = ctrl_channelfreq_set,
1198                 .get_value = ctrl_channelfreq_get,
1199                 DEFINT(0,0),
1200                 /* Hook in check for input value (tv/radio) and adjust
1201                    max/min values accordingly */
1202                 .get_max_value = ctrl_freq_max_get,
1203                 .get_min_value = ctrl_freq_min_get,
1204         },{
1205                 .desc = "Channel Program ID",
1206                 .name = "freq_table_channel",
1207                 .set_value = ctrl_channelprog_set,
1208                 .get_value = ctrl_channelprog_get,
1209                 DEFINT(0,FREQTABLE_SIZE),
1210         },{
1211                 .desc = "Streaming Enabled",
1212                 .name = "streaming_enabled",
1213                 .get_value = ctrl_streamingenabled_get,
1214                 DEFBOOL,
1215         },{
1216                 .desc = "USB Speed",
1217                 .name = "usb_speed",
1218                 .get_value = ctrl_hsm_get,
1219                 DEFENUM(control_values_hsm),
1220         },{
1221                 .desc = "Master State",
1222                 .name = "master_state",
1223                 .get_value = ctrl_masterstate_get,
1224                 DEFENUM(pvr2_state_names),
1225         },{
1226                 .desc = "Signal Present",
1227                 .name = "signal_present",
1228                 .get_value = ctrl_signal_get,
1229                 DEFINT(0,65535),
1230         },{
1231                 .desc = "Audio Modes Present",
1232                 .name = "audio_modes_present",
1233                 .get_value = ctrl_audio_modes_present_get,
1234                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1235                    v4l.  Nothing outside of this module cares about this,
1236                    but I reuse it in order to also reuse the
1237                    control_values_audiomode string table. */
1238                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1239                          (1 << V4L2_TUNER_MODE_STEREO)|
1240                          (1 << V4L2_TUNER_MODE_LANG1)|
1241                          (1 << V4L2_TUNER_MODE_LANG2)),
1242                         control_values_audiomode),
1243         },{
1244                 .desc = "Video Standards Available Mask",
1245                 .name = "video_standard_mask_available",
1246                 .internal_id = PVR2_CID_STDAVAIL,
1247                 .skip_init = !0,
1248                 .get_value = ctrl_stdavail_get,
1249                 .set_value = ctrl_stdavail_set,
1250                 .val_to_sym = ctrl_std_val_to_sym,
1251                 .sym_to_val = ctrl_std_sym_to_val,
1252                 .type = pvr2_ctl_bitmask,
1253         },{
1254                 .desc = "Video Standards In Use Mask",
1255                 .name = "video_standard_mask_active",
1256                 .internal_id = PVR2_CID_STDCUR,
1257                 .skip_init = !0,
1258                 .get_value = ctrl_stdcur_get,
1259                 .set_value = ctrl_stdcur_set,
1260                 .is_dirty = ctrl_stdcur_is_dirty,
1261                 .clear_dirty = ctrl_stdcur_clear_dirty,
1262                 .val_to_sym = ctrl_std_val_to_sym,
1263                 .sym_to_val = ctrl_std_sym_to_val,
1264                 .type = pvr2_ctl_bitmask,
1265         },{
1266                 .desc = "Video Standards Detected Mask",
1267                 .name = "video_standard_mask_detected",
1268                 .internal_id = PVR2_CID_STDDETECT,
1269                 .skip_init = !0,
1270                 .get_value = ctrl_stddetect_get,
1271                 .val_to_sym = ctrl_std_val_to_sym,
1272                 .sym_to_val = ctrl_std_sym_to_val,
1273                 .type = pvr2_ctl_bitmask,
1274         }
1275 };
1276
1277 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1278
1279
1280 const char *pvr2_config_get_name(enum pvr2_config cfg)
1281 {
1282         switch (cfg) {
1283         case pvr2_config_empty: return "empty";
1284         case pvr2_config_mpeg: return "mpeg";
1285         case pvr2_config_vbi: return "vbi";
1286         case pvr2_config_pcm: return "pcm";
1287         case pvr2_config_rawvideo: return "raw video";
1288         }
1289         return "<unknown>";
1290 }
1291
1292
1293 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1294 {
1295         return hdw->usb_dev;
1296 }
1297
1298
1299 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1300 {
1301         return hdw->serial_number;
1302 }
1303
1304
1305 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1306 {
1307         return hdw->bus_info;
1308 }
1309
1310
1311 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1312 {
1313         return hdw->identifier;
1314 }
1315
1316
1317 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1318 {
1319         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1320 }
1321
1322 /* Set the currently tuned frequency and account for all possible
1323    driver-core side effects of this action. */
1324 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1325 {
1326         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1327                 if (hdw->freqSelector) {
1328                         /* Swing over to radio frequency selection */
1329                         hdw->freqSelector = 0;
1330                         hdw->freqDirty = !0;
1331                 }
1332                 if (hdw->freqValRadio != val) {
1333                         hdw->freqValRadio = val;
1334                         hdw->freqSlotRadio = 0;
1335                         hdw->freqDirty = !0;
1336                 }
1337         } else {
1338                 if (!(hdw->freqSelector)) {
1339                         /* Swing over to television frequency selection */
1340                         hdw->freqSelector = 1;
1341                         hdw->freqDirty = !0;
1342                 }
1343                 if (hdw->freqValTelevision != val) {
1344                         hdw->freqValTelevision = val;
1345                         hdw->freqSlotTelevision = 0;
1346                         hdw->freqDirty = !0;
1347                 }
1348         }
1349 }
1350
1351 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1352 {
1353         return hdw->unit_number;
1354 }
1355
1356
1357 /* Attempt to locate one of the given set of files.  Messages are logged
1358    appropriate to what has been found.  The return value will be 0 or
1359    greater on success (it will be the index of the file name found) and
1360    fw_entry will be filled in.  Otherwise a negative error is returned on
1361    failure.  If the return value is -ENOENT then no viable firmware file
1362    could be located. */
1363 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1364                                 const struct firmware **fw_entry,
1365                                 const char *fwtypename,
1366                                 unsigned int fwcount,
1367                                 const char *fwnames[])
1368 {
1369         unsigned int idx;
1370         int ret = -EINVAL;
1371         for (idx = 0; idx < fwcount; idx++) {
1372                 ret = reject_firmware(fw_entry,
1373                                        fwnames[idx],
1374                                        &hdw->usb_dev->dev);
1375                 if (!ret) {
1376                         trace_firmware("Located %s firmware: %s;"
1377                                        " uploading...",
1378                                        fwtypename,
1379                                        fwnames[idx]);
1380                         return idx;
1381                 }
1382                 if (ret == -ENOENT) continue;
1383                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1384                            "request_firmware fatal error with code=%d",ret);
1385                 return ret;
1386         }
1387         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1388                    "***WARNING***"
1389                    " Device %s firmware"
1390                    " seems to be missing.",
1391                    fwtypename);
1392         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1393                    "Did you install the pvrusb2 firmware files"
1394                    " in their proper location?");
1395         if (fwcount == 1) {
1396                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1397                            "request_firmware unable to locate %s file %s",
1398                            fwtypename,fwnames[0]);
1399         } else {
1400                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1401                            "request_firmware unable to locate"
1402                            " one of the following %s files:",
1403                            fwtypename);
1404                 for (idx = 0; idx < fwcount; idx++) {
1405                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1406                                    "reject_firmware: Failed to find %s",
1407                                    fwnames[idx]);
1408                 }
1409         }
1410         return ret;
1411 }
1412
1413
1414 /*
1415  * pvr2_upload_firmware1().
1416  *
1417  * Send the 8051 firmware to the device.  After the upload, arrange for
1418  * device to re-enumerate.
1419  *
1420  * NOTE : the pointer to the firmware data given by reject_firmware()
1421  * is not suitable for an usb transaction.
1422  *
1423  */
1424 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1425 {
1426         const struct firmware *fw_entry = NULL;
1427         void  *fw_ptr;
1428         unsigned int pipe;
1429         unsigned int fwsize;
1430         int ret;
1431         u16 address;
1432
1433         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1434                 hdw->fw1_state = FW1_STATE_OK;
1435                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1436                            "Connected device type defines"
1437                            " no firmware to upload; ignoring firmware");
1438                 return -ENOTTY;
1439         }
1440
1441         hdw->fw1_state = FW1_STATE_FAILED; // default result
1442
1443         trace_firmware("pvr2_upload_firmware1");
1444
1445         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1446                                    hdw->hdw_desc->fx2_firmware.cnt,
1447                                    hdw->hdw_desc->fx2_firmware.lst);
1448         if (ret < 0) {
1449                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1450                 return ret;
1451         }
1452
1453         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1454
1455         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1456         fwsize = fw_entry->size;
1457
1458         if ((fwsize != 0x2000) &&
1459             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1460                 if (hdw->hdw_desc->flag_fx2_16kb) {
1461                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1462                                    "Wrong fx2 firmware size"
1463                                    " (expected 8192 or 16384, got %u)",
1464                                    fwsize);
1465                 } else {
1466                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1467                                    "Wrong fx2 firmware size"
1468                                    " (expected 8192, got %u)",
1469                                    fwsize);
1470                 }
1471                 release_firmware(fw_entry);
1472                 return -ENOMEM;
1473         }
1474
1475         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1476         if (fw_ptr == NULL){
1477                 release_firmware(fw_entry);
1478                 return -ENOMEM;
1479         }
1480
1481         /* We have to hold the CPU during firmware upload. */
1482         pvr2_hdw_cpureset_assert(hdw,1);
1483
1484         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1485            chunk. */
1486
1487         ret = 0;
1488         for (address = 0; address < fwsize; address += 0x800) {
1489                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1490                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1491                                        0, fw_ptr, 0x800, 1000);
1492         }
1493
1494         trace_firmware("Upload done, releasing device's CPU");
1495
1496         /* Now release the CPU.  It will disconnect and reconnect later. */
1497         pvr2_hdw_cpureset_assert(hdw,0);
1498
1499         kfree(fw_ptr);
1500         release_firmware(fw_entry);
1501
1502         trace_firmware("Upload done (%d bytes sent)",ret);
1503
1504         /* We should have written fwsize bytes */
1505         if (ret == fwsize) {
1506                 hdw->fw1_state = FW1_STATE_RELOAD;
1507                 return 0;
1508         }
1509
1510         return -EIO;
1511 }
1512
1513
1514 /*
1515  * pvr2_upload_firmware2()
1516  *
1517  * This uploads encoder firmware on endpoint 2.
1518  *
1519  */
1520
1521 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1522 {
1523         const struct firmware *fw_entry = NULL;
1524         void  *fw_ptr;
1525         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1526         int actual_length;
1527         int ret = 0;
1528         int fwidx;
1529         static const char *fw_files[] = {
1530                 CX2341X_FIRM_ENC_FILENAME,
1531         };
1532
1533         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1534                 return 0;
1535         }
1536
1537         trace_firmware("pvr2_upload_firmware2");
1538
1539         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1540                                    ARRAY_SIZE(fw_files), fw_files);
1541         if (ret < 0) return ret;
1542         fwidx = ret;
1543         ret = 0;
1544         /* Since we're about to completely reinitialize the encoder,
1545            invalidate our cached copy of its configuration state.  Next
1546            time we configure the encoder, then we'll fully configure it. */
1547         hdw->enc_cur_valid = 0;
1548
1549         /* Encoder is about to be reset so note that as far as we're
1550            concerned now, the encoder has never been run. */
1551         del_timer_sync(&hdw->encoder_run_timer);
1552         if (hdw->state_encoder_runok) {
1553                 hdw->state_encoder_runok = 0;
1554                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1555         }
1556
1557         /* First prepare firmware loading */
1558         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1559         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1560         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1561         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1562         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1563         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1564         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1565         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1566         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1567         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1568         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1569         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1570         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1571         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1572         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1573         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1574         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1575         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1576
1577         if (ret) {
1578                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1579                            "firmware2 upload prep failed, ret=%d",ret);
1580                 release_firmware(fw_entry);
1581                 goto done;
1582         }
1583
1584         /* Now send firmware */
1585
1586         fw_len = fw_entry->size;
1587
1588         if (fw_len % sizeof(u32)) {
1589                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1590                            "size of %s firmware"
1591                            " must be a multiple of %zu bytes",
1592                            fw_files[fwidx],sizeof(u32));
1593                 release_firmware(fw_entry);
1594                 ret = -EINVAL;
1595                 goto done;
1596         }
1597
1598         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1599         if (fw_ptr == NULL){
1600                 release_firmware(fw_entry);
1601                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1602                            "failed to allocate memory for firmware2 upload");
1603                 ret = -ENOMEM;
1604                 goto done;
1605         }
1606
1607         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1608
1609         fw_done = 0;
1610         for (fw_done = 0; fw_done < fw_len;) {
1611                 bcnt = fw_len - fw_done;
1612                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1613                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1614                 /* Usbsnoop log shows that we must swap bytes... */
1615                 /* Some background info: The data being swapped here is a
1616                    firmware image destined for the mpeg encoder chip that
1617                    lives at the other end of a USB endpoint.  The encoder
1618                    chip always talks in 32 bit chunks and its storage is
1619                    organized into 32 bit words.  However from the file
1620                    system to the encoder chip everything is purely a byte
1621                    stream.  The firmware file's contents are always 32 bit
1622                    swapped from what the encoder expects.  Thus the need
1623                    always exists to swap the bytes regardless of the endian
1624                    type of the host processor and therefore swab32() makes
1625                    the most sense. */
1626                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1627                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1628
1629                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1630                                     &actual_length, 1000);
1631                 ret |= (actual_length != bcnt);
1632                 if (ret) break;
1633                 fw_done += bcnt;
1634         }
1635
1636         trace_firmware("upload of %s : %i / %i ",
1637                        fw_files[fwidx],fw_done,fw_len);
1638
1639         kfree(fw_ptr);
1640         release_firmware(fw_entry);
1641
1642         if (ret) {
1643                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1644                            "firmware2 upload transfer failure");
1645                 goto done;
1646         }
1647
1648         /* Finish upload */
1649
1650         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1651         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1652         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1653
1654         if (ret) {
1655                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1656                            "firmware2 upload post-proc failure");
1657         }
1658
1659  done:
1660         if (hdw->hdw_desc->signal_routing_scheme ==
1661             PVR2_ROUTING_SCHEME_GOTVIEW) {
1662                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1663                    hardware. */
1664                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1665         }
1666         return ret;
1667 }
1668
1669
1670 static const char *pvr2_get_state_name(unsigned int st)
1671 {
1672         if (st < ARRAY_SIZE(pvr2_state_names)) {
1673                 return pvr2_state_names[st];
1674         }
1675         return "???";
1676 }
1677
1678 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1679 {
1680         /* Even though we really only care about the video decoder chip at
1681            this point, we'll broadcast stream on/off to all sub-devices
1682            anyway, just in case somebody else wants to hear the
1683            command... */
1684         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1685                    (enablefl ? "on" : "off"));
1686         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1687         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1688         if (hdw->decoder_client_id) {
1689                 /* We get here if the encoder has been noticed.  Otherwise
1690                    we'll issue a warning to the user (which should
1691                    normally never happen). */
1692                 return 0;
1693         }
1694         if (!hdw->flag_decoder_missed) {
1695                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1696                            "WARNING: No decoder present");
1697                 hdw->flag_decoder_missed = !0;
1698                 trace_stbit("flag_decoder_missed",
1699                             hdw->flag_decoder_missed);
1700         }
1701         return -EIO;
1702 }
1703
1704
1705 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1706 {
1707         return hdw->master_state;
1708 }
1709
1710
1711 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1712 {
1713         if (!hdw->flag_tripped) return 0;
1714         hdw->flag_tripped = 0;
1715         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1716                    "Clearing driver error statuss");
1717         return !0;
1718 }
1719
1720
1721 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1722 {
1723         int fl;
1724         LOCK_TAKE(hdw->big_lock); do {
1725                 fl = pvr2_hdw_untrip_unlocked(hdw);
1726         } while (0); LOCK_GIVE(hdw->big_lock);
1727         if (fl) pvr2_hdw_state_sched(hdw);
1728         return 0;
1729 }
1730
1731
1732
1733
1734 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1735 {
1736         return hdw->state_pipeline_req != 0;
1737 }
1738
1739
1740 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1741 {
1742         int ret,st;
1743         LOCK_TAKE(hdw->big_lock); do {
1744                 pvr2_hdw_untrip_unlocked(hdw);
1745                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1746                         hdw->state_pipeline_req = enable_flag != 0;
1747                         pvr2_trace(PVR2_TRACE_START_STOP,
1748                                    "/*--TRACE_STREAM--*/ %s",
1749                                    enable_flag ? "enable" : "disable");
1750                 }
1751                 pvr2_hdw_state_sched(hdw);
1752         } while (0); LOCK_GIVE(hdw->big_lock);
1753         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1754         if (enable_flag) {
1755                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1756                         if (st != PVR2_STATE_READY) return -EIO;
1757                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1758                 }
1759         }
1760         return 0;
1761 }
1762
1763
1764 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1765 {
1766         int fl;
1767         LOCK_TAKE(hdw->big_lock);
1768         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1769                 hdw->desired_stream_type = config;
1770                 hdw->state_pipeline_config = 0;
1771                 trace_stbit("state_pipeline_config",
1772                             hdw->state_pipeline_config);
1773                 pvr2_hdw_state_sched(hdw);
1774         }
1775         LOCK_GIVE(hdw->big_lock);
1776         if (fl) return 0;
1777         return pvr2_hdw_wait(hdw,0);
1778 }
1779
1780
1781 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1782 {
1783         int unit_number = hdw->unit_number;
1784         int tp = -1;
1785         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1786                 tp = tuner[unit_number];
1787         }
1788         if (tp < 0) return -EINVAL;
1789         hdw->tuner_type = tp;
1790         hdw->tuner_updated = !0;
1791         return 0;
1792 }
1793
1794
1795 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1796 {
1797         int unit_number = hdw->unit_number;
1798         int tp = 0;
1799         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1800                 tp = video_std[unit_number];
1801                 if (tp) return tp;
1802         }
1803         return 0;
1804 }
1805
1806
1807 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1808 {
1809         int unit_number = hdw->unit_number;
1810         int tp = 0;
1811         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1812                 tp = tolerance[unit_number];
1813         }
1814         return tp;
1815 }
1816
1817
1818 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1819 {
1820         /* Try a harmless request to fetch the eeprom's address over
1821            endpoint 1.  See what happens.  Only the full FX2 image can
1822            respond to this.  If this probe fails then likely the FX2
1823            firmware needs be loaded. */
1824         int result;
1825         LOCK_TAKE(hdw->ctl_lock); do {
1826                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1827                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1828                                            hdw->cmd_buffer,1,
1829                                            hdw->cmd_buffer,1);
1830                 if (result < 0) break;
1831         } while(0); LOCK_GIVE(hdw->ctl_lock);
1832         if (result) {
1833                 pvr2_trace(PVR2_TRACE_INIT,
1834                            "Probe of device endpoint 1 result status %d",
1835                            result);
1836         } else {
1837                 pvr2_trace(PVR2_TRACE_INIT,
1838                            "Probe of device endpoint 1 succeeded");
1839         }
1840         return result == 0;
1841 }
1842
1843 struct pvr2_std_hack {
1844         v4l2_std_id pat;  /* Pattern to match */
1845         v4l2_std_id msk;  /* Which bits we care about */
1846         v4l2_std_id std;  /* What additional standards or default to set */
1847 };
1848
1849 /* This data structure labels specific combinations of standards from
1850    tveeprom that we'll try to recognize.  If we recognize one, then assume
1851    a specified default standard to use.  This is here because tveeprom only
1852    tells us about available standards not the intended default standard (if
1853    any) for the device in question.  We guess the default based on what has
1854    been reported as available.  Note that this is only for guessing a
1855    default - which can always be overridden explicitly - and if the user
1856    has otherwise named a default then that default will always be used in
1857    place of this table. */
1858 static const struct pvr2_std_hack std_eeprom_maps[] = {
1859         {       /* PAL(B/G) */
1860                 .pat = V4L2_STD_B|V4L2_STD_GH,
1861                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1862         },
1863         {       /* NTSC(M) */
1864                 .pat = V4L2_STD_MN,
1865                 .std = V4L2_STD_NTSC_M,
1866         },
1867         {       /* PAL(I) */
1868                 .pat = V4L2_STD_PAL_I,
1869                 .std = V4L2_STD_PAL_I,
1870         },
1871         {       /* SECAM(L/L') */
1872                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1873                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1874         },
1875         {       /* PAL(D/D1/K) */
1876                 .pat = V4L2_STD_DK,
1877                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1878         },
1879 };
1880
1881 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1882 {
1883         char buf[40];
1884         unsigned int bcnt;
1885         v4l2_std_id std1,std2,std3;
1886
1887         std1 = get_default_standard(hdw);
1888         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1889
1890         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1891         pvr2_trace(PVR2_TRACE_STD,
1892                    "Supported video standard(s) reported available"
1893                    " in hardware: %.*s",
1894                    bcnt,buf);
1895
1896         hdw->std_mask_avail = hdw->std_mask_eeprom;
1897
1898         std2 = (std1|std3) & ~hdw->std_mask_avail;
1899         if (std2) {
1900                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1901                 pvr2_trace(PVR2_TRACE_STD,
1902                            "Expanding supported video standards"
1903                            " to include: %.*s",
1904                            bcnt,buf);
1905                 hdw->std_mask_avail |= std2;
1906         }
1907
1908         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1909
1910         if (std1) {
1911                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1912                 pvr2_trace(PVR2_TRACE_STD,
1913                            "Initial video standard forced to %.*s",
1914                            bcnt,buf);
1915                 hdw->std_mask_cur = std1;
1916                 hdw->std_dirty = !0;
1917                 return;
1918         }
1919         if (std3) {
1920                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1921                 pvr2_trace(PVR2_TRACE_STD,
1922                            "Initial video standard"
1923                            " (determined by device type): %.*s",bcnt,buf);
1924                 hdw->std_mask_cur = std3;
1925                 hdw->std_dirty = !0;
1926                 return;
1927         }
1928
1929         {
1930                 unsigned int idx;
1931                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1932                         if (std_eeprom_maps[idx].msk ?
1933                             ((std_eeprom_maps[idx].pat ^
1934                              hdw->std_mask_eeprom) &
1935                              std_eeprom_maps[idx].msk) :
1936                             (std_eeprom_maps[idx].pat !=
1937                              hdw->std_mask_eeprom)) continue;
1938                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1939                                                   std_eeprom_maps[idx].std);
1940                         pvr2_trace(PVR2_TRACE_STD,
1941                                    "Initial video standard guessed as %.*s",
1942                                    bcnt,buf);
1943                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1944                         hdw->std_dirty = !0;
1945                         return;
1946                 }
1947         }
1948
1949 }
1950
1951
1952 static unsigned int pvr2_copy_i2c_addr_list(
1953         unsigned short *dst, const unsigned char *src,
1954         unsigned int dst_max)
1955 {
1956         unsigned int cnt = 0;
1957         if (!src) return 0;
1958         while (src[cnt] && (cnt + 1) < dst_max) {
1959                 dst[cnt] = src[cnt];
1960                 cnt++;
1961         }
1962         dst[cnt] = I2C_CLIENT_END;
1963         return cnt;
1964 }
1965
1966
1967 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1968 {
1969         /*
1970           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1971           for cx25840 causes that module to correctly set up its video
1972           scaling.  This is really a problem in the cx25840 module itself,
1973           but we work around it here.  The problem has not been seen in
1974           ivtv because there VBI is supported and set up.  We don't do VBI
1975           here (at least not yet) and thus we never attempted to even set
1976           it up.
1977         */
1978         struct v4l2_format fmt;
1979         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1980                 /* We're not using a cx25840 so don't enable the hack */
1981                 return;
1982         }
1983
1984         pvr2_trace(PVR2_TRACE_INIT,
1985                    "Module ID %u:"
1986                    " Executing cx25840 VBI hack",
1987                    hdw->decoder_client_id);
1988         memset(&fmt, 0, sizeof(fmt));
1989         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1990         fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1991         fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1992         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1993                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
1994 }
1995
1996
1997 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1998                                 const struct pvr2_device_client_desc *cd)
1999 {
2000         const char *fname;
2001         unsigned char mid;
2002         struct v4l2_subdev *sd;
2003         unsigned int i2ccnt;
2004         const unsigned char *p;
2005         /* Arbitrary count - max # i2c addresses we will probe */
2006         unsigned short i2caddr[25];
2007
2008         mid = cd->module_id;
2009         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2010         if (!fname) {
2011                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2012                            "Module ID %u for device %s has no name?"
2013                            "  The driver might have a configuration problem.",
2014                            mid,
2015                            hdw->hdw_desc->description);
2016                 return -EINVAL;
2017         }
2018         pvr2_trace(PVR2_TRACE_INIT,
2019                    "Module ID %u (%s) for device %s being loaded...",
2020                    mid, fname,
2021                    hdw->hdw_desc->description);
2022
2023         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2024                                          ARRAY_SIZE(i2caddr));
2025         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2026                          module_i2c_addresses[mid] : NULL) != NULL)) {
2027                 /* Second chance: Try default i2c address list */
2028                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2029                                                  ARRAY_SIZE(i2caddr));
2030                 if (i2ccnt) {
2031                         pvr2_trace(PVR2_TRACE_INIT,
2032                                    "Module ID %u:"
2033                                    " Using default i2c address list",
2034                                    mid);
2035                 }
2036         }
2037
2038         if (!i2ccnt) {
2039                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2040                            "Module ID %u (%s) for device %s:"
2041                            " No i2c addresses."
2042                            "  The driver might have a configuration problem.",
2043                            mid, fname, hdw->hdw_desc->description);
2044                 return -EINVAL;
2045         }
2046
2047         if (i2ccnt == 1) {
2048                 pvr2_trace(PVR2_TRACE_INIT,
2049                            "Module ID %u:"
2050                            " Setting up with specified i2c address 0x%x",
2051                            mid, i2caddr[0]);
2052                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2053                                          fname, i2caddr[0], NULL);
2054         } else {
2055                 pvr2_trace(PVR2_TRACE_INIT,
2056                            "Module ID %u:"
2057                            " Setting up with address probe list",
2058                            mid);
2059                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2060                                          fname, 0, i2caddr);
2061         }
2062
2063         if (!sd) {
2064                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2065                            "Module ID %u (%s) for device %s failed to load."
2066                            "  Possible missing sub-device kernel module or"
2067                            " initialization failure within module.",
2068                            mid, fname, hdw->hdw_desc->description);
2069                 return -EIO;
2070         }
2071
2072         /* Tag this sub-device instance with the module ID we know about.
2073            In other places we'll use that tag to determine if the instance
2074            requires special handling. */
2075         sd->grp_id = mid;
2076
2077         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2078
2079
2080         /* client-specific setup... */
2081         switch (mid) {
2082         case PVR2_CLIENT_ID_CX25840:
2083         case PVR2_CLIENT_ID_SAA7115:
2084                 hdw->decoder_client_id = mid;
2085                 break;
2086         default: break;
2087         }
2088
2089         return 0;
2090 }
2091
2092
2093 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2094 {
2095         unsigned int idx;
2096         const struct pvr2_string_table *cm;
2097         const struct pvr2_device_client_table *ct;
2098         int okFl = !0;
2099
2100         cm = &hdw->hdw_desc->client_modules;
2101         for (idx = 0; idx < cm->cnt; idx++) {
2102                 request_module(cm->lst[idx]);
2103         }
2104
2105         ct = &hdw->hdw_desc->client_table;
2106         for (idx = 0; idx < ct->cnt; idx++) {
2107                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2108         }
2109         if (!okFl) {
2110                 hdw->flag_modulefail = !0;
2111                 pvr2_hdw_render_useless(hdw);
2112         }
2113 }
2114
2115
2116 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2117 {
2118         int ret;
2119         unsigned int idx;
2120         struct pvr2_ctrl *cptr;
2121         int reloadFl = 0;
2122         if (hdw->hdw_desc->fx2_firmware.cnt) {
2123                 if (!reloadFl) {
2124                         reloadFl =
2125                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2126                                  == 0);
2127                         if (reloadFl) {
2128                                 pvr2_trace(PVR2_TRACE_INIT,
2129                                            "USB endpoint config looks strange"
2130                                            "; possibly firmware needs to be"
2131                                            " loaded");
2132                         }
2133                 }
2134                 if (!reloadFl) {
2135                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2136                         if (reloadFl) {
2137                                 pvr2_trace(PVR2_TRACE_INIT,
2138                                            "Check for FX2 firmware failed"
2139                                            "; possibly firmware needs to be"
2140                                            " loaded");
2141                         }
2142                 }
2143                 if (reloadFl) {
2144                         if (pvr2_upload_firmware1(hdw) != 0) {
2145                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2146                                            "Failure uploading firmware1");
2147                         }
2148                         return;
2149                 }
2150         }
2151         hdw->fw1_state = FW1_STATE_OK;
2152
2153         if (!pvr2_hdw_dev_ok(hdw)) return;
2154
2155         hdw->force_dirty = !0;
2156
2157         if (!hdw->hdw_desc->flag_no_powerup) {
2158                 pvr2_hdw_cmd_powerup(hdw);
2159                 if (!pvr2_hdw_dev_ok(hdw)) return;
2160         }
2161
2162         /* Take the IR chip out of reset, if appropriate */
2163         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2164                 pvr2_issue_simple_cmd(hdw,
2165                                       FX2CMD_HCW_ZILOG_RESET |
2166                                       (1 << 8) |
2167                                       ((0) << 16));
2168         }
2169
2170         // This step MUST happen after the earlier powerup step.
2171         pvr2_i2c_core_init(hdw);
2172         if (!pvr2_hdw_dev_ok(hdw)) return;
2173
2174         pvr2_hdw_load_modules(hdw);
2175         if (!pvr2_hdw_dev_ok(hdw)) return;
2176
2177         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2178
2179         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2180                 cptr = hdw->controls + idx;
2181                 if (cptr->info->skip_init) continue;
2182                 if (!cptr->info->set_value) continue;
2183                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2184         }
2185
2186         pvr2_hdw_cx25840_vbi_hack(hdw);
2187
2188         /* Set up special default values for the television and radio
2189            frequencies here.  It's not really important what these defaults
2190            are, but I set them to something usable in the Chicago area just
2191            to make driver testing a little easier. */
2192
2193         hdw->freqValTelevision = default_tv_freq;
2194         hdw->freqValRadio = default_radio_freq;
2195
2196         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2197         // thread-safe against the normal pvr2_send_request() mechanism.
2198         // (We should make it thread safe).
2199
2200         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2201                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2202                 if (!pvr2_hdw_dev_ok(hdw)) return;
2203                 if (ret < 0) {
2204                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2205                                    "Unable to determine location of eeprom,"
2206                                    " skipping");
2207                 } else {
2208                         hdw->eeprom_addr = ret;
2209                         pvr2_eeprom_analyze(hdw);
2210                         if (!pvr2_hdw_dev_ok(hdw)) return;
2211                 }
2212         } else {
2213                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2214                 hdw->tuner_updated = !0;
2215                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2216         }
2217
2218         if (hdw->serial_number) {
2219                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2220                                 "sn-%lu", hdw->serial_number);
2221         } else if (hdw->unit_number >= 0) {
2222                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2223                                 "unit-%c",
2224                                 hdw->unit_number + 'a');
2225         } else {
2226                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2227                                 "unit-??");
2228         }
2229         hdw->identifier[idx] = 0;
2230
2231         pvr2_hdw_setup_std(hdw);
2232
2233         if (!get_default_tuner_type(hdw)) {
2234                 pvr2_trace(PVR2_TRACE_INIT,
2235                            "pvr2_hdw_setup: Tuner type overridden to %d",
2236                            hdw->tuner_type);
2237         }
2238
2239
2240         if (!pvr2_hdw_dev_ok(hdw)) return;
2241
2242         if (hdw->hdw_desc->signal_routing_scheme ==
2243             PVR2_ROUTING_SCHEME_GOTVIEW) {
2244                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2245                    hardware. */
2246                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2247         }
2248
2249         pvr2_hdw_commit_setup(hdw);
2250
2251         hdw->vid_stream = pvr2_stream_create();
2252         if (!pvr2_hdw_dev_ok(hdw)) return;
2253         pvr2_trace(PVR2_TRACE_INIT,
2254                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2255         if (hdw->vid_stream) {
2256                 idx = get_default_error_tolerance(hdw);
2257                 if (idx) {
2258                         pvr2_trace(PVR2_TRACE_INIT,
2259                                    "pvr2_hdw_setup: video stream %p"
2260                                    " setting tolerance %u",
2261                                    hdw->vid_stream,idx);
2262                 }
2263                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2264                                   PVR2_VID_ENDPOINT,idx);
2265         }
2266
2267         if (!pvr2_hdw_dev_ok(hdw)) return;
2268
2269         hdw->flag_init_ok = !0;
2270
2271         pvr2_hdw_state_sched(hdw);
2272 }
2273
2274
2275 /* Set up the structure and attempt to put the device into a usable state.
2276    This can be a time-consuming operation, which is why it is not done
2277    internally as part of the create() step. */
2278 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2279 {
2280         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2281         do {
2282                 pvr2_hdw_setup_low(hdw);
2283                 pvr2_trace(PVR2_TRACE_INIT,
2284                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2285                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2286                 if (pvr2_hdw_dev_ok(hdw)) {
2287                         if (hdw->flag_init_ok) {
2288                                 pvr2_trace(
2289                                         PVR2_TRACE_INFO,
2290                                         "Device initialization"
2291                                         " completed successfully.");
2292                                 break;
2293                         }
2294                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2295                                 pvr2_trace(
2296                                         PVR2_TRACE_INFO,
2297                                         "Device microcontroller firmware"
2298                                         " (re)loaded; it should now reset"
2299                                         " and reconnect.");
2300                                 break;
2301                         }
2302                         pvr2_trace(
2303                                 PVR2_TRACE_ERROR_LEGS,
2304                                 "Device initialization was not successful.");
2305                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2306                                 pvr2_trace(
2307                                         PVR2_TRACE_ERROR_LEGS,
2308                                         "Giving up since device"
2309                                         " microcontroller firmware"
2310                                         " appears to be missing.");
2311                                 break;
2312                         }
2313                 }
2314                 if (hdw->flag_modulefail) {
2315                         pvr2_trace(
2316                                 PVR2_TRACE_ERROR_LEGS,
2317                                 "***WARNING*** pvrusb2 driver initialization"
2318                                 " failed due to the failure of one or more"
2319                                 " sub-device kernel modules.");
2320                         pvr2_trace(
2321                                 PVR2_TRACE_ERROR_LEGS,
2322                                 "You need to resolve the failing condition"
2323                                 " before this driver can function.  There"
2324                                 " should be some earlier messages giving more"
2325                                 " information about the problem.");
2326                         break;
2327                 }
2328                 if (procreload) {
2329                         pvr2_trace(
2330                                 PVR2_TRACE_ERROR_LEGS,
2331                                 "Attempting pvrusb2 recovery by reloading"
2332                                 " primary firmware.");
2333                         pvr2_trace(
2334                                 PVR2_TRACE_ERROR_LEGS,
2335                                 "If this works, device should disconnect"
2336                                 " and reconnect in a sane state.");
2337                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2338                         pvr2_upload_firmware1(hdw);
2339                 } else {
2340                         pvr2_trace(
2341                                 PVR2_TRACE_ERROR_LEGS,
2342                                 "***WARNING*** pvrusb2 device hardware"
2343                                 " appears to be jammed"
2344                                 " and I can't clear it.");
2345                         pvr2_trace(
2346                                 PVR2_TRACE_ERROR_LEGS,
2347                                 "You might need to power cycle"
2348                                 " the pvrusb2 device"
2349                                 " in order to recover.");
2350                 }
2351         } while (0);
2352         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2353 }
2354
2355
2356 /* Perform second stage initialization.  Set callback pointer first so that
2357    we can avoid a possible initialization race (if the kernel thread runs
2358    before the callback has been set). */
2359 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2360                         void (*callback_func)(void *),
2361                         void *callback_data)
2362 {
2363         LOCK_TAKE(hdw->big_lock); do {
2364                 if (hdw->flag_disconnected) {
2365                         /* Handle a race here: If we're already
2366                            disconnected by this point, then give up.  If we
2367                            get past this then we'll remain connected for
2368                            the duration of initialization since the entire
2369                            initialization sequence is now protected by the
2370                            big_lock. */
2371                         break;
2372                 }
2373                 hdw->state_data = callback_data;
2374                 hdw->state_func = callback_func;
2375                 pvr2_hdw_setup(hdw);
2376         } while (0); LOCK_GIVE(hdw->big_lock);
2377         return hdw->flag_init_ok;
2378 }
2379
2380
2381 /* Create, set up, and return a structure for interacting with the
2382    underlying hardware.  */
2383 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2384                                  const struct usb_device_id *devid)
2385 {
2386         unsigned int idx,cnt1,cnt2,m;
2387         struct pvr2_hdw *hdw = NULL;
2388         int valid_std_mask;
2389         struct pvr2_ctrl *cptr;
2390         struct usb_device *usb_dev;
2391         const struct pvr2_device_desc *hdw_desc;
2392         __u8 ifnum;
2393         struct v4l2_queryctrl qctrl;
2394         struct pvr2_ctl_info *ciptr;
2395
2396         usb_dev = interface_to_usbdev(intf);
2397
2398         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2399
2400         if (hdw_desc == NULL) {
2401                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2402                            " No device description pointer,"
2403                            " unable to continue.");
2404                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2405                            " please contact Mike Isely <isely@pobox.com>"
2406                            " to get it included in the driver\n");
2407                 goto fail;
2408         }
2409
2410         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2411         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2412                    hdw,hdw_desc->description);
2413         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2414                 hdw_desc->description);
2415         if (hdw_desc->flag_is_experimental) {
2416                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2417                 pvr2_trace(PVR2_TRACE_INFO,
2418                            "WARNING: Support for this device (%s) is"
2419                            " experimental.", hdw_desc->description);
2420                 pvr2_trace(PVR2_TRACE_INFO,
2421                            "Important functionality might not be"
2422                            " entirely working.");
2423                 pvr2_trace(PVR2_TRACE_INFO,
2424                            "Please consider contacting the driver author to"
2425                            " help with further stabilization of the driver.");
2426                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2427         }
2428         if (!hdw) goto fail;
2429
2430         setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout,
2431                     (unsigned long)hdw);
2432
2433         setup_timer(&hdw->decoder_stabilization_timer,
2434                     pvr2_hdw_decoder_stabilization_timeout,
2435                     (unsigned long)hdw);
2436
2437         setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2438                     (unsigned long)hdw);
2439
2440         setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout,
2441                     (unsigned long)hdw);
2442
2443         hdw->master_state = PVR2_STATE_DEAD;
2444
2445         init_waitqueue_head(&hdw->state_wait_data);
2446
2447         hdw->tuner_signal_stale = !0;
2448         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2449
2450         /* Calculate which inputs are OK */
2451         m = 0;
2452         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2453         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2454                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2455         }
2456         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2457         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2458         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2459         hdw->input_avail_mask = m;
2460         hdw->input_allowed_mask = hdw->input_avail_mask;
2461
2462         /* If not a hybrid device, pathway_state never changes.  So
2463            initialize it here to what it should forever be. */
2464         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2465                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2466         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2467                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2468         }
2469
2470         hdw->control_cnt = CTRLDEF_COUNT;
2471         hdw->control_cnt += MPEGDEF_COUNT;
2472         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2473                                 GFP_KERNEL);
2474         if (!hdw->controls) goto fail;
2475         hdw->hdw_desc = hdw_desc;
2476         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2477         for (idx = 0; idx < hdw->control_cnt; idx++) {
2478                 cptr = hdw->controls + idx;
2479                 cptr->hdw = hdw;
2480         }
2481         for (idx = 0; idx < 32; idx++) {
2482                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2483         }
2484         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2485                 cptr = hdw->controls + idx;
2486                 cptr->info = control_defs+idx;
2487         }
2488
2489         /* Ensure that default input choice is a valid one. */
2490         m = hdw->input_avail_mask;
2491         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2492                 if (!((1 << idx) & m)) continue;
2493                 hdw->input_val = idx;
2494                 break;
2495         }
2496
2497         /* Define and configure additional controls from cx2341x module. */
2498         hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2499                                       sizeof(*(hdw->mpeg_ctrl_info)),
2500                                       GFP_KERNEL);
2501         if (!hdw->mpeg_ctrl_info) goto fail;
2502         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2503                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2504                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2505                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2506                 ciptr->name = mpeg_ids[idx].strid;
2507                 ciptr->v4l_id = mpeg_ids[idx].id;
2508                 ciptr->skip_init = !0;
2509                 ciptr->get_value = ctrl_cx2341x_get;
2510                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2511                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2512                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2513                 qctrl.id = ciptr->v4l_id;
2514                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2515                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2516                         ciptr->set_value = ctrl_cx2341x_set;
2517                 }
2518                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2519                         PVR2_CTLD_INFO_DESC_SIZE);
2520                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2521                 ciptr->default_value = qctrl.default_value;
2522                 switch (qctrl.type) {
2523                 default:
2524                 case V4L2_CTRL_TYPE_INTEGER:
2525                         ciptr->type = pvr2_ctl_int;
2526                         ciptr->def.type_int.min_value = qctrl.minimum;
2527                         ciptr->def.type_int.max_value = qctrl.maximum;
2528                         break;
2529                 case V4L2_CTRL_TYPE_BOOLEAN:
2530                         ciptr->type = pvr2_ctl_bool;
2531                         break;
2532                 case V4L2_CTRL_TYPE_MENU:
2533                         ciptr->type = pvr2_ctl_enum;
2534                         ciptr->def.type_enum.value_names =
2535                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2536                                                                 ciptr->v4l_id);
2537                         for (cnt1 = 0;
2538                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2539                              cnt1++) { }
2540                         ciptr->def.type_enum.count = cnt1;
2541                         break;
2542                 }
2543                 cptr->info = ciptr;
2544         }
2545
2546         // Initialize control data regarding video standard masks
2547         valid_std_mask = pvr2_std_get_usable();
2548         for (idx = 0; idx < 32; idx++) {
2549                 if (!(valid_std_mask & (1 << idx))) continue;
2550                 cnt1 = pvr2_std_id_to_str(
2551                         hdw->std_mask_names[idx],
2552                         sizeof(hdw->std_mask_names[idx])-1,
2553                         1 << idx);
2554                 hdw->std_mask_names[idx][cnt1] = 0;
2555         }
2556         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2557         if (cptr) {
2558                 memcpy(&hdw->std_info_avail,cptr->info,
2559                        sizeof(hdw->std_info_avail));
2560                 cptr->info = &hdw->std_info_avail;
2561                 hdw->std_info_avail.def.type_bitmask.bit_names =
2562                         hdw->std_mask_ptrs;
2563                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2564                         valid_std_mask;
2565         }
2566         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2567         if (cptr) {
2568                 memcpy(&hdw->std_info_cur,cptr->info,
2569                        sizeof(hdw->std_info_cur));
2570                 cptr->info = &hdw->std_info_cur;
2571                 hdw->std_info_cur.def.type_bitmask.bit_names =
2572                         hdw->std_mask_ptrs;
2573                 hdw->std_info_cur.def.type_bitmask.valid_bits =
2574                         valid_std_mask;
2575         }
2576         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2577         if (cptr) {
2578                 memcpy(&hdw->std_info_detect,cptr->info,
2579                        sizeof(hdw->std_info_detect));
2580                 cptr->info = &hdw->std_info_detect;
2581                 hdw->std_info_detect.def.type_bitmask.bit_names =
2582                         hdw->std_mask_ptrs;
2583                 hdw->std_info_detect.def.type_bitmask.valid_bits =
2584                         valid_std_mask;
2585         }
2586
2587         hdw->cropcap_stale = !0;
2588         hdw->eeprom_addr = -1;
2589         hdw->unit_number = -1;
2590         hdw->v4l_minor_number_video = -1;
2591         hdw->v4l_minor_number_vbi = -1;
2592         hdw->v4l_minor_number_radio = -1;
2593         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2594         if (!hdw->ctl_write_buffer) goto fail;
2595         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2596         if (!hdw->ctl_read_buffer) goto fail;
2597         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2598         if (!hdw->ctl_write_urb) goto fail;
2599         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2600         if (!hdw->ctl_read_urb) goto fail;
2601
2602         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2603                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2604                            "Error registering with v4l core, giving up");
2605                 goto fail;
2606         }
2607         mutex_lock(&pvr2_unit_mtx);
2608         do {
2609                 for (idx = 0; idx < PVR_NUM; idx++) {
2610                         if (unit_pointers[idx]) continue;
2611                         hdw->unit_number = idx;
2612                         unit_pointers[idx] = hdw;
2613                         break;
2614                 }
2615         } while (0);
2616         mutex_unlock(&pvr2_unit_mtx);
2617
2618         cnt1 = 0;
2619         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2620         cnt1 += cnt2;
2621         if (hdw->unit_number >= 0) {
2622                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2623                                  ('a' + hdw->unit_number));
2624                 cnt1 += cnt2;
2625         }
2626         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2627         hdw->name[cnt1] = 0;
2628
2629         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2630
2631         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2632                    hdw->unit_number,hdw->name);
2633
2634         hdw->tuner_type = -1;
2635         hdw->flag_ok = !0;
2636
2637         hdw->usb_intf = intf;
2638         hdw->usb_dev = usb_dev;
2639
2640         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2641
2642         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2643         usb_set_interface(hdw->usb_dev,ifnum,0);
2644
2645         mutex_init(&hdw->ctl_lock_mutex);
2646         mutex_init(&hdw->big_lock_mutex);
2647
2648         return hdw;
2649  fail:
2650         if (hdw) {
2651                 del_timer_sync(&hdw->quiescent_timer);
2652                 del_timer_sync(&hdw->decoder_stabilization_timer);
2653                 del_timer_sync(&hdw->encoder_run_timer);
2654                 del_timer_sync(&hdw->encoder_wait_timer);
2655                 flush_work(&hdw->workpoll);
2656                 usb_free_urb(hdw->ctl_read_urb);
2657                 usb_free_urb(hdw->ctl_write_urb);
2658                 kfree(hdw->ctl_read_buffer);
2659                 kfree(hdw->ctl_write_buffer);
2660                 kfree(hdw->controls);
2661                 kfree(hdw->mpeg_ctrl_info);
2662                 kfree(hdw);
2663         }
2664         return NULL;
2665 }
2666
2667
2668 /* Remove _all_ associations between this driver and the underlying USB
2669    layer. */
2670 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2671 {
2672         if (hdw->flag_disconnected) return;
2673         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2674         if (hdw->ctl_read_urb) {
2675                 usb_kill_urb(hdw->ctl_read_urb);
2676                 usb_free_urb(hdw->ctl_read_urb);
2677                 hdw->ctl_read_urb = NULL;
2678         }
2679         if (hdw->ctl_write_urb) {
2680                 usb_kill_urb(hdw->ctl_write_urb);
2681                 usb_free_urb(hdw->ctl_write_urb);
2682                 hdw->ctl_write_urb = NULL;
2683         }
2684         if (hdw->ctl_read_buffer) {
2685                 kfree(hdw->ctl_read_buffer);
2686                 hdw->ctl_read_buffer = NULL;
2687         }
2688         if (hdw->ctl_write_buffer) {
2689                 kfree(hdw->ctl_write_buffer);
2690                 hdw->ctl_write_buffer = NULL;
2691         }
2692         hdw->flag_disconnected = !0;
2693         /* If we don't do this, then there will be a dangling struct device
2694            reference to our disappearing device persisting inside the V4L
2695            core... */
2696         v4l2_device_disconnect(&hdw->v4l2_dev);
2697         hdw->usb_dev = NULL;
2698         hdw->usb_intf = NULL;
2699         pvr2_hdw_render_useless(hdw);
2700 }
2701
2702 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2703 {
2704         vdev->v4l2_dev = &hdw->v4l2_dev;
2705 }
2706
2707 /* Destroy hardware interaction structure */
2708 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2709 {
2710         if (!hdw) return;
2711         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2712         flush_work(&hdw->workpoll);
2713         del_timer_sync(&hdw->quiescent_timer);
2714         del_timer_sync(&hdw->decoder_stabilization_timer);
2715         del_timer_sync(&hdw->encoder_run_timer);
2716         del_timer_sync(&hdw->encoder_wait_timer);
2717         if (hdw->fw_buffer) {
2718                 kfree(hdw->fw_buffer);
2719                 hdw->fw_buffer = NULL;
2720         }
2721         if (hdw->vid_stream) {
2722                 pvr2_stream_destroy(hdw->vid_stream);
2723                 hdw->vid_stream = NULL;
2724         }
2725         v4l2_device_unregister(&hdw->v4l2_dev);
2726         pvr2_hdw_disconnect(hdw);
2727         mutex_lock(&pvr2_unit_mtx);
2728         do {
2729                 if ((hdw->unit_number >= 0) &&
2730                     (hdw->unit_number < PVR_NUM) &&
2731                     (unit_pointers[hdw->unit_number] == hdw)) {
2732                         unit_pointers[hdw->unit_number] = NULL;
2733                 }
2734         } while (0);
2735         mutex_unlock(&pvr2_unit_mtx);
2736         kfree(hdw->controls);
2737         kfree(hdw->mpeg_ctrl_info);
2738         kfree(hdw);
2739 }
2740
2741
2742 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2743 {
2744         return (hdw && hdw->flag_ok);
2745 }
2746
2747
2748 /* Called when hardware has been unplugged */
2749 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2750 {
2751         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2752         LOCK_TAKE(hdw->big_lock);
2753         pvr2_i2c_core_done(hdw);
2754         LOCK_TAKE(hdw->ctl_lock);
2755         pvr2_hdw_remove_usb_stuff(hdw);
2756         LOCK_GIVE(hdw->ctl_lock);
2757         LOCK_GIVE(hdw->big_lock);
2758 }
2759
2760
2761 /* Get the number of defined controls */
2762 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2763 {
2764         return hdw->control_cnt;
2765 }
2766
2767
2768 /* Retrieve a control handle given its index (0..count-1) */
2769 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2770                                              unsigned int idx)
2771 {
2772         if (idx >= hdw->control_cnt) return NULL;
2773         return hdw->controls + idx;
2774 }
2775
2776
2777 /* Retrieve a control handle given its index (0..count-1) */
2778 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2779                                           unsigned int ctl_id)
2780 {
2781         struct pvr2_ctrl *cptr;
2782         unsigned int idx;
2783         int i;
2784
2785         /* This could be made a lot more efficient, but for now... */
2786         for (idx = 0; idx < hdw->control_cnt; idx++) {
2787                 cptr = hdw->controls + idx;
2788                 i = cptr->info->internal_id;
2789                 if (i && (i == ctl_id)) return cptr;
2790         }
2791         return NULL;
2792 }
2793
2794
2795 /* Given a V4L ID, retrieve the control structure associated with it. */
2796 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2797 {
2798         struct pvr2_ctrl *cptr;
2799         unsigned int idx;
2800         int i;
2801
2802         /* This could be made a lot more efficient, but for now... */
2803         for (idx = 0; idx < hdw->control_cnt; idx++) {
2804                 cptr = hdw->controls + idx;
2805                 i = cptr->info->v4l_id;
2806                 if (i && (i == ctl_id)) return cptr;
2807         }
2808         return NULL;
2809 }
2810
2811
2812 /* Given a V4L ID for its immediate predecessor, retrieve the control
2813    structure associated with it. */
2814 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2815                                             unsigned int ctl_id)
2816 {
2817         struct pvr2_ctrl *cptr,*cp2;
2818         unsigned int idx;
2819         int i;
2820
2821         /* This could be made a lot more efficient, but for now... */
2822         cp2 = NULL;
2823         for (idx = 0; idx < hdw->control_cnt; idx++) {
2824                 cptr = hdw->controls + idx;
2825                 i = cptr->info->v4l_id;
2826                 if (!i) continue;
2827                 if (i <= ctl_id) continue;
2828                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2829                 cp2 = cptr;
2830         }
2831         return cp2;
2832         return NULL;
2833 }
2834
2835
2836 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2837 {
2838         switch (tp) {
2839         case pvr2_ctl_int: return "integer";
2840         case pvr2_ctl_enum: return "enum";
2841         case pvr2_ctl_bool: return "boolean";
2842         case pvr2_ctl_bitmask: return "bitmask";
2843         }
2844         return "";
2845 }
2846
2847
2848 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2849                                     const char *name, int val)
2850 {
2851         struct v4l2_control ctrl;
2852         struct v4l2_subdev *sd;
2853
2854         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2855         memset(&ctrl, 0, sizeof(ctrl));
2856         ctrl.id = id;
2857         ctrl.value = val;
2858
2859         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2860                 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2861 }
2862
2863 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2864         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2865                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2866         }
2867
2868 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2869 {
2870         v4l2_std_id std;
2871         std = (v4l2_std_id)hdw->std_mask_avail;
2872         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2873                              video, querystd, &std);
2874         return std;
2875 }
2876
2877 /* Execute whatever commands are required to update the state of all the
2878    sub-devices so that they match our current control values. */
2879 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2880 {
2881         struct v4l2_subdev *sd;
2882         unsigned int id;
2883         pvr2_subdev_update_func fp;
2884
2885         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2886
2887         if (hdw->tuner_updated || hdw->force_dirty) {
2888                 struct tuner_setup setup;
2889                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2890                            hdw->tuner_type);
2891                 if (((int)(hdw->tuner_type)) >= 0) {
2892                         memset(&setup, 0, sizeof(setup));
2893                         setup.addr = ADDR_UNSET;
2894                         setup.type = hdw->tuner_type;
2895                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2896                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2897                                              tuner, s_type_addr, &setup);
2898                 }
2899         }
2900
2901         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2902                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2903                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2904                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2905                                              tuner, s_radio);
2906                 } else {
2907                         v4l2_std_id vs;
2908                         vs = hdw->std_mask_cur;
2909                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2910                                              video, s_std, vs);
2911                         pvr2_hdw_cx25840_vbi_hack(hdw);
2912                 }
2913                 hdw->tuner_signal_stale = !0;
2914                 hdw->cropcap_stale = !0;
2915         }
2916
2917         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2918         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2919         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2920         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2921         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2922         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2923         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2924         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2925         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2926
2927         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2928                 struct v4l2_tuner vt;
2929                 memset(&vt, 0, sizeof(vt));
2930                 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2931                         V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2932                 vt.audmode = hdw->audiomode_val;
2933                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2934         }
2935
2936         if (hdw->freqDirty || hdw->force_dirty) {
2937                 unsigned long fv;
2938                 struct v4l2_frequency freq;
2939                 fv = pvr2_hdw_get_cur_freq(hdw);
2940                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2941                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2942                 memset(&freq, 0, sizeof(freq));
2943                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2944                         /* ((fv * 1000) / 62500) */
2945                         freq.frequency = (fv * 2) / 125;
2946                 } else {
2947                         freq.frequency = fv / 62500;
2948                 }
2949                 /* tuner-core currently doesn't seem to care about this, but
2950                    let's set it anyway for completeness. */
2951                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2952                         freq.type = V4L2_TUNER_RADIO;
2953                 } else {
2954                         freq.type = V4L2_TUNER_ANALOG_TV;
2955                 }
2956                 freq.tuner = 0;
2957                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2958                                      s_frequency, &freq);
2959         }
2960
2961         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2962                 struct v4l2_subdev_format format = {
2963                         .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2964                 };
2965
2966                 format.format.width = hdw->res_hor_val;
2967                 format.format.height = hdw->res_ver_val;
2968                 format.format.code = MEDIA_BUS_FMT_FIXED;
2969                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2970                            format.format.width, format.format.height);
2971                 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2972                                      NULL, &format);
2973         }
2974
2975         if (hdw->srate_dirty || hdw->force_dirty) {
2976                 u32 val;
2977                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2978                            hdw->srate_val);
2979                 switch (hdw->srate_val) {
2980                 default:
2981                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2982                         val = 48000;
2983                         break;
2984                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2985                         val = 44100;
2986                         break;
2987                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2988                         val = 32000;
2989                         break;
2990                 }
2991                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2992                                      audio, s_clock_freq, val);
2993         }
2994
2995         /* Unable to set crop parameters; there is apparently no equivalent
2996            for VIDIOC_S_CROP */
2997
2998         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2999                 id = sd->grp_id;
3000                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3001                 fp = pvr2_module_update_functions[id];
3002                 if (!fp) continue;
3003                 (*fp)(hdw, sd);
3004         }
3005
3006         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3007                 pvr2_hdw_status_poll(hdw);
3008         }
3009 }
3010
3011
3012 /* Figure out if we need to commit control changes.  If so, mark internal
3013    state flags to indicate this fact and return true.  Otherwise do nothing
3014    else and return false. */
3015 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3016 {
3017         unsigned int idx;
3018         struct pvr2_ctrl *cptr;
3019         int value;
3020         int commit_flag = hdw->force_dirty;
3021         char buf[100];
3022         unsigned int bcnt,ccnt;
3023
3024         for (idx = 0; idx < hdw->control_cnt; idx++) {
3025                 cptr = hdw->controls + idx;
3026                 if (!cptr->info->is_dirty) continue;
3027                 if (!cptr->info->is_dirty(cptr)) continue;
3028                 commit_flag = !0;
3029
3030                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3031                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3032                                  cptr->info->name);
3033                 value = 0;
3034                 cptr->info->get_value(cptr,&value);
3035                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3036                                                 buf+bcnt,
3037                                                 sizeof(buf)-bcnt,&ccnt);
3038                 bcnt += ccnt;
3039                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3040                                   get_ctrl_typename(cptr->info->type));
3041                 pvr2_trace(PVR2_TRACE_CTL,
3042                            "/*--TRACE_COMMIT--*/ %.*s",
3043                            bcnt,buf);
3044         }
3045
3046         if (!commit_flag) {
3047                 /* Nothing has changed */
3048                 return 0;
3049         }
3050
3051         hdw->state_pipeline_config = 0;
3052         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3053         pvr2_hdw_state_sched(hdw);
3054
3055         return !0;
3056 }
3057
3058
3059 /* Perform all operations needed to commit all control changes.  This must
3060    be performed in synchronization with the pipeline state and is thus
3061    expected to be called as part of the driver's worker thread.  Return
3062    true if commit successful, otherwise return false to indicate that
3063    commit isn't possible at this time. */
3064 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3065 {
3066         unsigned int idx;
3067         struct pvr2_ctrl *cptr;
3068         int disruptive_change;
3069
3070         if (hdw->input_dirty && hdw->state_pathway_ok &&
3071             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3072               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3073              hdw->pathway_state)) {
3074                 /* Change of mode being asked for... */
3075                 hdw->state_pathway_ok = 0;
3076                 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3077         }
3078         if (!hdw->state_pathway_ok) {
3079                 /* Can't commit anything until pathway is ok. */
3080                 return 0;
3081         }
3082
3083         /* Handle some required side effects when the video standard is
3084            changed.... */
3085         if (hdw->std_dirty) {
3086                 int nvres;
3087                 int gop_size;
3088                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3089                         nvres = 480;
3090                         gop_size = 15;
3091                 } else {
3092                         nvres = 576;
3093                         gop_size = 12;
3094                 }
3095                 /* Rewrite the vertical resolution to be appropriate to the
3096                    video standard that has been selected. */
3097                 if (nvres != hdw->res_ver_val) {
3098                         hdw->res_ver_val = nvres;
3099                         hdw->res_ver_dirty = !0;
3100                 }
3101                 /* Rewrite the GOP size to be appropriate to the video
3102                    standard that has been selected. */
3103                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3104                         struct v4l2_ext_controls cs;
3105                         struct v4l2_ext_control c1;
3106                         memset(&cs, 0, sizeof(cs));
3107                         memset(&c1, 0, sizeof(c1));
3108                         cs.controls = &c1;
3109                         cs.count = 1;
3110                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3111                         c1.value = gop_size;
3112                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3113                                           VIDIOC_S_EXT_CTRLS);
3114                 }
3115         }
3116
3117         /* The broadcast decoder can only scale down, so if
3118          * res_*_dirty && crop window < output format ==> enlarge crop.
3119          *
3120          * The mpeg encoder receives fields of res_hor_val dots and
3121          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3122          */
3123         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3124                 hdw->cropw_val = hdw->res_hor_val;
3125                 hdw->cropw_dirty = !0;
3126         } else if (hdw->cropw_dirty) {
3127                 hdw->res_hor_dirty = !0;           /* must rescale */
3128                 hdw->res_hor_val = min(720, hdw->cropw_val);
3129         }
3130         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3131                 hdw->croph_val = hdw->res_ver_val;
3132                 hdw->croph_dirty = !0;
3133         } else if (hdw->croph_dirty) {
3134                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3135                 hdw->res_ver_dirty = !0;
3136                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3137         }
3138
3139         /* If any of the below has changed, then we can't do the update
3140            while the pipeline is running.  Pipeline must be paused first
3141            and decoder -> encoder connection be made quiescent before we
3142            can proceed. */
3143         disruptive_change =
3144                 (hdw->std_dirty ||
3145                  hdw->enc_unsafe_stale ||
3146                  hdw->srate_dirty ||
3147                  hdw->res_ver_dirty ||
3148                  hdw->res_hor_dirty ||
3149                  hdw->cropw_dirty ||
3150                  hdw->croph_dirty ||
3151                  hdw->input_dirty ||
3152                  (hdw->active_stream_type != hdw->desired_stream_type));
3153         if (disruptive_change && !hdw->state_pipeline_idle) {
3154                 /* Pipeline is not idle; we can't proceed.  Arrange to
3155                    cause pipeline to stop so that we can try this again
3156                    later.... */
3157                 hdw->state_pipeline_pause = !0;
3158                 return 0;
3159         }
3160
3161         if (hdw->srate_dirty) {
3162                 /* Write new sample rate into control structure since
3163                  * the master copy is stale.  We must track srate
3164                  * separate from the mpeg control structure because
3165                  * other logic also uses this value. */
3166                 struct v4l2_ext_controls cs;
3167                 struct v4l2_ext_control c1;
3168                 memset(&cs,0,sizeof(cs));
3169                 memset(&c1,0,sizeof(c1));
3170                 cs.controls = &c1;
3171                 cs.count = 1;
3172                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3173                 c1.value = hdw->srate_val;
3174                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3175         }
3176
3177         if (hdw->active_stream_type != hdw->desired_stream_type) {
3178                 /* Handle any side effects of stream config here */
3179                 hdw->active_stream_type = hdw->desired_stream_type;
3180         }
3181
3182         if (hdw->hdw_desc->signal_routing_scheme ==
3183             PVR2_ROUTING_SCHEME_GOTVIEW) {
3184                 u32 b;
3185                 /* Handle GOTVIEW audio switching */
3186                 pvr2_hdw_gpio_get_out(hdw,&b);
3187                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3188                         /* Set GPIO 11 */
3189                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3190                 } else {
3191                         /* Clear GPIO 11 */
3192                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3193                 }
3194         }
3195
3196         /* Check and update state for all sub-devices. */
3197         pvr2_subdev_update(hdw);
3198
3199         hdw->tuner_updated = 0;
3200         hdw->force_dirty = 0;
3201         for (idx = 0; idx < hdw->control_cnt; idx++) {
3202                 cptr = hdw->controls + idx;
3203                 if (!cptr->info->clear_dirty) continue;
3204                 cptr->info->clear_dirty(cptr);
3205         }
3206
3207         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3208             hdw->state_encoder_run) {
3209                 /* If encoder isn't running or it can't be touched, then
3210                    this will get worked out later when we start the
3211                    encoder. */
3212                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3213         }
3214
3215         hdw->state_pipeline_config = !0;
3216         /* Hardware state may have changed in a way to cause the cropping
3217            capabilities to have changed.  So mark it stale, which will
3218            cause a later re-fetch. */
3219         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3220         return !0;
3221 }
3222
3223
3224 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3225 {
3226         int fl;
3227         LOCK_TAKE(hdw->big_lock);
3228         fl = pvr2_hdw_commit_setup(hdw);
3229         LOCK_GIVE(hdw->big_lock);
3230         if (!fl) return 0;
3231         return pvr2_hdw_wait(hdw,0);
3232 }
3233
3234
3235 static void pvr2_hdw_worker_poll(struct work_struct *work)
3236 {
3237         int fl = 0;
3238         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3239         LOCK_TAKE(hdw->big_lock); do {
3240                 fl = pvr2_hdw_state_eval(hdw);
3241         } while (0); LOCK_GIVE(hdw->big_lock);
3242         if (fl && hdw->state_func) {
3243                 hdw->state_func(hdw->state_data);
3244         }
3245 }
3246
3247
3248 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3249 {
3250         return wait_event_interruptible(
3251                 hdw->state_wait_data,
3252                 (hdw->state_stale == 0) &&
3253                 (!state || (hdw->master_state != state)));
3254 }
3255
3256
3257 /* Return name for this driver instance */
3258 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3259 {
3260         return hdw->name;
3261 }
3262
3263
3264 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3265 {
3266         return hdw->hdw_desc->description;
3267 }
3268
3269
3270 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3271 {
3272         return hdw->hdw_desc->shortname;
3273 }
3274
3275
3276 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3277 {
3278         int result;
3279         LOCK_TAKE(hdw->ctl_lock); do {
3280                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3281                 result = pvr2_send_request(hdw,
3282                                            hdw->cmd_buffer,1,
3283                                            hdw->cmd_buffer,1);
3284                 if (result < 0) break;
3285                 result = (hdw->cmd_buffer[0] != 0);
3286         } while(0); LOCK_GIVE(hdw->ctl_lock);
3287         return result;
3288 }
3289
3290
3291 /* Execute poll of tuner status */
3292 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3293 {
3294         LOCK_TAKE(hdw->big_lock); do {
3295                 pvr2_hdw_status_poll(hdw);
3296         } while (0); LOCK_GIVE(hdw->big_lock);
3297 }
3298
3299
3300 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3301 {
3302         if (!hdw->cropcap_stale) {
3303                 return 0;
3304         }
3305         pvr2_hdw_status_poll(hdw);
3306         if (hdw->cropcap_stale) {
3307                 return -EIO;
3308         }
3309         return 0;
3310 }
3311
3312
3313 /* Return information about cropping capabilities */
3314 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3315 {
3316         int stat = 0;
3317         LOCK_TAKE(hdw->big_lock);
3318         stat = pvr2_hdw_check_cropcap(hdw);
3319         if (!stat) {
3320                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3321         }
3322         LOCK_GIVE(hdw->big_lock);
3323         return stat;
3324 }
3325
3326
3327 /* Return information about the tuner */
3328 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3329 {
3330         LOCK_TAKE(hdw->big_lock); do {
3331                 if (hdw->tuner_signal_stale) {
3332                         pvr2_hdw_status_poll(hdw);
3333                 }
3334                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3335         } while (0); LOCK_GIVE(hdw->big_lock);
3336         return 0;
3337 }
3338
3339
3340 /* Get handle to video output stream */
3341 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3342 {
3343         return hp->vid_stream;
3344 }
3345
3346
3347 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3348 {
3349         int nr = pvr2_hdw_get_unit_number(hdw);
3350         LOCK_TAKE(hdw->big_lock);
3351         do {
3352                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3353                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3354                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3355                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3356                 pvr2_hdw_state_log_state(hdw);
3357                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3358         } while (0);
3359         LOCK_GIVE(hdw->big_lock);
3360 }
3361
3362
3363 /* Grab EEPROM contents, needed for direct method. */
3364 #define EEPROM_SIZE 8192
3365 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3366 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3367 {
3368         struct i2c_msg msg[2];
3369         u8 *eeprom;
3370         u8 iadd[2];
3371         u8 addr;
3372         u16 eepromSize;
3373         unsigned int offs;
3374         int ret;
3375         int mode16 = 0;
3376         unsigned pcnt,tcnt;
3377         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3378         if (!eeprom) {
3379                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3380                            "Failed to allocate memory"
3381                            " required to read eeprom");
3382                 return NULL;
3383         }
3384
3385         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3386                      hdw->eeprom_addr);
3387         addr = hdw->eeprom_addr;
3388         /* Seems that if the high bit is set, then the *real* eeprom
3389            address is shifted right now bit position (noticed this in
3390            newer PVR USB2 hardware) */
3391         if (addr & 0x80) addr >>= 1;
3392
3393         /* FX2 documentation states that a 16bit-addressed eeprom is
3394            expected if the I2C address is an odd number (yeah, this is
3395            strange but it's what they do) */
3396         mode16 = (addr & 1);
3397         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3398         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3399                      " using %d bit addressing",eepromSize,addr,
3400                      mode16 ? 16 : 8);
3401
3402         msg[0].addr = addr;
3403         msg[0].flags = 0;
3404         msg[0].len = mode16 ? 2 : 1;
3405         msg[0].buf = iadd;
3406         msg[1].addr = addr;
3407         msg[1].flags = I2C_M_RD;
3408
3409         /* We have to do the actual eeprom data fetch ourselves, because
3410            (1) we're only fetching part of the eeprom, and (2) if we were
3411            getting the whole thing our I2C driver can't grab it in one
3412            pass - which is what tveeprom is otherwise going to attempt */
3413         memset(eeprom,0,EEPROM_SIZE);
3414         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3415                 pcnt = 16;
3416                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3417                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3418                 if (mode16) {
3419                         iadd[0] = offs >> 8;
3420                         iadd[1] = offs;
3421                 } else {
3422                         iadd[0] = offs;
3423                 }
3424                 msg[1].len = pcnt;
3425                 msg[1].buf = eeprom+tcnt;
3426                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3427                                         msg,ARRAY_SIZE(msg))) != 2) {
3428                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3429                                    "eeprom fetch set offs err=%d",ret);
3430                         kfree(eeprom);
3431                         return NULL;
3432                 }
3433         }
3434         return eeprom;
3435 }
3436
3437
3438 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3439                                 int mode,
3440                                 int enable_flag)
3441 {
3442         int ret;
3443         u16 address;
3444         unsigned int pipe;
3445         LOCK_TAKE(hdw->big_lock); do {
3446                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3447
3448                 if (!enable_flag) {
3449                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3450                                    "Cleaning up after CPU firmware fetch");
3451                         kfree(hdw->fw_buffer);
3452                         hdw->fw_buffer = NULL;
3453                         hdw->fw_size = 0;
3454                         if (hdw->fw_cpu_flag) {
3455                                 /* Now release the CPU.  It will disconnect
3456                                    and reconnect later. */
3457                                 pvr2_hdw_cpureset_assert(hdw,0);
3458                         }
3459                         break;
3460                 }
3461
3462                 hdw->fw_cpu_flag = (mode != 2);
3463                 if (hdw->fw_cpu_flag) {
3464                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3465                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3466                                    "Preparing to suck out CPU firmware"
3467                                    " (size=%u)", hdw->fw_size);
3468                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3469                         if (!hdw->fw_buffer) {
3470                                 hdw->fw_size = 0;
3471                                 break;
3472                         }
3473
3474                         /* We have to hold the CPU during firmware upload. */
3475                         pvr2_hdw_cpureset_assert(hdw,1);
3476
3477                         /* download the firmware from address 0000-1fff in 2048
3478                            (=0x800) bytes chunk. */
3479
3480                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3481                                    "Grabbing CPU firmware");
3482                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3483                         for(address = 0; address < hdw->fw_size;
3484                             address += 0x800) {
3485                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3486                                                       0xa0,0xc0,
3487                                                       address,0,
3488                                                       hdw->fw_buffer+address,
3489                                                       0x800,1000);
3490                                 if (ret < 0) break;
3491                         }
3492
3493                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3494                                    "Done grabbing CPU firmware");
3495                 } else {
3496                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3497                                    "Sucking down EEPROM contents");
3498                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3499                         if (!hdw->fw_buffer) {
3500                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3501                                            "EEPROM content suck failed.");
3502                                 break;
3503                         }
3504                         hdw->fw_size = EEPROM_SIZE;
3505                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3506                                    "Done sucking down EEPROM contents");
3507                 }
3508
3509         } while (0); LOCK_GIVE(hdw->big_lock);
3510 }
3511
3512
3513 /* Return true if we're in a mode for retrieval CPU firmware */
3514 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3515 {
3516         return hdw->fw_buffer != NULL;
3517 }
3518
3519
3520 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3521                        char *buf,unsigned int cnt)
3522 {
3523         int ret = -EINVAL;
3524         LOCK_TAKE(hdw->big_lock); do {
3525                 if (!buf) break;
3526                 if (!cnt) break;
3527
3528                 if (!hdw->fw_buffer) {
3529                         ret = -EIO;
3530                         break;
3531                 }
3532
3533                 if (offs >= hdw->fw_size) {
3534                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3535                                    "Read firmware data offs=%d EOF",
3536                                    offs);
3537                         ret = 0;
3538                         break;
3539                 }
3540
3541                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3542
3543                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3544
3545                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3546                            "Read firmware data offs=%d cnt=%d",
3547                            offs,cnt);
3548                 ret = cnt;
3549         } while (0); LOCK_GIVE(hdw->big_lock);
3550
3551         return ret;
3552 }
3553
3554
3555 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3556                                   enum pvr2_v4l_type index)
3557 {
3558         switch (index) {
3559         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3560         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3561         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3562         default: return -1;
3563         }
3564 }
3565
3566
3567 /* Store a v4l minor device number */
3568 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3569                                      enum pvr2_v4l_type index,int v)
3570 {
3571         switch (index) {
3572         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3573         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3574         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3575         default: break;
3576         }
3577 }
3578
3579
3580 static void pvr2_ctl_write_complete(struct urb *urb)
3581 {
3582         struct pvr2_hdw *hdw = urb->context;
3583         hdw->ctl_write_pend_flag = 0;
3584         if (hdw->ctl_read_pend_flag) return;
3585         complete(&hdw->ctl_done);
3586 }
3587
3588
3589 static void pvr2_ctl_read_complete(struct urb *urb)
3590 {
3591         struct pvr2_hdw *hdw = urb->context;
3592         hdw->ctl_read_pend_flag = 0;
3593         if (hdw->ctl_write_pend_flag) return;
3594         complete(&hdw->ctl_done);
3595 }
3596
3597
3598 static void pvr2_ctl_timeout(unsigned long data)
3599 {
3600         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3601         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3602                 hdw->ctl_timeout_flag = !0;
3603                 if (hdw->ctl_write_pend_flag)
3604                         usb_unlink_urb(hdw->ctl_write_urb);
3605                 if (hdw->ctl_read_pend_flag)
3606                         usb_unlink_urb(hdw->ctl_read_urb);
3607         }
3608 }
3609
3610
3611 /* Issue a command and get a response from the device.  This extended
3612    version includes a probe flag (which if set means that device errors
3613    should not be logged or treated as fatal) and a timeout in jiffies.
3614    This can be used to non-lethally probe the health of endpoint 1. */
3615 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3616                                 unsigned int timeout,int probe_fl,
3617                                 void *write_data,unsigned int write_len,
3618                                 void *read_data,unsigned int read_len)
3619 {
3620         unsigned int idx;
3621         int status = 0;
3622         struct timer_list timer;
3623         if (!hdw->ctl_lock_held) {
3624                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3625                            "Attempted to execute control transfer"
3626                            " without lock!!");
3627                 return -EDEADLK;
3628         }
3629         if (!hdw->flag_ok && !probe_fl) {
3630                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3631                            "Attempted to execute control transfer"
3632                            " when device not ok");
3633                 return -EIO;
3634         }
3635         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3636                 if (!probe_fl) {
3637                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3638                                    "Attempted to execute control transfer"
3639                                    " when USB is disconnected");
3640                 }
3641                 return -ENOTTY;
3642         }
3643
3644         /* Ensure that we have sane parameters */
3645         if (!write_data) write_len = 0;
3646         if (!read_data) read_len = 0;
3647         if (write_len > PVR2_CTL_BUFFSIZE) {
3648                 pvr2_trace(
3649                         PVR2_TRACE_ERROR_LEGS,
3650                         "Attempted to execute %d byte"
3651                         " control-write transfer (limit=%d)",
3652                         write_len,PVR2_CTL_BUFFSIZE);
3653                 return -EINVAL;
3654         }
3655         if (read_len > PVR2_CTL_BUFFSIZE) {
3656                 pvr2_trace(
3657                         PVR2_TRACE_ERROR_LEGS,
3658                         "Attempted to execute %d byte"
3659                         " control-read transfer (limit=%d)",
3660                         write_len,PVR2_CTL_BUFFSIZE);
3661                 return -EINVAL;
3662         }
3663         if ((!write_len) && (!read_len)) {
3664                 pvr2_trace(
3665                         PVR2_TRACE_ERROR_LEGS,
3666                         "Attempted to execute null control transfer?");
3667                 return -EINVAL;
3668         }
3669
3670
3671         hdw->cmd_debug_state = 1;
3672         if (write_len && write_data)
3673                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3674         else
3675                 hdw->cmd_debug_code = 0;
3676         hdw->cmd_debug_write_len = write_len;
3677         hdw->cmd_debug_read_len = read_len;
3678
3679         /* Initialize common stuff */
3680         init_completion(&hdw->ctl_done);
3681         hdw->ctl_timeout_flag = 0;
3682         hdw->ctl_write_pend_flag = 0;
3683         hdw->ctl_read_pend_flag = 0;
3684         setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw);
3685         timer.expires = jiffies + timeout;
3686
3687         if (write_len && write_data) {
3688                 hdw->cmd_debug_state = 2;
3689                 /* Transfer write data to internal buffer */
3690                 for (idx = 0; idx < write_len; idx++) {
3691                         hdw->ctl_write_buffer[idx] =
3692                                 ((unsigned char *)write_data)[idx];
3693                 }
3694                 /* Initiate a write request */
3695                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3696                                   hdw->usb_dev,
3697                                   usb_sndbulkpipe(hdw->usb_dev,
3698                                                   PVR2_CTL_WRITE_ENDPOINT),
3699                                   hdw->ctl_write_buffer,
3700                                   write_len,
3701                                   pvr2_ctl_write_complete,
3702                                   hdw);
3703                 hdw->ctl_write_urb->actual_length = 0;
3704                 hdw->ctl_write_pend_flag = !0;
3705                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3706                 if (status < 0) {
3707                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3708                                    "Failed to submit write-control"
3709                                    " URB status=%d",status);
3710                         hdw->ctl_write_pend_flag = 0;
3711                         goto done;
3712                 }
3713         }
3714
3715         if (read_len) {
3716                 hdw->cmd_debug_state = 3;
3717                 memset(hdw->ctl_read_buffer,0x43,read_len);
3718                 /* Initiate a read request */
3719                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3720                                   hdw->usb_dev,
3721                                   usb_rcvbulkpipe(hdw->usb_dev,
3722                                                   PVR2_CTL_READ_ENDPOINT),
3723                                   hdw->ctl_read_buffer,
3724                                   read_len,
3725                                   pvr2_ctl_read_complete,
3726                                   hdw);
3727                 hdw->ctl_read_urb->actual_length = 0;
3728                 hdw->ctl_read_pend_flag = !0;
3729                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3730                 if (status < 0) {
3731                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3732                                    "Failed to submit read-control"
3733                                    " URB status=%d",status);
3734                         hdw->ctl_read_pend_flag = 0;
3735                         goto done;
3736                 }
3737         }
3738
3739         /* Start timer */
3740         add_timer(&timer);
3741
3742         /* Now wait for all I/O to complete */
3743         hdw->cmd_debug_state = 4;
3744         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3745                 wait_for_completion(&hdw->ctl_done);
3746         }
3747         hdw->cmd_debug_state = 5;
3748
3749         /* Stop timer */
3750         del_timer_sync(&timer);
3751
3752         hdw->cmd_debug_state = 6;
3753         status = 0;
3754
3755         if (hdw->ctl_timeout_flag) {
3756                 status = -ETIMEDOUT;
3757                 if (!probe_fl) {
3758                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3759                                    "Timed out control-write");
3760                 }
3761                 goto done;
3762         }
3763
3764         if (write_len) {
3765                 /* Validate results of write request */
3766                 if ((hdw->ctl_write_urb->status != 0) &&
3767                     (hdw->ctl_write_urb->status != -ENOENT) &&
3768                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3769                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3770                         /* USB subsystem is reporting some kind of failure
3771                            on the write */
3772                         status = hdw->ctl_write_urb->status;
3773                         if (!probe_fl) {
3774                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3775                                            "control-write URB failure,"
3776                                            " status=%d",
3777                                            status);
3778                         }
3779                         goto done;
3780                 }
3781                 if (hdw->ctl_write_urb->actual_length < write_len) {
3782                         /* Failed to write enough data */
3783                         status = -EIO;
3784                         if (!probe_fl) {
3785                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3786                                            "control-write URB short,"
3787                                            " expected=%d got=%d",
3788                                            write_len,
3789                                            hdw->ctl_write_urb->actual_length);
3790                         }
3791                         goto done;
3792                 }
3793         }
3794         if (read_len && read_data) {
3795                 /* Validate results of read request */
3796                 if ((hdw->ctl_read_urb->status != 0) &&
3797                     (hdw->ctl_read_urb->status != -ENOENT) &&
3798                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3799                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3800                         /* USB subsystem is reporting some kind of failure
3801                            on the read */
3802                         status = hdw->ctl_read_urb->status;
3803                         if (!probe_fl) {
3804                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3805                                            "control-read URB failure,"
3806                                            " status=%d",
3807                                            status);
3808                         }
3809                         goto done;
3810                 }
3811                 if (hdw->ctl_read_urb->actual_length < read_len) {
3812                         /* Failed to read enough data */
3813                         status = -EIO;
3814                         if (!probe_fl) {
3815                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3816                                            "control-read URB short,"
3817                                            " expected=%d got=%d",
3818                                            read_len,
3819                                            hdw->ctl_read_urb->actual_length);
3820                         }
3821                         goto done;
3822                 }
3823                 /* Transfer retrieved data out from internal buffer */
3824                 for (idx = 0; idx < read_len; idx++) {
3825                         ((unsigned char *)read_data)[idx] =
3826                                 hdw->ctl_read_buffer[idx];
3827                 }
3828         }
3829
3830  done:
3831
3832         hdw->cmd_debug_state = 0;
3833         if ((status < 0) && (!probe_fl)) {
3834                 pvr2_hdw_render_useless(hdw);
3835         }
3836         return status;
3837 }
3838
3839
3840 int pvr2_send_request(struct pvr2_hdw *hdw,
3841                       void *write_data,unsigned int write_len,
3842                       void *read_data,unsigned int read_len)
3843 {
3844         return pvr2_send_request_ex(hdw,HZ*4,0,
3845                                     write_data,write_len,
3846                                     read_data,read_len);
3847 }
3848
3849
3850 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3851 {
3852         int ret;
3853         unsigned int cnt = 1;
3854         unsigned int args = 0;
3855         LOCK_TAKE(hdw->ctl_lock);
3856         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3857         args = (cmdcode >> 8) & 0xffu;
3858         args = (args > 2) ? 2 : args;
3859         if (args) {
3860                 cnt += args;
3861                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3862                 if (args > 1) {
3863                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3864                 }
3865         }
3866         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3867                 unsigned int idx;
3868                 unsigned int ccnt,bcnt;
3869                 char tbuf[50];
3870                 cmdcode &= 0xffu;
3871                 bcnt = 0;
3872                 ccnt = scnprintf(tbuf+bcnt,
3873                                  sizeof(tbuf)-bcnt,
3874                                  "Sending FX2 command 0x%x",cmdcode);
3875                 bcnt += ccnt;
3876                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3877                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3878                                 ccnt = scnprintf(tbuf+bcnt,
3879                                                  sizeof(tbuf)-bcnt,
3880                                                  " \"%s\"",
3881                                                  pvr2_fx2cmd_desc[idx].desc);
3882                                 bcnt += ccnt;
3883                                 break;
3884                         }
3885                 }
3886                 if (args) {
3887                         ccnt = scnprintf(tbuf+bcnt,
3888                                          sizeof(tbuf)-bcnt,
3889                                          " (%u",hdw->cmd_buffer[1]);
3890                         bcnt += ccnt;
3891                         if (args > 1) {
3892                                 ccnt = scnprintf(tbuf+bcnt,
3893                                                  sizeof(tbuf)-bcnt,
3894                                                  ",%u",hdw->cmd_buffer[2]);
3895                                 bcnt += ccnt;
3896                         }
3897                         ccnt = scnprintf(tbuf+bcnt,
3898                                          sizeof(tbuf)-bcnt,
3899                                          ")");
3900                         bcnt += ccnt;
3901                 }
3902                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3903         }
3904         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3905         LOCK_GIVE(hdw->ctl_lock);
3906         return ret;
3907 }
3908
3909
3910 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3911 {
3912         int ret;
3913
3914         LOCK_TAKE(hdw->ctl_lock);
3915
3916         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3917         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3918         hdw->cmd_buffer[5] = 0;
3919         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3920         hdw->cmd_buffer[7] = reg & 0xff;
3921
3922
3923         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3924
3925         LOCK_GIVE(hdw->ctl_lock);
3926
3927         return ret;
3928 }
3929
3930
3931 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3932 {
3933         int ret = 0;
3934
3935         LOCK_TAKE(hdw->ctl_lock);
3936
3937         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3938         hdw->cmd_buffer[1] = 0;
3939         hdw->cmd_buffer[2] = 0;
3940         hdw->cmd_buffer[3] = 0;
3941         hdw->cmd_buffer[4] = 0;
3942         hdw->cmd_buffer[5] = 0;
3943         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3944         hdw->cmd_buffer[7] = reg & 0xff;
3945
3946         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3947         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3948
3949         LOCK_GIVE(hdw->ctl_lock);
3950
3951         return ret;
3952 }
3953
3954
3955 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3956 {
3957         if (!hdw->flag_ok) return;
3958         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3959                    "Device being rendered inoperable");
3960         if (hdw->vid_stream) {
3961                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3962         }
3963         hdw->flag_ok = 0;
3964         trace_stbit("flag_ok",hdw->flag_ok);
3965         pvr2_hdw_state_sched(hdw);
3966 }
3967
3968
3969 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3970 {
3971         int ret;
3972         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3973         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3974         if (ret == 0) {
3975                 ret = usb_reset_device(hdw->usb_dev);
3976                 usb_unlock_device(hdw->usb_dev);
3977         } else {
3978                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3979                            "Failed to lock USB device ret=%d",ret);
3980         }
3981         if (init_pause_msec) {
3982                 pvr2_trace(PVR2_TRACE_INFO,
3983                            "Waiting %u msec for hardware to settle",
3984                            init_pause_msec);
3985                 msleep(init_pause_msec);
3986         }
3987
3988 }
3989
3990
3991 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3992 {
3993         char *da;
3994         unsigned int pipe;
3995         int ret;
3996
3997         if (!hdw->usb_dev) return;
3998
3999         da = kmalloc(16, GFP_KERNEL);
4000
4001         if (da == NULL) {
4002                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4003                            "Unable to allocate memory to control CPU reset");
4004                 return;
4005         }
4006
4007         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4008
4009         da[0] = val ? 0x01 : 0x00;
4010
4011         /* Write the CPUCS register on the 8051.  The lsb of the register
4012            is the reset bit; a 1 asserts reset while a 0 clears it. */
4013         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4014         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,1000);
4015         if (ret < 0) {
4016                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4017                            "cpureset_assert(%d) error=%d",val,ret);
4018                 pvr2_hdw_render_useless(hdw);
4019         }
4020
4021         kfree(da);
4022 }
4023
4024
4025 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4026 {
4027         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4028 }
4029
4030
4031 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4032 {
4033         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4034 }
4035
4036
4037
4038 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4039 {
4040         pvr2_trace(PVR2_TRACE_INIT,
4041                    "Requesting decoder reset");
4042         if (hdw->decoder_client_id) {
4043                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4044                                      core, reset, 0);
4045                 pvr2_hdw_cx25840_vbi_hack(hdw);
4046                 return 0;
4047         }
4048         pvr2_trace(PVR2_TRACE_INIT,
4049                    "Unable to reset decoder: nothing attached");
4050         return -ENOTTY;
4051 }
4052
4053
4054 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4055 {
4056         hdw->flag_ok = !0;
4057         return pvr2_issue_simple_cmd(hdw,
4058                                      FX2CMD_HCW_DEMOD_RESETIN |
4059                                      (1 << 8) |
4060                                      ((onoff ? 1 : 0) << 16));
4061 }
4062
4063
4064 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4065 {
4066         hdw->flag_ok = !0;
4067         return pvr2_issue_simple_cmd(hdw,(onoff ?
4068                                           FX2CMD_ONAIR_DTV_POWER_ON :
4069                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4070 }
4071
4072
4073 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4074                                                 int onoff)
4075 {
4076         return pvr2_issue_simple_cmd(hdw,(onoff ?
4077                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4078                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4079 }
4080
4081
4082 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4083 {
4084         int cmode;
4085         /* Compare digital/analog desired setting with current setting.  If
4086            they don't match, fix it... */
4087         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4088         if (cmode == hdw->pathway_state) {
4089                 /* They match; nothing to do */
4090                 return;
4091         }
4092
4093         switch (hdw->hdw_desc->digital_control_scheme) {
4094         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4095                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4096                 if (cmode == PVR2_PATHWAY_ANALOG) {
4097                         /* If moving to analog mode, also force the decoder
4098                            to reset.  If no decoder is attached, then it's
4099                            ok to ignore this because if/when the decoder
4100                            attaches, it will reset itself at that time. */
4101                         pvr2_hdw_cmd_decoder_reset(hdw);
4102                 }
4103                 break;
4104         case PVR2_DIGITAL_SCHEME_ONAIR:
4105                 /* Supposedly we should always have the power on whether in
4106                    digital or analog mode.  But for now do what appears to
4107                    work... */
4108                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4109                 break;
4110         default: break;
4111         }
4112
4113         pvr2_hdw_untrip_unlocked(hdw);
4114         hdw->pathway_state = cmode;
4115 }
4116
4117
4118 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4119 {
4120         /* change some GPIO data
4121          *
4122          * note: bit d7 of dir appears to control the LED,
4123          * so we shut it off here.
4124          *
4125          */
4126         if (onoff) {
4127                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4128         } else {
4129                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4130         }
4131         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4132 }
4133
4134
4135 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4136
4137 static led_method_func led_methods[] = {
4138         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4139 };
4140
4141
4142 /* Toggle LED */
4143 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4144 {
4145         unsigned int scheme_id;
4146         led_method_func fp;
4147
4148         if ((!onoff) == (!hdw->led_on)) return;
4149
4150         hdw->led_on = onoff != 0;
4151
4152         scheme_id = hdw->hdw_desc->led_scheme;
4153         if (scheme_id < ARRAY_SIZE(led_methods)) {
4154                 fp = led_methods[scheme_id];
4155         } else {
4156                 fp = NULL;
4157         }
4158
4159         if (fp) (*fp)(hdw,onoff);
4160 }
4161
4162
4163 /* Stop / start video stream transport */
4164 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4165 {
4166         int ret;
4167
4168         /* If we're in analog mode, then just issue the usual analog
4169            command. */
4170         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4171                 return pvr2_issue_simple_cmd(hdw,
4172                                              (runFl ?
4173                                               FX2CMD_STREAMING_ON :
4174                                               FX2CMD_STREAMING_OFF));
4175                 /*Note: Not reached */
4176         }
4177
4178         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4179                 /* Whoops, we don't know what mode we're in... */
4180                 return -EINVAL;
4181         }
4182
4183         /* To get here we have to be in digital mode.  The mechanism here
4184            is unfortunately different for different vendors.  So we switch
4185            on the device's digital scheme attribute in order to figure out
4186            what to do. */
4187         switch (hdw->hdw_desc->digital_control_scheme) {
4188         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4189                 return pvr2_issue_simple_cmd(hdw,
4190                                              (runFl ?
4191                                               FX2CMD_HCW_DTV_STREAMING_ON :
4192                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4193         case PVR2_DIGITAL_SCHEME_ONAIR:
4194                 ret = pvr2_issue_simple_cmd(hdw,
4195                                             (runFl ?
4196                                              FX2CMD_STREAMING_ON :
4197                                              FX2CMD_STREAMING_OFF));
4198                 if (ret) return ret;
4199                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4200         default:
4201                 return -EINVAL;
4202         }
4203 }
4204
4205
4206 /* Evaluate whether or not state_pathway_ok can change */
4207 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4208 {
4209         if (hdw->state_pathway_ok) {
4210                 /* Nothing to do if pathway is already ok */
4211                 return 0;
4212         }
4213         if (!hdw->state_pipeline_idle) {
4214                 /* Not allowed to change anything if pipeline is not idle */
4215                 return 0;
4216         }
4217         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4218         hdw->state_pathway_ok = !0;
4219         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4220         return !0;
4221 }
4222
4223
4224 /* Evaluate whether or not state_encoder_ok can change */
4225 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4226 {
4227         if (hdw->state_encoder_ok) return 0;
4228         if (hdw->flag_tripped) return 0;
4229         if (hdw->state_encoder_run) return 0;
4230         if (hdw->state_encoder_config) return 0;
4231         if (hdw->state_decoder_run) return 0;
4232         if (hdw->state_usbstream_run) return 0;
4233         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4234                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4235         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4236                 return 0;
4237         }
4238
4239         if (pvr2_upload_firmware2(hdw) < 0) {
4240                 hdw->flag_tripped = !0;
4241                 trace_stbit("flag_tripped",hdw->flag_tripped);
4242                 return !0;
4243         }
4244         hdw->state_encoder_ok = !0;
4245         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4246         return !0;
4247 }
4248
4249
4250 /* Evaluate whether or not state_encoder_config can change */
4251 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4252 {
4253         if (hdw->state_encoder_config) {
4254                 if (hdw->state_encoder_ok) {
4255                         if (hdw->state_pipeline_req &&
4256                             !hdw->state_pipeline_pause) return 0;
4257                 }
4258                 hdw->state_encoder_config = 0;
4259                 hdw->state_encoder_waitok = 0;
4260                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4261                 /* paranoia - solve race if timer just completed */
4262                 del_timer_sync(&hdw->encoder_wait_timer);
4263         } else {
4264                 if (!hdw->state_pathway_ok ||
4265                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4266                     !hdw->state_encoder_ok ||
4267                     !hdw->state_pipeline_idle ||
4268                     hdw->state_pipeline_pause ||
4269                     !hdw->state_pipeline_req ||
4270                     !hdw->state_pipeline_config) {
4271                         /* We must reset the enforced wait interval if
4272                            anything has happened that might have disturbed
4273                            the encoder.  This should be a rare case. */
4274                         if (timer_pending(&hdw->encoder_wait_timer)) {
4275                                 del_timer_sync(&hdw->encoder_wait_timer);
4276                         }
4277                         if (hdw->state_encoder_waitok) {
4278                                 /* Must clear the state - therefore we did
4279                                    something to a state bit and must also
4280                                    return true. */
4281                                 hdw->state_encoder_waitok = 0;
4282                                 trace_stbit("state_encoder_waitok",
4283                                             hdw->state_encoder_waitok);
4284                                 return !0;
4285                         }
4286                         return 0;
4287                 }
4288                 if (!hdw->state_encoder_waitok) {
4289                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4290                                 /* waitok flag wasn't set and timer isn't
4291                                    running.  Check flag once more to avoid
4292                                    a race then start the timer.  This is
4293                                    the point when we measure out a minimal
4294                                    quiet interval before doing something to
4295                                    the encoder. */
4296                                 if (!hdw->state_encoder_waitok) {
4297                                         hdw->encoder_wait_timer.expires =
4298                                                 jiffies + msecs_to_jiffies(
4299                                                 TIME_MSEC_ENCODER_WAIT);
4300                                         add_timer(&hdw->encoder_wait_timer);
4301                                 }
4302                         }
4303                         /* We can't continue until we know we have been
4304                            quiet for the interval measured by this
4305                            timer. */
4306                         return 0;
4307                 }
4308                 pvr2_encoder_configure(hdw);
4309                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4310         }
4311         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4312         return !0;
4313 }
4314
4315
4316 /* Return true if the encoder should not be running. */
4317 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4318 {
4319         if (!hdw->state_encoder_ok) {
4320                 /* Encoder isn't healthy at the moment, so stop it. */
4321                 return !0;
4322         }
4323         if (!hdw->state_pathway_ok) {
4324                 /* Mode is not understood at the moment (i.e. it wants to
4325                    change), so encoder must be stopped. */
4326                 return !0;
4327         }
4328
4329         switch (hdw->pathway_state) {
4330         case PVR2_PATHWAY_ANALOG:
4331                 if (!hdw->state_decoder_run) {
4332                         /* We're in analog mode and the decoder is not
4333                            running; thus the encoder should be stopped as
4334                            well. */
4335                         return !0;
4336                 }
4337                 break;
4338         case PVR2_PATHWAY_DIGITAL:
4339                 if (hdw->state_encoder_runok) {
4340                         /* This is a funny case.  We're in digital mode so
4341                            really the encoder should be stopped.  However
4342                            if it really is running, only kill it after
4343                            runok has been set.  This gives a chance for the
4344                            onair quirk to function (encoder must run
4345                            briefly first, at least once, before onair
4346                            digital streaming can work). */
4347                         return !0;
4348                 }
4349                 break;
4350         default:
4351                 /* Unknown mode; so encoder should be stopped. */
4352                 return !0;
4353         }
4354
4355         /* If we get here, we haven't found a reason to stop the
4356            encoder. */
4357         return 0;
4358 }
4359
4360
4361 /* Return true if the encoder should be running. */
4362 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4363 {
4364         if (!hdw->state_encoder_ok) {
4365                 /* Don't run the encoder if it isn't healthy... */
4366                 return 0;
4367         }
4368         if (!hdw->state_pathway_ok) {
4369                 /* Don't run the encoder if we don't (yet) know what mode
4370                    we need to be in... */
4371                 return 0;
4372         }
4373
4374         switch (hdw->pathway_state) {
4375         case PVR2_PATHWAY_ANALOG:
4376                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4377                         /* In analog mode, if the decoder is running, then
4378                            run the encoder. */
4379                         return !0;
4380                 }
4381                 break;
4382         case PVR2_PATHWAY_DIGITAL:
4383                 if ((hdw->hdw_desc->digital_control_scheme ==
4384                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4385                     !hdw->state_encoder_runok) {
4386                         /* This is a quirk.  OnAir hardware won't stream
4387                            digital until the encoder has been run at least
4388                            once, for a minimal period of time (empiricially
4389                            measured to be 1/4 second).  So if we're on
4390                            OnAir hardware and the encoder has never been
4391                            run at all, then start the encoder.  Normal
4392                            state machine logic in the driver will
4393                            automatically handle the remaining bits. */
4394                         return !0;
4395                 }
4396                 break;
4397         default:
4398                 /* For completeness (unknown mode; encoder won't run ever) */
4399                 break;
4400         }
4401         /* If we get here, then we haven't found any reason to run the
4402            encoder, so don't run it. */
4403         return 0;
4404 }
4405
4406
4407 /* Evaluate whether or not state_encoder_run can change */
4408 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4409 {
4410         if (hdw->state_encoder_run) {
4411                 if (!state_check_disable_encoder_run(hdw)) return 0;
4412                 if (hdw->state_encoder_ok) {
4413                         del_timer_sync(&hdw->encoder_run_timer);
4414                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4415                 }
4416                 hdw->state_encoder_run = 0;
4417         } else {
4418                 if (!state_check_enable_encoder_run(hdw)) return 0;
4419                 if (pvr2_encoder_start(hdw) < 0) return !0;
4420                 hdw->state_encoder_run = !0;
4421                 if (!hdw->state_encoder_runok) {
4422                         hdw->encoder_run_timer.expires = jiffies +
4423                                  msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4424                         add_timer(&hdw->encoder_run_timer);
4425                 }
4426         }
4427         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4428         return !0;
4429 }
4430
4431
4432 /* Timeout function for quiescent timer. */
4433 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4434 {
4435         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4436         hdw->state_decoder_quiescent = !0;
4437         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4438         hdw->state_stale = !0;
4439         schedule_work(&hdw->workpoll);
4440 }
4441
4442
4443 /* Timeout function for decoder stabilization timer. */
4444 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4445 {
4446         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4447         hdw->state_decoder_ready = !0;
4448         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4449         hdw->state_stale = !0;
4450         schedule_work(&hdw->workpoll);
4451 }
4452
4453
4454 /* Timeout function for encoder wait timer. */
4455 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4456 {
4457         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4458         hdw->state_encoder_waitok = !0;
4459         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4460         hdw->state_stale = !0;
4461         schedule_work(&hdw->workpoll);
4462 }
4463
4464
4465 /* Timeout function for encoder run timer. */
4466 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4467 {
4468         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4469         if (!hdw->state_encoder_runok) {
4470                 hdw->state_encoder_runok = !0;
4471                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4472                 hdw->state_stale = !0;
4473                 schedule_work(&hdw->workpoll);
4474         }
4475 }
4476
4477
4478 /* Evaluate whether or not state_decoder_run can change */
4479 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4480 {
4481         if (hdw->state_decoder_run) {
4482                 if (hdw->state_encoder_ok) {
4483                         if (hdw->state_pipeline_req &&
4484                             !hdw->state_pipeline_pause &&
4485                             hdw->state_pathway_ok) return 0;
4486                 }
4487                 if (!hdw->flag_decoder_missed) {
4488                         pvr2_decoder_enable(hdw,0);
4489                 }
4490                 hdw->state_decoder_quiescent = 0;
4491                 hdw->state_decoder_run = 0;
4492                 /* paranoia - solve race if timer(s) just completed */
4493                 del_timer_sync(&hdw->quiescent_timer);
4494                 /* Kill the stabilization timer, in case we're killing the
4495                    encoder before the previous stabilization interval has
4496                    been properly timed. */
4497                 del_timer_sync(&hdw->decoder_stabilization_timer);
4498                 hdw->state_decoder_ready = 0;
4499         } else {
4500                 if (!hdw->state_decoder_quiescent) {
4501                         if (!timer_pending(&hdw->quiescent_timer)) {
4502                                 /* We don't do something about the
4503                                    quiescent timer until right here because
4504                                    we also want to catch cases where the
4505                                    decoder was already not running (like
4506                                    after initialization) as opposed to
4507                                    knowing that we had just stopped it.
4508                                    The second flag check is here to cover a
4509                                    race - the timer could have run and set
4510                                    this flag just after the previous check
4511                                    but before we did the pending check. */
4512                                 if (!hdw->state_decoder_quiescent) {
4513                                         hdw->quiescent_timer.expires =
4514                                                 jiffies + msecs_to_jiffies(
4515                                                 TIME_MSEC_DECODER_WAIT);
4516                                         add_timer(&hdw->quiescent_timer);
4517                                 }
4518                         }
4519                         /* Don't allow decoder to start again until it has
4520                            been quiesced first.  This little detail should
4521                            hopefully further stabilize the encoder. */
4522                         return 0;
4523                 }
4524                 if (!hdw->state_pathway_ok ||
4525                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4526                     !hdw->state_pipeline_req ||
4527                     hdw->state_pipeline_pause ||
4528                     !hdw->state_pipeline_config ||
4529                     !hdw->state_encoder_config ||
4530                     !hdw->state_encoder_ok) return 0;
4531                 del_timer_sync(&hdw->quiescent_timer);
4532                 if (hdw->flag_decoder_missed) return 0;
4533                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4534                 hdw->state_decoder_quiescent = 0;
4535                 hdw->state_decoder_ready = 0;
4536                 hdw->state_decoder_run = !0;
4537                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4538                         hdw->decoder_stabilization_timer.expires =
4539                                 jiffies + msecs_to_jiffies(
4540                                 TIME_MSEC_DECODER_STABILIZATION_WAIT);
4541                         add_timer(&hdw->decoder_stabilization_timer);
4542                 } else {
4543                         hdw->state_decoder_ready = !0;
4544                 }
4545         }
4546         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4547         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4548         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4549         return !0;
4550 }
4551
4552
4553 /* Evaluate whether or not state_usbstream_run can change */
4554 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4555 {
4556         if (hdw->state_usbstream_run) {
4557                 int fl = !0;
4558                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4559                         fl = (hdw->state_encoder_ok &&
4560                               hdw->state_encoder_run);
4561                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4562                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4563                         fl = hdw->state_encoder_ok;
4564                 }
4565                 if (fl &&
4566                     hdw->state_pipeline_req &&
4567                     !hdw->state_pipeline_pause &&
4568                     hdw->state_pathway_ok) {
4569                         return 0;
4570                 }
4571                 pvr2_hdw_cmd_usbstream(hdw,0);
4572                 hdw->state_usbstream_run = 0;
4573         } else {
4574                 if (!hdw->state_pipeline_req ||
4575                     hdw->state_pipeline_pause ||
4576                     !hdw->state_pathway_ok) return 0;
4577                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4578                         if (!hdw->state_encoder_ok ||
4579                             !hdw->state_encoder_run) return 0;
4580                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4581                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4582                         if (!hdw->state_encoder_ok) return 0;
4583                         if (hdw->state_encoder_run) return 0;
4584                         if (hdw->hdw_desc->digital_control_scheme ==
4585                             PVR2_DIGITAL_SCHEME_ONAIR) {
4586                                 /* OnAir digital receivers won't stream
4587                                    unless the analog encoder has run first.
4588                                    Why?  I have no idea.  But don't even
4589                                    try until we know the analog side is
4590                                    known to have run. */
4591                                 if (!hdw->state_encoder_runok) return 0;
4592                         }
4593                 }
4594                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4595                 hdw->state_usbstream_run = !0;
4596         }
4597         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4598         return !0;
4599 }
4600
4601
4602 /* Attempt to configure pipeline, if needed */
4603 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4604 {
4605         if (hdw->state_pipeline_config ||
4606             hdw->state_pipeline_pause) return 0;
4607         pvr2_hdw_commit_execute(hdw);
4608         return !0;
4609 }
4610
4611
4612 /* Update pipeline idle and pipeline pause tracking states based on other
4613    inputs.  This must be called whenever the other relevant inputs have
4614    changed. */
4615 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4616 {
4617         unsigned int st;
4618         int updatedFl = 0;
4619         /* Update pipeline state */
4620         st = !(hdw->state_encoder_run ||
4621                hdw->state_decoder_run ||
4622                hdw->state_usbstream_run ||
4623                (!hdw->state_decoder_quiescent));
4624         if (!st != !hdw->state_pipeline_idle) {
4625                 hdw->state_pipeline_idle = st;
4626                 updatedFl = !0;
4627         }
4628         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4629                 hdw->state_pipeline_pause = 0;
4630                 updatedFl = !0;
4631         }
4632         return updatedFl;
4633 }
4634
4635
4636 typedef int (*state_eval_func)(struct pvr2_hdw *);
4637
4638 /* Set of functions to be run to evaluate various states in the driver. */
4639 static const state_eval_func eval_funcs[] = {
4640         state_eval_pathway_ok,
4641         state_eval_pipeline_config,
4642         state_eval_encoder_ok,
4643         state_eval_encoder_config,
4644         state_eval_decoder_run,
4645         state_eval_encoder_run,
4646         state_eval_usbstream_run,
4647 };
4648
4649
4650 /* Process various states and return true if we did anything interesting. */
4651 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4652 {
4653         unsigned int i;
4654         int state_updated = 0;
4655         int check_flag;
4656
4657         if (!hdw->state_stale) return 0;
4658         if ((hdw->fw1_state != FW1_STATE_OK) ||
4659             !hdw->flag_ok) {
4660                 hdw->state_stale = 0;
4661                 return !0;
4662         }
4663         /* This loop is the heart of the entire driver.  It keeps trying to
4664            evaluate various bits of driver state until nothing changes for
4665            one full iteration.  Each "bit of state" tracks some global
4666            aspect of the driver, e.g. whether decoder should run, if
4667            pipeline is configured, usb streaming is on, etc.  We separately
4668            evaluate each of those questions based on other driver state to
4669            arrive at the correct running configuration. */
4670         do {
4671                 check_flag = 0;
4672                 state_update_pipeline_state(hdw);
4673                 /* Iterate over each bit of state */
4674                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4675                         if ((*eval_funcs[i])(hdw)) {
4676                                 check_flag = !0;
4677                                 state_updated = !0;
4678                                 state_update_pipeline_state(hdw);
4679                         }
4680                 }
4681         } while (check_flag && hdw->flag_ok);
4682         hdw->state_stale = 0;
4683         trace_stbit("state_stale",hdw->state_stale);
4684         return state_updated;
4685 }
4686
4687
4688 static unsigned int print_input_mask(unsigned int msk,
4689                                      char *buf,unsigned int acnt)
4690 {
4691         unsigned int idx,ccnt;
4692         unsigned int tcnt = 0;
4693         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4694                 if (!((1 << idx) & msk)) continue;
4695                 ccnt = scnprintf(buf+tcnt,
4696                                  acnt-tcnt,
4697                                  "%s%s",
4698                                  (tcnt ? ", " : ""),
4699                                  control_values_input[idx]);
4700                 tcnt += ccnt;
4701         }
4702         return tcnt;
4703 }
4704
4705
4706 static const char *pvr2_pathway_state_name(int id)
4707 {
4708         switch (id) {
4709         case PVR2_PATHWAY_ANALOG: return "analog";
4710         case PVR2_PATHWAY_DIGITAL: return "digital";
4711         default: return "unknown";
4712         }
4713 }
4714
4715
4716 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4717                                              char *buf,unsigned int acnt)
4718 {
4719         switch (which) {
4720         case 0:
4721                 return scnprintf(
4722                         buf,acnt,
4723                         "driver:%s%s%s%s%s <mode=%s>",
4724                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4725                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4726                         (hdw->flag_disconnected ? " <disconnected>" :
4727                          " <connected>"),
4728                         (hdw->flag_tripped ? " <tripped>" : ""),
4729                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4730                         pvr2_pathway_state_name(hdw->pathway_state));
4731
4732         case 1:
4733                 return scnprintf(
4734                         buf,acnt,
4735                         "pipeline:%s%s%s%s",
4736                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4737                         (hdw->state_pipeline_config ?
4738                          " <configok>" : " <stale>"),
4739                         (hdw->state_pipeline_req ? " <req>" : ""),
4740                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4741         case 2:
4742                 return scnprintf(
4743                         buf,acnt,
4744                         "worker:%s%s%s%s%s%s%s",
4745                         (hdw->state_decoder_run ?
4746                          (hdw->state_decoder_ready ?
4747                           "<decode:run>" : " <decode:start>") :
4748                          (hdw->state_decoder_quiescent ?
4749                           "" : " <decode:stop>")),
4750                         (hdw->state_decoder_quiescent ?
4751                          " <decode:quiescent>" : ""),
4752                         (hdw->state_encoder_ok ?
4753                          "" : " <encode:init>"),
4754                         (hdw->state_encoder_run ?
4755                          (hdw->state_encoder_runok ?
4756                           " <encode:run>" :
4757                           " <encode:firstrun>") :
4758                          (hdw->state_encoder_runok ?
4759                           " <encode:stop>" :
4760                           " <encode:virgin>")),
4761                         (hdw->state_encoder_config ?
4762                          " <encode:configok>" :
4763                          (hdw->state_encoder_waitok ?
4764                           "" : " <encode:waitok>")),
4765                         (hdw->state_usbstream_run ?
4766                          " <usb:run>" : " <usb:stop>"),
4767                         (hdw->state_pathway_ok ?
4768                          " <pathway:ok>" : ""));
4769         case 3:
4770                 return scnprintf(
4771                         buf,acnt,
4772                         "state: %s",
4773                         pvr2_get_state_name(hdw->master_state));
4774         case 4: {
4775                 unsigned int tcnt = 0;
4776                 unsigned int ccnt;
4777
4778                 ccnt = scnprintf(buf,
4779                                  acnt,
4780                                  "Hardware supported inputs: ");
4781                 tcnt += ccnt;
4782                 tcnt += print_input_mask(hdw->input_avail_mask,
4783                                          buf+tcnt,
4784                                          acnt-tcnt);
4785                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4786                         ccnt = scnprintf(buf+tcnt,
4787                                          acnt-tcnt,
4788                                          "; allowed inputs: ");
4789                         tcnt += ccnt;
4790                         tcnt += print_input_mask(hdw->input_allowed_mask,
4791                                                  buf+tcnt,
4792                                                  acnt-tcnt);
4793                 }
4794                 return tcnt;
4795         }
4796         case 5: {
4797                 struct pvr2_stream_stats stats;
4798                 if (!hdw->vid_stream) break;
4799                 pvr2_stream_get_stats(hdw->vid_stream,
4800                                       &stats,
4801                                       0);
4802                 return scnprintf(
4803                         buf,acnt,
4804                         "Bytes streamed=%u"
4805                         " URBs: queued=%u idle=%u ready=%u"
4806                         " processed=%u failed=%u",
4807                         stats.bytes_processed,
4808                         stats.buffers_in_queue,
4809                         stats.buffers_in_idle,
4810                         stats.buffers_in_ready,
4811                         stats.buffers_processed,
4812                         stats.buffers_failed);
4813         }
4814         case 6: {
4815                 unsigned int id = hdw->ir_scheme_active;
4816                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4817                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4818                                   "?" : ir_scheme_names[id]));
4819         }
4820         default: break;
4821         }
4822         return 0;
4823 }
4824
4825
4826 /* Generate report containing info about attached sub-devices and attached
4827    i2c clients, including an indication of which attached i2c clients are
4828    actually sub-devices. */
4829 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4830                                             char *buf, unsigned int acnt)
4831 {
4832         struct v4l2_subdev *sd;
4833         unsigned int tcnt = 0;
4834         unsigned int ccnt;
4835         struct i2c_client *client;
4836         const char *p;
4837         unsigned int id;
4838
4839         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4840         tcnt += ccnt;
4841         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4842                 id = sd->grp_id;
4843                 p = NULL;
4844                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4845                 if (p) {
4846                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4847                         tcnt += ccnt;
4848                 } else {
4849                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4850                                          "  (unknown id=%u):", id);
4851                         tcnt += ccnt;
4852                 }
4853                 client = v4l2_get_subdevdata(sd);
4854                 if (client) {
4855                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4856                                          " %s @ %02x\n", client->name,
4857                                          client->addr);
4858                         tcnt += ccnt;
4859                 } else {
4860                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4861                                          " no i2c client\n");
4862                         tcnt += ccnt;
4863                 }
4864         }
4865         return tcnt;
4866 }
4867
4868
4869 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4870                                    char *buf,unsigned int acnt)
4871 {
4872         unsigned int bcnt,ccnt,idx;
4873         bcnt = 0;
4874         LOCK_TAKE(hdw->big_lock);
4875         for (idx = 0; ; idx++) {
4876                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4877                 if (!ccnt) break;
4878                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4879                 if (!acnt) break;
4880                 buf[0] = '\n'; ccnt = 1;
4881                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4882         }
4883         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4884         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4885         LOCK_GIVE(hdw->big_lock);
4886         return bcnt;
4887 }
4888
4889
4890 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4891 {
4892         char buf[256];
4893         unsigned int idx, ccnt;
4894         unsigned int lcnt, ucnt;
4895
4896         for (idx = 0; ; idx++) {
4897                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4898                 if (!ccnt) break;
4899                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4900         }
4901         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4902         if (ccnt >= sizeof(buf))
4903                 ccnt = sizeof(buf);
4904
4905         ucnt = 0;
4906         while (ucnt < ccnt) {
4907                 lcnt = 0;
4908                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4909                         lcnt++;
4910                 }
4911                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4912                 ucnt += lcnt + 1;
4913         }
4914 }
4915
4916
4917 /* Evaluate and update the driver's current state, taking various actions
4918    as appropriate for the update. */
4919 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4920 {
4921         unsigned int st;
4922         int state_updated = 0;
4923         int callback_flag = 0;
4924         int analog_mode;
4925
4926         pvr2_trace(PVR2_TRACE_STBITS,
4927                    "Drive state check START");
4928         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4929                 pvr2_hdw_state_log_state(hdw);
4930         }
4931
4932         /* Process all state and get back over disposition */
4933         state_updated = pvr2_hdw_state_update(hdw);
4934
4935         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4936
4937         /* Update master state based upon all other states. */
4938         if (!hdw->flag_ok) {
4939                 st = PVR2_STATE_DEAD;
4940         } else if (hdw->fw1_state != FW1_STATE_OK) {
4941                 st = PVR2_STATE_COLD;
4942         } else if ((analog_mode ||
4943                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4944                    !hdw->state_encoder_ok) {
4945                 st = PVR2_STATE_WARM;
4946         } else if (hdw->flag_tripped ||
4947                    (analog_mode && hdw->flag_decoder_missed)) {
4948                 st = PVR2_STATE_ERROR;
4949         } else if (hdw->state_usbstream_run &&
4950                    (!analog_mode ||
4951                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4952                 st = PVR2_STATE_RUN;
4953         } else {
4954                 st = PVR2_STATE_READY;
4955         }
4956         if (hdw->master_state != st) {
4957                 pvr2_trace(PVR2_TRACE_STATE,
4958                            "Device state change from %s to %s",
4959                            pvr2_get_state_name(hdw->master_state),
4960                            pvr2_get_state_name(st));
4961                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4962                 hdw->master_state = st;
4963                 state_updated = !0;
4964                 callback_flag = !0;
4965         }
4966         if (state_updated) {
4967                 /* Trigger anyone waiting on any state changes here. */
4968                 wake_up(&hdw->state_wait_data);
4969         }
4970
4971         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4972                 pvr2_hdw_state_log_state(hdw);
4973         }
4974         pvr2_trace(PVR2_TRACE_STBITS,
4975                    "Drive state check DONE callback=%d",callback_flag);
4976
4977         return callback_flag;
4978 }
4979
4980
4981 /* Cause kernel thread to check / update driver state */
4982 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4983 {
4984         if (hdw->state_stale) return;
4985         hdw->state_stale = !0;
4986         trace_stbit("state_stale",hdw->state_stale);
4987         schedule_work(&hdw->workpoll);
4988 }
4989
4990
4991 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4992 {
4993         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4994 }
4995
4996
4997 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4998 {
4999         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5000 }
5001
5002
5003 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5004 {
5005         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5006 }
5007
5008
5009 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5010 {
5011         u32 cval,nval;
5012         int ret;
5013         if (~msk) {
5014                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5015                 if (ret) return ret;
5016                 nval = (cval & ~msk) | (val & msk);
5017                 pvr2_trace(PVR2_TRACE_GPIO,
5018                            "GPIO direction changing 0x%x:0x%x"
5019                            " from 0x%x to 0x%x",
5020                            msk,val,cval,nval);
5021         } else {
5022                 nval = val;
5023                 pvr2_trace(PVR2_TRACE_GPIO,
5024                            "GPIO direction changing to 0x%x",nval);
5025         }
5026         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5027 }
5028
5029
5030 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5031 {
5032         u32 cval,nval;
5033         int ret;
5034         if (~msk) {
5035                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5036                 if (ret) return ret;
5037                 nval = (cval & ~msk) | (val & msk);
5038                 pvr2_trace(PVR2_TRACE_GPIO,
5039                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5040                            msk,val,cval,nval);
5041         } else {
5042                 nval = val;
5043                 pvr2_trace(PVR2_TRACE_GPIO,
5044                            "GPIO output changing to 0x%x",nval);
5045         }
5046         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5047 }
5048
5049
5050 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5051 {
5052         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5053         memset(vtp, 0, sizeof(*vtp));
5054         vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5055                 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5056         hdw->tuner_signal_stale = 0;
5057         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5058            using v4l2-subdev - therefore we can't support that AT ALL right
5059            now.  (Of course, no sub-drivers seem to implement it either.
5060            But now it's a a chicken and egg problem...) */
5061         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5062         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5063                    " type=%u strength=%u audio=0x%x cap=0x%x"
5064                    " low=%u hi=%u",
5065                    vtp->type,
5066                    vtp->signal, vtp->rxsubchans, vtp->capability,
5067                    vtp->rangelow, vtp->rangehigh);
5068
5069         /* We have to do this to avoid getting into constant polling if
5070            there's nobody to answer a poll of cropcap info. */
5071         hdw->cropcap_stale = 0;
5072 }
5073
5074
5075 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5076 {
5077         return hdw->input_avail_mask;
5078 }
5079
5080
5081 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5082 {
5083         return hdw->input_allowed_mask;
5084 }
5085
5086
5087 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5088 {
5089         if (hdw->input_val != v) {
5090                 hdw->input_val = v;
5091                 hdw->input_dirty = !0;
5092         }
5093
5094         /* Handle side effects - if we switch to a mode that needs the RF
5095            tuner, then select the right frequency choice as well and mark
5096            it dirty. */
5097         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5098                 hdw->freqSelector = 0;
5099                 hdw->freqDirty = !0;
5100         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5101                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5102                 hdw->freqSelector = 1;
5103                 hdw->freqDirty = !0;
5104         }
5105         return 0;
5106 }
5107
5108
5109 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5110                                unsigned int change_mask,
5111                                unsigned int change_val)
5112 {
5113         int ret = 0;
5114         unsigned int nv,m,idx;
5115         LOCK_TAKE(hdw->big_lock);
5116         do {
5117                 nv = hdw->input_allowed_mask & ~change_mask;
5118                 nv |= (change_val & change_mask);
5119                 nv &= hdw->input_avail_mask;
5120                 if (!nv) {
5121                         /* No legal modes left; return error instead. */
5122                         ret = -EPERM;
5123                         break;
5124                 }
5125                 hdw->input_allowed_mask = nv;
5126                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5127                         /* Current mode is still in the allowed mask, so
5128                            we're done. */
5129                         break;
5130                 }
5131                 /* Select and switch to a mode that is still in the allowed
5132                    mask */
5133                 if (!hdw->input_allowed_mask) {
5134                         /* Nothing legal; give up */
5135                         break;
5136                 }
5137                 m = hdw->input_allowed_mask;
5138                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5139                         if (!((1 << idx) & m)) continue;
5140                         pvr2_hdw_set_input(hdw,idx);
5141                         break;
5142                 }
5143         } while (0);
5144         LOCK_GIVE(hdw->big_lock);
5145         return ret;
5146 }
5147
5148
5149 /* Find I2C address of eeprom */
5150 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5151 {
5152         int result;
5153         LOCK_TAKE(hdw->ctl_lock); do {
5154                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5155                 result = pvr2_send_request(hdw,
5156                                            hdw->cmd_buffer,1,
5157                                            hdw->cmd_buffer,1);
5158                 if (result < 0) break;
5159                 result = hdw->cmd_buffer[0];
5160         } while(0); LOCK_GIVE(hdw->ctl_lock);
5161         return result;
5162 }