4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
28 #include <media/tuner.h>
30 #include "pvrusb2-std.h"
31 #include "pvrusb2-util.h"
32 #include "pvrusb2-hdw.h"
33 #include "pvrusb2-i2c-core.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
38 #include "pvrusb2-fx2-cmd.h"
39 #include "pvrusb2-wm8775.h"
40 #include "pvrusb2-video-v4l.h"
41 #include "pvrusb2-cx2584x-v4l.h"
42 #include "pvrusb2-cs53l32a.h"
43 #include "pvrusb2-audio.h"
45 #define TV_MIN_FREQ 55250000L
46 #define TV_MAX_FREQ 850000000L
48 /* This defines a minimum interval that the decoder must remain quiet
49 before we are allowed to start it running. */
50 #define TIME_MSEC_DECODER_WAIT 50
52 /* This defines a minimum interval that the decoder must be allowed to run
53 before we can safely begin using its streaming output. */
54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
56 /* This defines a minimum interval that the encoder must remain quiet
57 before we are allowed to configure it. */
58 #define TIME_MSEC_ENCODER_WAIT 50
60 /* This defines the minimum interval that the encoder must successfully run
61 before we consider that the encoder has run at least once since its
62 firmware has been loaded. This measurement is in important for cases
63 where we can't do something until we know that the encoder has been run
65 #define TIME_MSEC_ENCODER_OK 250
67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
68 static DEFINE_MUTEX(pvr2_unit_mtx);
71 static int procreload;
72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
75 static int init_pause_msec;
77 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
81 module_param(procreload, int, S_IRUGO|S_IWUSR);
82 MODULE_PARM_DESC(procreload,
83 "Attempt init failure recovery with firmware reload");
84 module_param_array(tuner, int, NULL, 0444);
85 MODULE_PARM_DESC(tuner,"specify installed tuner type");
86 module_param_array(video_std, int, NULL, 0444);
87 MODULE_PARM_DESC(video_std,"specify initial video standard");
88 module_param_array(tolerance, int, NULL, 0444);
89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
92 static int default_tv_freq = 61250000L;
93 /* 104.3 MHz, a usable FM station for my area */
94 static int default_radio_freq = 104300000L;
96 module_param_named(tv_freq, default_tv_freq, int, 0444);
97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
98 module_param_named(radio_freq, default_radio_freq, int, 0444);
99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
101 #define PVR2_CTL_WRITE_ENDPOINT 0x01
102 #define PVR2_CTL_READ_ENDPOINT 0x81
104 #define PVR2_GPIO_IN 0x9008
105 #define PVR2_GPIO_OUT 0x900c
106 #define PVR2_GPIO_DIR 0x9020
108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
110 #define PVR2_FIRMWARE_ENDPOINT 0x02
112 /* size of a firmware chunk */
113 #define FIRMWARE_CHUNK_SIZE 0x2000
115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
116 struct v4l2_subdev *);
118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
126 static const char *module_names[] = {
127 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
128 [PVR2_CLIENT_ID_CX25840] = "cx25840",
129 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
130 [PVR2_CLIENT_ID_TUNER] = "tuner",
131 [PVR2_CLIENT_ID_DEMOD] = "tuner",
132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
133 [PVR2_CLIENT_ID_WM8775] = "wm8775",
137 static const unsigned char *module_i2c_addresses[] = {
138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
139 [PVR2_CLIENT_ID_DEMOD] = "\x43",
140 [PVR2_CLIENT_ID_MSP3400] = "\x40",
141 [PVR2_CLIENT_ID_SAA7115] = "\x21",
142 [PVR2_CLIENT_ID_WM8775] = "\x1b",
143 [PVR2_CLIENT_ID_CX25840] = "\x44",
144 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
148 static const char *ir_scheme_names[] = {
149 [PVR2_IR_SCHEME_NONE] = "none",
150 [PVR2_IR_SCHEME_29XXX] = "29xxx",
151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
153 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
157 /* Define the list of additional controls we'll dynamically construct based
158 on query of the cx2341x module. */
159 struct pvr2_mpeg_ids {
163 static const struct pvr2_mpeg_ids mpeg_ids[] = {
165 .strid = "audio_layer",
166 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
168 .strid = "audio_bitrate",
169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
171 /* Already using audio_mode elsewhere :-( */
172 .strid = "mpeg_audio_mode",
173 .id = V4L2_CID_MPEG_AUDIO_MODE,
175 .strid = "mpeg_audio_mode_extension",
176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
178 .strid = "audio_emphasis",
179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
181 .strid = "audio_crc",
182 .id = V4L2_CID_MPEG_AUDIO_CRC,
184 .strid = "video_aspect",
185 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
187 .strid = "video_b_frames",
188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
190 .strid = "video_gop_size",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
193 .strid = "video_gop_closure",
194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
196 .strid = "video_bitrate_mode",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
199 .strid = "video_bitrate",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
202 .strid = "video_bitrate_peak",
203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
205 .strid = "video_temporal_decimation",
206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
208 .strid = "stream_type",
209 .id = V4L2_CID_MPEG_STREAM_TYPE,
211 .strid = "video_spatial_filter_mode",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
214 .strid = "video_spatial_filter",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
217 .strid = "video_luma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
220 .strid = "video_chroma_spatial_filter_type",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
223 .strid = "video_temporal_filter_mode",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
226 .strid = "video_temporal_filter",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
229 .strid = "video_median_filter_type",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
232 .strid = "video_luma_median_filter_top",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
235 .strid = "video_luma_median_filter_bottom",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
238 .strid = "video_chroma_median_filter_top",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
241 .strid = "video_chroma_median_filter_bottom",
242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
248 static const char *control_values_srate[] = {
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
256 static const char *control_values_input[] = {
257 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
258 [PVR2_CVAL_INPUT_DTV] = "dtv",
259 [PVR2_CVAL_INPUT_RADIO] = "radio",
260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
265 static const char *control_values_audiomode[] = {
266 [V4L2_TUNER_MODE_MONO] = "Mono",
267 [V4L2_TUNER_MODE_STEREO] = "Stereo",
268 [V4L2_TUNER_MODE_LANG1] = "Lang1",
269 [V4L2_TUNER_MODE_LANG2] = "Lang2",
270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
274 static const char *control_values_hsm[] = {
275 [PVR2_CVAL_HSM_FAIL] = "Fail",
276 [PVR2_CVAL_HSM_HIGH] = "High",
277 [PVR2_CVAL_HSM_FULL] = "Full",
281 static const char *pvr2_state_names[] = {
282 [PVR2_STATE_NONE] = "none",
283 [PVR2_STATE_DEAD] = "dead",
284 [PVR2_STATE_COLD] = "cold",
285 [PVR2_STATE_WARM] = "warm",
286 [PVR2_STATE_ERROR] = "error",
287 [PVR2_STATE_READY] = "ready",
288 [PVR2_STATE_RUN] = "run",
292 struct pvr2_fx2cmd_descdef {
297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
302 {FX2CMD_REG_WRITE, "write encoder register"},
303 {FX2CMD_REG_READ, "read encoder register"},
304 {FX2CMD_MEMSEL, "encoder memsel"},
305 {FX2CMD_I2C_WRITE, "i2c write"},
306 {FX2CMD_I2C_READ, "i2c read"},
307 {FX2CMD_GET_USB_SPEED, "get USB speed"},
308 {FX2CMD_STREAMING_ON, "stream on"},
309 {FX2CMD_STREAMING_OFF, "stream off"},
310 {FX2CMD_FWPOST1, "fwpost1"},
311 {FX2CMD_POWER_OFF, "power off"},
312 {FX2CMD_POWER_ON, "power on"},
313 {FX2CMD_DEEP_RESET, "deep reset"},
314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
315 {FX2CMD_GET_IR_CODE, "get IR code"},
316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
327 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
328 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
330 static void pvr2_hdw_worker_poll(struct work_struct *work);
331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
337 static void pvr2_hdw_quiescent_timeout(unsigned long);
338 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
339 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
340 static void pvr2_hdw_encoder_run_timeout(unsigned long);
341 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
342 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
343 unsigned int timeout,int probe_fl,
344 void *write_data,unsigned int write_len,
345 void *read_data,unsigned int read_len);
346 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
347 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
349 static void trace_stbit(const char *name,int val)
351 pvr2_trace(PVR2_TRACE_STBITS,
352 "State bit %s <-- %s",
353 name,(val ? "true" : "false"));
356 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
358 struct pvr2_hdw *hdw = cptr->hdw;
359 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
360 *vp = hdw->freqTable[hdw->freqProgSlot-1];
367 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
369 struct pvr2_hdw *hdw = cptr->hdw;
370 unsigned int slotId = hdw->freqProgSlot;
371 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
372 hdw->freqTable[slotId-1] = v;
373 /* Handle side effects correctly - if we're tuned to this
374 slot, then forgot the slot id relation since the stored
375 frequency has been changed. */
376 if (hdw->freqSelector) {
377 if (hdw->freqSlotRadio == slotId) {
378 hdw->freqSlotRadio = 0;
381 if (hdw->freqSlotTelevision == slotId) {
382 hdw->freqSlotTelevision = 0;
389 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
391 *vp = cptr->hdw->freqProgSlot;
395 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
397 struct pvr2_hdw *hdw = cptr->hdw;
398 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
399 hdw->freqProgSlot = v;
404 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
406 struct pvr2_hdw *hdw = cptr->hdw;
407 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
411 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
414 struct pvr2_hdw *hdw = cptr->hdw;
415 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
417 freq = hdw->freqTable[slotId-1];
419 pvr2_hdw_set_cur_freq(hdw,freq);
421 if (hdw->freqSelector) {
422 hdw->freqSlotRadio = slotId;
424 hdw->freqSlotTelevision = slotId;
429 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
431 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
435 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
437 return cptr->hdw->freqDirty != 0;
440 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
442 cptr->hdw->freqDirty = 0;
445 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
447 pvr2_hdw_set_cur_freq(cptr->hdw,v);
451 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
453 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
454 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
458 *left = cap->bounds.left;
462 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
464 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
465 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
469 *left = cap->bounds.left;
470 if (cap->bounds.width > cptr->hdw->cropw_val) {
471 *left += cap->bounds.width - cptr->hdw->cropw_val;
476 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
478 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
479 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
483 *top = cap->bounds.top;
487 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
489 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
490 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
494 *top = cap->bounds.top;
495 if (cap->bounds.height > cptr->hdw->croph_val) {
496 *top += cap->bounds.height - cptr->hdw->croph_val;
501 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
503 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
504 int stat, bleftend, cleft;
506 stat = pvr2_hdw_check_cropcap(cptr->hdw);
510 bleftend = cap->bounds.left+cap->bounds.width;
511 cleft = cptr->hdw->cropl_val;
513 *width = cleft < bleftend ? bleftend-cleft : 0;
517 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
519 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
520 int stat, btopend, ctop;
522 stat = pvr2_hdw_check_cropcap(cptr->hdw);
526 btopend = cap->bounds.top+cap->bounds.height;
527 ctop = cptr->hdw->cropt_val;
529 *height = ctop < btopend ? btopend-ctop : 0;
533 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
535 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
536 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
540 *val = cap->bounds.left;
544 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
546 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
547 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
551 *val = cap->bounds.top;
555 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
557 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
558 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
562 *val = cap->bounds.width;
566 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
568 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
569 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
573 *val = cap->bounds.height;
577 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
579 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
580 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
584 *val = cap->defrect.left;
588 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
590 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
591 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
595 *val = cap->defrect.top;
599 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
601 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
602 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
606 *val = cap->defrect.width;
610 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
612 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
613 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
617 *val = cap->defrect.height;
621 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
623 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
624 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
628 *val = cap->pixelaspect.numerator;
632 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
634 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
635 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
639 *val = cap->pixelaspect.denominator;
643 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
645 /* Actual maximum depends on the video standard in effect. */
646 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
654 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
656 /* Actual minimum depends on device digitizer type. */
657 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
665 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
667 *vp = cptr->hdw->input_val;
671 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
673 if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
675 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
678 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
680 return pvr2_hdw_set_input(cptr->hdw,v);
683 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
685 return cptr->hdw->input_dirty != 0;
688 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
690 cptr->hdw->input_dirty = 0;
694 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
697 struct pvr2_hdw *hdw = cptr->hdw;
698 if (hdw->tuner_signal_stale) {
699 pvr2_hdw_status_poll(hdw);
701 fv = hdw->tuner_signal_info.rangehigh;
703 /* Safety fallback */
707 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
716 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
719 struct pvr2_hdw *hdw = cptr->hdw;
720 if (hdw->tuner_signal_stale) {
721 pvr2_hdw_status_poll(hdw);
723 fv = hdw->tuner_signal_info.rangelow;
725 /* Safety fallback */
729 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
738 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
740 return cptr->hdw->enc_stale != 0;
743 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
745 cptr->hdw->enc_stale = 0;
746 cptr->hdw->enc_unsafe_stale = 0;
749 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
752 struct v4l2_ext_controls cs;
753 struct v4l2_ext_control c1;
754 memset(&cs,0,sizeof(cs));
755 memset(&c1,0,sizeof(c1));
758 c1.id = cptr->info->v4l_id;
759 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
766 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
769 struct pvr2_hdw *hdw = cptr->hdw;
770 struct v4l2_ext_controls cs;
771 struct v4l2_ext_control c1;
772 memset(&cs,0,sizeof(cs));
773 memset(&c1,0,sizeof(c1));
776 c1.id = cptr->info->v4l_id;
778 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
779 hdw->state_encoder_run, &cs,
782 /* Oops. cx2341x is telling us it's not safe to change
783 this control while we're capturing. Make a note of this
784 fact so that the pipeline will be stopped the next time
785 controls are committed. Then go on ahead and store this
787 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
790 if (!ret) hdw->enc_unsafe_stale = !0;
797 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
799 struct v4l2_queryctrl qctrl;
800 struct pvr2_ctl_info *info;
801 qctrl.id = cptr->info->v4l_id;
802 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
803 /* Strip out the const so we can adjust a function pointer. It's
804 OK to do this here because we know this is a dynamically created
805 control, so the underlying storage for the info pointer is (a)
806 private to us, and (b) not in read-only storage. Either we do
807 this or we significantly complicate the underlying control
809 info = (struct pvr2_ctl_info *)(cptr->info);
810 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
811 if (info->set_value) {
812 info->set_value = NULL;
815 if (!(info->set_value)) {
816 info->set_value = ctrl_cx2341x_set;
822 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
824 *vp = cptr->hdw->state_pipeline_req;
828 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
830 *vp = cptr->hdw->master_state;
834 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
836 int result = pvr2_hdw_is_hsm(cptr->hdw);
837 *vp = PVR2_CVAL_HSM_FULL;
838 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
839 if (result) *vp = PVR2_CVAL_HSM_HIGH;
843 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
845 *vp = pvr2_hdw_get_detected_std(cptr->hdw);
849 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
851 *vp = cptr->hdw->std_mask_avail;
855 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
857 struct pvr2_hdw *hdw = cptr->hdw;
859 ns = hdw->std_mask_avail;
860 ns = (ns & ~m) | (v & m);
861 if (ns == hdw->std_mask_avail) return 0;
862 hdw->std_mask_avail = ns;
863 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
867 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
868 char *bufPtr,unsigned int bufSize,
871 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
875 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
876 const char *bufPtr,unsigned int bufSize,
881 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
882 if (ret < 0) return ret;
883 if (mskp) *mskp = id;
884 if (valp) *valp = id;
888 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
890 *vp = cptr->hdw->std_mask_cur;
894 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
896 struct pvr2_hdw *hdw = cptr->hdw;
898 ns = hdw->std_mask_cur;
899 ns = (ns & ~m) | (v & m);
900 if (ns == hdw->std_mask_cur) return 0;
901 hdw->std_mask_cur = ns;
906 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
908 return cptr->hdw->std_dirty != 0;
911 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
913 cptr->hdw->std_dirty = 0;
916 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
918 struct pvr2_hdw *hdw = cptr->hdw;
919 pvr2_hdw_status_poll(hdw);
920 *vp = hdw->tuner_signal_info.signal;
924 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
927 unsigned int subchan;
928 struct pvr2_hdw *hdw = cptr->hdw;
929 pvr2_hdw_status_poll(hdw);
930 subchan = hdw->tuner_signal_info.rxsubchans;
931 if (subchan & V4L2_TUNER_SUB_MONO) {
932 val |= (1 << V4L2_TUNER_MODE_MONO);
934 if (subchan & V4L2_TUNER_SUB_STEREO) {
935 val |= (1 << V4L2_TUNER_MODE_STEREO);
937 if (subchan & V4L2_TUNER_SUB_LANG1) {
938 val |= (1 << V4L2_TUNER_MODE_LANG1);
940 if (subchan & V4L2_TUNER_SUB_LANG2) {
941 val |= (1 << V4L2_TUNER_MODE_LANG2);
948 #define DEFINT(vmin,vmax) \
949 .type = pvr2_ctl_int, \
950 .def.type_int.min_value = vmin, \
951 .def.type_int.max_value = vmax
953 #define DEFENUM(tab) \
954 .type = pvr2_ctl_enum, \
955 .def.type_enum.count = ARRAY_SIZE(tab), \
956 .def.type_enum.value_names = tab
959 .type = pvr2_ctl_bool
961 #define DEFMASK(msk,tab) \
962 .type = pvr2_ctl_bitmask, \
963 .def.type_bitmask.valid_bits = msk, \
964 .def.type_bitmask.bit_names = tab
966 #define DEFREF(vname) \
967 .set_value = ctrl_set_##vname, \
968 .get_value = ctrl_get_##vname, \
969 .is_dirty = ctrl_isdirty_##vname, \
970 .clear_dirty = ctrl_cleardirty_##vname
973 #define VCREATE_FUNCS(vname) \
974 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
975 {*vp = cptr->hdw->vname##_val; return 0;} \
976 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
977 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
978 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
979 {return cptr->hdw->vname##_dirty != 0;} \
980 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
981 {cptr->hdw->vname##_dirty = 0;}
983 VCREATE_FUNCS(brightness)
984 VCREATE_FUNCS(contrast)
985 VCREATE_FUNCS(saturation)
987 VCREATE_FUNCS(volume)
988 VCREATE_FUNCS(balance)
990 VCREATE_FUNCS(treble)
996 VCREATE_FUNCS(audiomode)
997 VCREATE_FUNCS(res_hor)
998 VCREATE_FUNCS(res_ver)
1001 /* Table definition of all controls which can be manipulated */
1002 static const struct pvr2_ctl_info control_defs[] = {
1004 .v4l_id = V4L2_CID_BRIGHTNESS,
1005 .desc = "Brightness",
1006 .name = "brightness",
1007 .default_value = 128,
1011 .v4l_id = V4L2_CID_CONTRAST,
1014 .default_value = 68,
1018 .v4l_id = V4L2_CID_SATURATION,
1019 .desc = "Saturation",
1020 .name = "saturation",
1021 .default_value = 64,
1025 .v4l_id = V4L2_CID_HUE,
1032 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1035 .default_value = 62000,
1039 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1044 DEFINT(-32768,32767),
1046 .v4l_id = V4L2_CID_AUDIO_BASS,
1051 DEFINT(-32768,32767),
1053 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1058 DEFINT(-32768,32767),
1060 .v4l_id = V4L2_CID_AUDIO_MUTE,
1067 .desc = "Capture crop left margin",
1068 .name = "crop_left",
1069 .internal_id = PVR2_CID_CROPL,
1073 .get_min_value = ctrl_cropl_min_get,
1074 .get_max_value = ctrl_cropl_max_get,
1075 .get_def_value = ctrl_get_cropcapdl,
1077 .desc = "Capture crop top margin",
1079 .internal_id = PVR2_CID_CROPT,
1083 .get_min_value = ctrl_cropt_min_get,
1084 .get_max_value = ctrl_cropt_max_get,
1085 .get_def_value = ctrl_get_cropcapdt,
1087 .desc = "Capture crop width",
1088 .name = "crop_width",
1089 .internal_id = PVR2_CID_CROPW,
1090 .default_value = 720,
1093 .get_max_value = ctrl_cropw_max_get,
1094 .get_def_value = ctrl_get_cropcapdw,
1096 .desc = "Capture crop height",
1097 .name = "crop_height",
1098 .internal_id = PVR2_CID_CROPH,
1099 .default_value = 480,
1102 .get_max_value = ctrl_croph_max_get,
1103 .get_def_value = ctrl_get_cropcapdh,
1105 .desc = "Capture capability pixel aspect numerator",
1106 .name = "cropcap_pixel_numerator",
1107 .internal_id = PVR2_CID_CROPCAPPAN,
1108 .get_value = ctrl_get_cropcappan,
1110 .desc = "Capture capability pixel aspect denominator",
1111 .name = "cropcap_pixel_denominator",
1112 .internal_id = PVR2_CID_CROPCAPPAD,
1113 .get_value = ctrl_get_cropcappad,
1115 .desc = "Capture capability bounds top",
1116 .name = "cropcap_bounds_top",
1117 .internal_id = PVR2_CID_CROPCAPBT,
1118 .get_value = ctrl_get_cropcapbt,
1120 .desc = "Capture capability bounds left",
1121 .name = "cropcap_bounds_left",
1122 .internal_id = PVR2_CID_CROPCAPBL,
1123 .get_value = ctrl_get_cropcapbl,
1125 .desc = "Capture capability bounds width",
1126 .name = "cropcap_bounds_width",
1127 .internal_id = PVR2_CID_CROPCAPBW,
1128 .get_value = ctrl_get_cropcapbw,
1130 .desc = "Capture capability bounds height",
1131 .name = "cropcap_bounds_height",
1132 .internal_id = PVR2_CID_CROPCAPBH,
1133 .get_value = ctrl_get_cropcapbh,
1135 .desc = "Video Source",
1137 .internal_id = PVR2_CID_INPUT,
1138 .default_value = PVR2_CVAL_INPUT_TV,
1139 .check_value = ctrl_check_input,
1141 DEFENUM(control_values_input),
1143 .desc = "Audio Mode",
1144 .name = "audio_mode",
1145 .internal_id = PVR2_CID_AUDIOMODE,
1146 .default_value = V4L2_TUNER_MODE_STEREO,
1148 DEFENUM(control_values_audiomode),
1150 .desc = "Horizontal capture resolution",
1151 .name = "resolution_hor",
1152 .internal_id = PVR2_CID_HRES,
1153 .default_value = 720,
1157 .desc = "Vertical capture resolution",
1158 .name = "resolution_ver",
1159 .internal_id = PVR2_CID_VRES,
1160 .default_value = 480,
1163 /* Hook in check for video standard and adjust maximum
1164 depending on the standard. */
1165 .get_max_value = ctrl_vres_max_get,
1166 .get_min_value = ctrl_vres_min_get,
1168 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1169 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1170 .desc = "Audio Sampling Frequency",
1173 DEFENUM(control_values_srate),
1175 .desc = "Tuner Frequency (Hz)",
1176 .name = "frequency",
1177 .internal_id = PVR2_CID_FREQUENCY,
1179 .set_value = ctrl_freq_set,
1180 .get_value = ctrl_freq_get,
1181 .is_dirty = ctrl_freq_is_dirty,
1182 .clear_dirty = ctrl_freq_clear_dirty,
1184 /* Hook in check for input value (tv/radio) and adjust
1185 max/min values accordingly */
1186 .get_max_value = ctrl_freq_max_get,
1187 .get_min_value = ctrl_freq_min_get,
1191 .set_value = ctrl_channel_set,
1192 .get_value = ctrl_channel_get,
1193 DEFINT(0,FREQTABLE_SIZE),
1195 .desc = "Channel Program Frequency",
1196 .name = "freq_table_value",
1197 .set_value = ctrl_channelfreq_set,
1198 .get_value = ctrl_channelfreq_get,
1200 /* Hook in check for input value (tv/radio) and adjust
1201 max/min values accordingly */
1202 .get_max_value = ctrl_freq_max_get,
1203 .get_min_value = ctrl_freq_min_get,
1205 .desc = "Channel Program ID",
1206 .name = "freq_table_channel",
1207 .set_value = ctrl_channelprog_set,
1208 .get_value = ctrl_channelprog_get,
1209 DEFINT(0,FREQTABLE_SIZE),
1211 .desc = "Streaming Enabled",
1212 .name = "streaming_enabled",
1213 .get_value = ctrl_streamingenabled_get,
1216 .desc = "USB Speed",
1217 .name = "usb_speed",
1218 .get_value = ctrl_hsm_get,
1219 DEFENUM(control_values_hsm),
1221 .desc = "Master State",
1222 .name = "master_state",
1223 .get_value = ctrl_masterstate_get,
1224 DEFENUM(pvr2_state_names),
1226 .desc = "Signal Present",
1227 .name = "signal_present",
1228 .get_value = ctrl_signal_get,
1231 .desc = "Audio Modes Present",
1232 .name = "audio_modes_present",
1233 .get_value = ctrl_audio_modes_present_get,
1234 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1235 v4l. Nothing outside of this module cares about this,
1236 but I reuse it in order to also reuse the
1237 control_values_audiomode string table. */
1238 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1239 (1 << V4L2_TUNER_MODE_STEREO)|
1240 (1 << V4L2_TUNER_MODE_LANG1)|
1241 (1 << V4L2_TUNER_MODE_LANG2)),
1242 control_values_audiomode),
1244 .desc = "Video Standards Available Mask",
1245 .name = "video_standard_mask_available",
1246 .internal_id = PVR2_CID_STDAVAIL,
1248 .get_value = ctrl_stdavail_get,
1249 .set_value = ctrl_stdavail_set,
1250 .val_to_sym = ctrl_std_val_to_sym,
1251 .sym_to_val = ctrl_std_sym_to_val,
1252 .type = pvr2_ctl_bitmask,
1254 .desc = "Video Standards In Use Mask",
1255 .name = "video_standard_mask_active",
1256 .internal_id = PVR2_CID_STDCUR,
1258 .get_value = ctrl_stdcur_get,
1259 .set_value = ctrl_stdcur_set,
1260 .is_dirty = ctrl_stdcur_is_dirty,
1261 .clear_dirty = ctrl_stdcur_clear_dirty,
1262 .val_to_sym = ctrl_std_val_to_sym,
1263 .sym_to_val = ctrl_std_sym_to_val,
1264 .type = pvr2_ctl_bitmask,
1266 .desc = "Video Standards Detected Mask",
1267 .name = "video_standard_mask_detected",
1268 .internal_id = PVR2_CID_STDDETECT,
1270 .get_value = ctrl_stddetect_get,
1271 .val_to_sym = ctrl_std_val_to_sym,
1272 .sym_to_val = ctrl_std_sym_to_val,
1273 .type = pvr2_ctl_bitmask,
1277 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1280 const char *pvr2_config_get_name(enum pvr2_config cfg)
1283 case pvr2_config_empty: return "empty";
1284 case pvr2_config_mpeg: return "mpeg";
1285 case pvr2_config_vbi: return "vbi";
1286 case pvr2_config_pcm: return "pcm";
1287 case pvr2_config_rawvideo: return "raw video";
1293 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1295 return hdw->usb_dev;
1299 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1301 return hdw->serial_number;
1305 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1307 return hdw->bus_info;
1311 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1313 return hdw->identifier;
1317 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1319 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1322 /* Set the currently tuned frequency and account for all possible
1323 driver-core side effects of this action. */
1324 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1326 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1327 if (hdw->freqSelector) {
1328 /* Swing over to radio frequency selection */
1329 hdw->freqSelector = 0;
1330 hdw->freqDirty = !0;
1332 if (hdw->freqValRadio != val) {
1333 hdw->freqValRadio = val;
1334 hdw->freqSlotRadio = 0;
1335 hdw->freqDirty = !0;
1338 if (!(hdw->freqSelector)) {
1339 /* Swing over to television frequency selection */
1340 hdw->freqSelector = 1;
1341 hdw->freqDirty = !0;
1343 if (hdw->freqValTelevision != val) {
1344 hdw->freqValTelevision = val;
1345 hdw->freqSlotTelevision = 0;
1346 hdw->freqDirty = !0;
1351 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1353 return hdw->unit_number;
1357 /* Attempt to locate one of the given set of files. Messages are logged
1358 appropriate to what has been found. The return value will be 0 or
1359 greater on success (it will be the index of the file name found) and
1360 fw_entry will be filled in. Otherwise a negative error is returned on
1361 failure. If the return value is -ENOENT then no viable firmware file
1362 could be located. */
1363 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1364 const struct firmware **fw_entry,
1365 const char *fwtypename,
1366 unsigned int fwcount,
1367 const char *fwnames[])
1371 for (idx = 0; idx < fwcount; idx++) {
1372 ret = reject_firmware(fw_entry,
1374 &hdw->usb_dev->dev);
1376 trace_firmware("Located %s firmware: %s;"
1382 if (ret == -ENOENT) continue;
1383 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1384 "request_firmware fatal error with code=%d",ret);
1387 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1389 " Device %s firmware"
1390 " seems to be missing.",
1392 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1393 "Did you install the pvrusb2 firmware files"
1394 " in their proper location?");
1396 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1397 "request_firmware unable to locate %s file %s",
1398 fwtypename,fwnames[0]);
1400 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1401 "request_firmware unable to locate"
1402 " one of the following %s files:",
1404 for (idx = 0; idx < fwcount; idx++) {
1405 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1406 "reject_firmware: Failed to find %s",
1415 * pvr2_upload_firmware1().
1417 * Send the 8051 firmware to the device. After the upload, arrange for
1418 * device to re-enumerate.
1420 * NOTE : the pointer to the firmware data given by reject_firmware()
1421 * is not suitable for an usb transaction.
1424 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1426 const struct firmware *fw_entry = NULL;
1429 unsigned int fwsize;
1433 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1434 hdw->fw1_state = FW1_STATE_OK;
1435 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1436 "Connected device type defines"
1437 " no firmware to upload; ignoring firmware");
1441 hdw->fw1_state = FW1_STATE_FAILED; // default result
1443 trace_firmware("pvr2_upload_firmware1");
1445 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1446 hdw->hdw_desc->fx2_firmware.cnt,
1447 hdw->hdw_desc->fx2_firmware.lst);
1449 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1453 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1455 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1456 fwsize = fw_entry->size;
1458 if ((fwsize != 0x2000) &&
1459 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1460 if (hdw->hdw_desc->flag_fx2_16kb) {
1461 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1462 "Wrong fx2 firmware size"
1463 " (expected 8192 or 16384, got %u)",
1466 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1467 "Wrong fx2 firmware size"
1468 " (expected 8192, got %u)",
1471 release_firmware(fw_entry);
1475 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1476 if (fw_ptr == NULL){
1477 release_firmware(fw_entry);
1481 /* We have to hold the CPU during firmware upload. */
1482 pvr2_hdw_cpureset_assert(hdw,1);
1484 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1488 for (address = 0; address < fwsize; address += 0x800) {
1489 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1490 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1491 0, fw_ptr, 0x800, HZ);
1494 trace_firmware("Upload done, releasing device's CPU");
1496 /* Now release the CPU. It will disconnect and reconnect later. */
1497 pvr2_hdw_cpureset_assert(hdw,0);
1500 release_firmware(fw_entry);
1502 trace_firmware("Upload done (%d bytes sent)",ret);
1504 /* We should have written fwsize bytes */
1505 if (ret == fwsize) {
1506 hdw->fw1_state = FW1_STATE_RELOAD;
1515 * pvr2_upload_firmware2()
1517 * This uploads encoder firmware on endpoint 2.
1521 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1523 const struct firmware *fw_entry = NULL;
1525 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1529 static const char *fw_files[] = {
1530 CX2341X_FIRM_ENC_FILENAME,
1533 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1537 trace_firmware("pvr2_upload_firmware2");
1539 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1540 ARRAY_SIZE(fw_files), fw_files);
1541 if (ret < 0) return ret;
1544 /* Since we're about to completely reinitialize the encoder,
1545 invalidate our cached copy of its configuration state. Next
1546 time we configure the encoder, then we'll fully configure it. */
1547 hdw->enc_cur_valid = 0;
1549 /* Encoder is about to be reset so note that as far as we're
1550 concerned now, the encoder has never been run. */
1551 del_timer_sync(&hdw->encoder_run_timer);
1552 if (hdw->state_encoder_runok) {
1553 hdw->state_encoder_runok = 0;
1554 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1557 /* First prepare firmware loading */
1558 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1559 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1560 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1561 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1562 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1563 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1564 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1565 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1566 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1567 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1568 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1569 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1570 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1571 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1572 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1573 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1574 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1575 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1578 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1579 "firmware2 upload prep failed, ret=%d",ret);
1580 release_firmware(fw_entry);
1584 /* Now send firmware */
1586 fw_len = fw_entry->size;
1588 if (fw_len % sizeof(u32)) {
1589 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1590 "size of %s firmware"
1591 " must be a multiple of %zu bytes",
1592 fw_files[fwidx],sizeof(u32));
1593 release_firmware(fw_entry);
1598 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1599 if (fw_ptr == NULL){
1600 release_firmware(fw_entry);
1601 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1602 "failed to allocate memory for firmware2 upload");
1607 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1610 for (fw_done = 0; fw_done < fw_len;) {
1611 bcnt = fw_len - fw_done;
1612 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1613 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1614 /* Usbsnoop log shows that we must swap bytes... */
1615 /* Some background info: The data being swapped here is a
1616 firmware image destined for the mpeg encoder chip that
1617 lives at the other end of a USB endpoint. The encoder
1618 chip always talks in 32 bit chunks and its storage is
1619 organized into 32 bit words. However from the file
1620 system to the encoder chip everything is purely a byte
1621 stream. The firmware file's contents are always 32 bit
1622 swapped from what the encoder expects. Thus the need
1623 always exists to swap the bytes regardless of the endian
1624 type of the host processor and therefore swab32() makes
1626 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1627 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1629 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1630 &actual_length, HZ);
1631 ret |= (actual_length != bcnt);
1636 trace_firmware("upload of %s : %i / %i ",
1637 fw_files[fwidx],fw_done,fw_len);
1640 release_firmware(fw_entry);
1643 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1644 "firmware2 upload transfer failure");
1650 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1651 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1652 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1655 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1656 "firmware2 upload post-proc failure");
1660 if (hdw->hdw_desc->signal_routing_scheme ==
1661 PVR2_ROUTING_SCHEME_GOTVIEW) {
1662 /* Ensure that GPIO 11 is set to output for GOTVIEW
1664 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1670 static const char *pvr2_get_state_name(unsigned int st)
1672 if (st < ARRAY_SIZE(pvr2_state_names)) {
1673 return pvr2_state_names[st];
1678 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1680 /* Even though we really only care about the video decoder chip at
1681 this point, we'll broadcast stream on/off to all sub-devices
1682 anyway, just in case somebody else wants to hear the
1684 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1685 (enablefl ? "on" : "off"));
1686 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1687 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1688 if (hdw->decoder_client_id) {
1689 /* We get here if the encoder has been noticed. Otherwise
1690 we'll issue a warning to the user (which should
1691 normally never happen). */
1694 if (!hdw->flag_decoder_missed) {
1695 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1696 "WARNING: No decoder present");
1697 hdw->flag_decoder_missed = !0;
1698 trace_stbit("flag_decoder_missed",
1699 hdw->flag_decoder_missed);
1705 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1707 return hdw->master_state;
1711 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1713 if (!hdw->flag_tripped) return 0;
1714 hdw->flag_tripped = 0;
1715 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1716 "Clearing driver error statuss");
1721 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1724 LOCK_TAKE(hdw->big_lock); do {
1725 fl = pvr2_hdw_untrip_unlocked(hdw);
1726 } while (0); LOCK_GIVE(hdw->big_lock);
1727 if (fl) pvr2_hdw_state_sched(hdw);
1734 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1736 return hdw->state_pipeline_req != 0;
1740 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1743 LOCK_TAKE(hdw->big_lock); do {
1744 pvr2_hdw_untrip_unlocked(hdw);
1745 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1746 hdw->state_pipeline_req = enable_flag != 0;
1747 pvr2_trace(PVR2_TRACE_START_STOP,
1748 "/*--TRACE_STREAM--*/ %s",
1749 enable_flag ? "enable" : "disable");
1751 pvr2_hdw_state_sched(hdw);
1752 } while (0); LOCK_GIVE(hdw->big_lock);
1753 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1755 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1756 if (st != PVR2_STATE_READY) return -EIO;
1757 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1764 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1767 LOCK_TAKE(hdw->big_lock);
1768 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1769 hdw->desired_stream_type = config;
1770 hdw->state_pipeline_config = 0;
1771 trace_stbit("state_pipeline_config",
1772 hdw->state_pipeline_config);
1773 pvr2_hdw_state_sched(hdw);
1775 LOCK_GIVE(hdw->big_lock);
1777 return pvr2_hdw_wait(hdw,0);
1781 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1783 int unit_number = hdw->unit_number;
1785 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1786 tp = tuner[unit_number];
1788 if (tp < 0) return -EINVAL;
1789 hdw->tuner_type = tp;
1790 hdw->tuner_updated = !0;
1795 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1797 int unit_number = hdw->unit_number;
1799 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1800 tp = video_std[unit_number];
1807 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1809 int unit_number = hdw->unit_number;
1811 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1812 tp = tolerance[unit_number];
1818 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1820 /* Try a harmless request to fetch the eeprom's address over
1821 endpoint 1. See what happens. Only the full FX2 image can
1822 respond to this. If this probe fails then likely the FX2
1823 firmware needs be loaded. */
1825 LOCK_TAKE(hdw->ctl_lock); do {
1826 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1827 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1830 if (result < 0) break;
1831 } while(0); LOCK_GIVE(hdw->ctl_lock);
1833 pvr2_trace(PVR2_TRACE_INIT,
1834 "Probe of device endpoint 1 result status %d",
1837 pvr2_trace(PVR2_TRACE_INIT,
1838 "Probe of device endpoint 1 succeeded");
1843 struct pvr2_std_hack {
1844 v4l2_std_id pat; /* Pattern to match */
1845 v4l2_std_id msk; /* Which bits we care about */
1846 v4l2_std_id std; /* What additional standards or default to set */
1849 /* This data structure labels specific combinations of standards from
1850 tveeprom that we'll try to recognize. If we recognize one, then assume
1851 a specified default standard to use. This is here because tveeprom only
1852 tells us about available standards not the intended default standard (if
1853 any) for the device in question. We guess the default based on what has
1854 been reported as available. Note that this is only for guessing a
1855 default - which can always be overridden explicitly - and if the user
1856 has otherwise named a default then that default will always be used in
1857 place of this table. */
1858 static const struct pvr2_std_hack std_eeprom_maps[] = {
1860 .pat = V4L2_STD_B|V4L2_STD_GH,
1861 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1865 .std = V4L2_STD_NTSC_M,
1868 .pat = V4L2_STD_PAL_I,
1869 .std = V4L2_STD_PAL_I,
1872 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1873 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1877 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1881 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1885 v4l2_std_id std1,std2,std3;
1887 std1 = get_default_standard(hdw);
1888 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1890 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1891 pvr2_trace(PVR2_TRACE_STD,
1892 "Supported video standard(s) reported available"
1893 " in hardware: %.*s",
1896 hdw->std_mask_avail = hdw->std_mask_eeprom;
1898 std2 = (std1|std3) & ~hdw->std_mask_avail;
1900 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1901 pvr2_trace(PVR2_TRACE_STD,
1902 "Expanding supported video standards"
1903 " to include: %.*s",
1905 hdw->std_mask_avail |= std2;
1908 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1911 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1912 pvr2_trace(PVR2_TRACE_STD,
1913 "Initial video standard forced to %.*s",
1915 hdw->std_mask_cur = std1;
1916 hdw->std_dirty = !0;
1920 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1921 pvr2_trace(PVR2_TRACE_STD,
1922 "Initial video standard"
1923 " (determined by device type): %.*s",bcnt,buf);
1924 hdw->std_mask_cur = std3;
1925 hdw->std_dirty = !0;
1931 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1932 if (std_eeprom_maps[idx].msk ?
1933 ((std_eeprom_maps[idx].pat ^
1934 hdw->std_mask_eeprom) &
1935 std_eeprom_maps[idx].msk) :
1936 (std_eeprom_maps[idx].pat !=
1937 hdw->std_mask_eeprom)) continue;
1938 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1939 std_eeprom_maps[idx].std);
1940 pvr2_trace(PVR2_TRACE_STD,
1941 "Initial video standard guessed as %.*s",
1943 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1944 hdw->std_dirty = !0;
1952 static unsigned int pvr2_copy_i2c_addr_list(
1953 unsigned short *dst, const unsigned char *src,
1954 unsigned int dst_max)
1956 unsigned int cnt = 0;
1958 while (src[cnt] && (cnt + 1) < dst_max) {
1959 dst[cnt] = src[cnt];
1962 dst[cnt] = I2C_CLIENT_END;
1967 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1970 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1971 for cx25840 causes that module to correctly set up its video
1972 scaling. This is really a problem in the cx25840 module itself,
1973 but we work around it here. The problem has not been seen in
1974 ivtv because there VBI is supported and set up. We don't do VBI
1975 here (at least not yet) and thus we never attempted to even set
1978 struct v4l2_format fmt;
1979 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1980 /* We're not using a cx25840 so don't enable the hack */
1984 pvr2_trace(PVR2_TRACE_INIT,
1986 " Executing cx25840 VBI hack",
1987 hdw->decoder_client_id);
1988 memset(&fmt, 0, sizeof(fmt));
1989 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1990 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1991 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1992 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1993 vbi, s_sliced_fmt, &fmt.fmt.sliced);
1997 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1998 const struct pvr2_device_client_desc *cd)
2002 struct v4l2_subdev *sd;
2003 unsigned int i2ccnt;
2004 const unsigned char *p;
2005 /* Arbitrary count - max # i2c addresses we will probe */
2006 unsigned short i2caddr[25];
2008 mid = cd->module_id;
2009 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2011 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2012 "Module ID %u for device %s has no name?"
2013 " The driver might have a configuration problem.",
2015 hdw->hdw_desc->description);
2018 pvr2_trace(PVR2_TRACE_INIT,
2019 "Module ID %u (%s) for device %s being loaded...",
2021 hdw->hdw_desc->description);
2023 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2024 ARRAY_SIZE(i2caddr));
2025 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2026 module_i2c_addresses[mid] : NULL) != NULL)) {
2027 /* Second chance: Try default i2c address list */
2028 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2029 ARRAY_SIZE(i2caddr));
2031 pvr2_trace(PVR2_TRACE_INIT,
2033 " Using default i2c address list",
2039 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2040 "Module ID %u (%s) for device %s:"
2041 " No i2c addresses."
2042 " The driver might have a configuration problem.",
2043 mid, fname, hdw->hdw_desc->description);
2048 pvr2_trace(PVR2_TRACE_INIT,
2050 " Setting up with specified i2c address 0x%x",
2052 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2053 fname, i2caddr[0], NULL);
2055 pvr2_trace(PVR2_TRACE_INIT,
2057 " Setting up with address probe list",
2059 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2064 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2065 "Module ID %u (%s) for device %s failed to load."
2066 " Possible missing sub-device kernel module or"
2067 " initialization failure within module.",
2068 mid, fname, hdw->hdw_desc->description);
2072 /* Tag this sub-device instance with the module ID we know about.
2073 In other places we'll use that tag to determine if the instance
2074 requires special handling. */
2077 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2080 /* client-specific setup... */
2082 case PVR2_CLIENT_ID_CX25840:
2083 case PVR2_CLIENT_ID_SAA7115:
2084 hdw->decoder_client_id = mid;
2093 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2096 const struct pvr2_string_table *cm;
2097 const struct pvr2_device_client_table *ct;
2100 cm = &hdw->hdw_desc->client_modules;
2101 for (idx = 0; idx < cm->cnt; idx++) {
2102 request_module(cm->lst[idx]);
2105 ct = &hdw->hdw_desc->client_table;
2106 for (idx = 0; idx < ct->cnt; idx++) {
2107 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2110 hdw->flag_modulefail = !0;
2111 pvr2_hdw_render_useless(hdw);
2116 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2120 struct pvr2_ctrl *cptr;
2122 if (hdw->hdw_desc->fx2_firmware.cnt) {
2125 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2128 pvr2_trace(PVR2_TRACE_INIT,
2129 "USB endpoint config looks strange"
2130 "; possibly firmware needs to be"
2135 reloadFl = !pvr2_hdw_check_firmware(hdw);
2137 pvr2_trace(PVR2_TRACE_INIT,
2138 "Check for FX2 firmware failed"
2139 "; possibly firmware needs to be"
2144 if (pvr2_upload_firmware1(hdw) != 0) {
2145 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2146 "Failure uploading firmware1");
2151 hdw->fw1_state = FW1_STATE_OK;
2153 if (!pvr2_hdw_dev_ok(hdw)) return;
2155 hdw->force_dirty = !0;
2157 if (!hdw->hdw_desc->flag_no_powerup) {
2158 pvr2_hdw_cmd_powerup(hdw);
2159 if (!pvr2_hdw_dev_ok(hdw)) return;
2162 /* Take the IR chip out of reset, if appropriate */
2163 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2164 pvr2_issue_simple_cmd(hdw,
2165 FX2CMD_HCW_ZILOG_RESET |
2170 // This step MUST happen after the earlier powerup step.
2171 pvr2_i2c_core_init(hdw);
2172 if (!pvr2_hdw_dev_ok(hdw)) return;
2174 pvr2_hdw_load_modules(hdw);
2175 if (!pvr2_hdw_dev_ok(hdw)) return;
2177 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2179 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2180 cptr = hdw->controls + idx;
2181 if (cptr->info->skip_init) continue;
2182 if (!cptr->info->set_value) continue;
2183 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2186 pvr2_hdw_cx25840_vbi_hack(hdw);
2188 /* Set up special default values for the television and radio
2189 frequencies here. It's not really important what these defaults
2190 are, but I set them to something usable in the Chicago area just
2191 to make driver testing a little easier. */
2193 hdw->freqValTelevision = default_tv_freq;
2194 hdw->freqValRadio = default_radio_freq;
2196 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2197 // thread-safe against the normal pvr2_send_request() mechanism.
2198 // (We should make it thread safe).
2200 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2201 ret = pvr2_hdw_get_eeprom_addr(hdw);
2202 if (!pvr2_hdw_dev_ok(hdw)) return;
2204 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2205 "Unable to determine location of eeprom,"
2208 hdw->eeprom_addr = ret;
2209 pvr2_eeprom_analyze(hdw);
2210 if (!pvr2_hdw_dev_ok(hdw)) return;
2213 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2214 hdw->tuner_updated = !0;
2215 hdw->std_mask_eeprom = V4L2_STD_ALL;
2218 if (hdw->serial_number) {
2219 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2220 "sn-%lu", hdw->serial_number);
2221 } else if (hdw->unit_number >= 0) {
2222 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2224 hdw->unit_number + 'a');
2226 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2229 hdw->identifier[idx] = 0;
2231 pvr2_hdw_setup_std(hdw);
2233 if (!get_default_tuner_type(hdw)) {
2234 pvr2_trace(PVR2_TRACE_INIT,
2235 "pvr2_hdw_setup: Tuner type overridden to %d",
2240 if (!pvr2_hdw_dev_ok(hdw)) return;
2242 if (hdw->hdw_desc->signal_routing_scheme ==
2243 PVR2_ROUTING_SCHEME_GOTVIEW) {
2244 /* Ensure that GPIO 11 is set to output for GOTVIEW
2246 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2249 pvr2_hdw_commit_setup(hdw);
2251 hdw->vid_stream = pvr2_stream_create();
2252 if (!pvr2_hdw_dev_ok(hdw)) return;
2253 pvr2_trace(PVR2_TRACE_INIT,
2254 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2255 if (hdw->vid_stream) {
2256 idx = get_default_error_tolerance(hdw);
2258 pvr2_trace(PVR2_TRACE_INIT,
2259 "pvr2_hdw_setup: video stream %p"
2260 " setting tolerance %u",
2261 hdw->vid_stream,idx);
2263 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2264 PVR2_VID_ENDPOINT,idx);
2267 if (!pvr2_hdw_dev_ok(hdw)) return;
2269 hdw->flag_init_ok = !0;
2271 pvr2_hdw_state_sched(hdw);
2275 /* Set up the structure and attempt to put the device into a usable state.
2276 This can be a time-consuming operation, which is why it is not done
2277 internally as part of the create() step. */
2278 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2280 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2282 pvr2_hdw_setup_low(hdw);
2283 pvr2_trace(PVR2_TRACE_INIT,
2284 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2285 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2286 if (pvr2_hdw_dev_ok(hdw)) {
2287 if (hdw->flag_init_ok) {
2290 "Device initialization"
2291 " completed successfully.");
2294 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2297 "Device microcontroller firmware"
2298 " (re)loaded; it should now reset"
2303 PVR2_TRACE_ERROR_LEGS,
2304 "Device initialization was not successful.");
2305 if (hdw->fw1_state == FW1_STATE_MISSING) {
2307 PVR2_TRACE_ERROR_LEGS,
2308 "Giving up since device"
2309 " microcontroller firmware"
2310 " appears to be missing.");
2314 if (hdw->flag_modulefail) {
2316 PVR2_TRACE_ERROR_LEGS,
2317 "***WARNING*** pvrusb2 driver initialization"
2318 " failed due to the failure of one or more"
2319 " sub-device kernel modules.");
2321 PVR2_TRACE_ERROR_LEGS,
2322 "You need to resolve the failing condition"
2323 " before this driver can function. There"
2324 " should be some earlier messages giving more"
2325 " information about the problem.");
2330 PVR2_TRACE_ERROR_LEGS,
2331 "Attempting pvrusb2 recovery by reloading"
2332 " primary firmware.");
2334 PVR2_TRACE_ERROR_LEGS,
2335 "If this works, device should disconnect"
2336 " and reconnect in a sane state.");
2337 hdw->fw1_state = FW1_STATE_UNKNOWN;
2338 pvr2_upload_firmware1(hdw);
2341 PVR2_TRACE_ERROR_LEGS,
2342 "***WARNING*** pvrusb2 device hardware"
2343 " appears to be jammed"
2344 " and I can't clear it.");
2346 PVR2_TRACE_ERROR_LEGS,
2347 "You might need to power cycle"
2348 " the pvrusb2 device"
2349 " in order to recover.");
2352 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2356 /* Perform second stage initialization. Set callback pointer first so that
2357 we can avoid a possible initialization race (if the kernel thread runs
2358 before the callback has been set). */
2359 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2360 void (*callback_func)(void *),
2361 void *callback_data)
2363 LOCK_TAKE(hdw->big_lock); do {
2364 if (hdw->flag_disconnected) {
2365 /* Handle a race here: If we're already
2366 disconnected by this point, then give up. If we
2367 get past this then we'll remain connected for
2368 the duration of initialization since the entire
2369 initialization sequence is now protected by the
2373 hdw->state_data = callback_data;
2374 hdw->state_func = callback_func;
2375 pvr2_hdw_setup(hdw);
2376 } while (0); LOCK_GIVE(hdw->big_lock);
2377 return hdw->flag_init_ok;
2381 /* Create, set up, and return a structure for interacting with the
2382 underlying hardware. */
2383 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2384 const struct usb_device_id *devid)
2386 unsigned int idx,cnt1,cnt2,m;
2387 struct pvr2_hdw *hdw = NULL;
2389 struct pvr2_ctrl *cptr;
2390 struct usb_device *usb_dev;
2391 const struct pvr2_device_desc *hdw_desc;
2393 struct v4l2_queryctrl qctrl;
2394 struct pvr2_ctl_info *ciptr;
2396 usb_dev = interface_to_usbdev(intf);
2398 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2400 if (hdw_desc == NULL) {
2401 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2402 " No device description pointer,"
2403 " unable to continue.");
2404 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2405 " please contact Mike Isely <isely@pobox.com>"
2406 " to get it included in the driver\n");
2410 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2411 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2412 hdw,hdw_desc->description);
2413 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2414 hdw_desc->description);
2415 if (hdw_desc->flag_is_experimental) {
2416 pvr2_trace(PVR2_TRACE_INFO, "**********");
2417 pvr2_trace(PVR2_TRACE_INFO,
2418 "WARNING: Support for this device (%s) is"
2419 " experimental.", hdw_desc->description);
2420 pvr2_trace(PVR2_TRACE_INFO,
2421 "Important functionality might not be"
2422 " entirely working.");
2423 pvr2_trace(PVR2_TRACE_INFO,
2424 "Please consider contacting the driver author to"
2425 " help with further stabilization of the driver.");
2426 pvr2_trace(PVR2_TRACE_INFO, "**********");
2428 if (!hdw) goto fail;
2430 setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout,
2431 (unsigned long)hdw);
2433 setup_timer(&hdw->decoder_stabilization_timer,
2434 pvr2_hdw_decoder_stabilization_timeout,
2435 (unsigned long)hdw);
2437 setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2438 (unsigned long)hdw);
2440 setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout,
2441 (unsigned long)hdw);
2443 hdw->master_state = PVR2_STATE_DEAD;
2445 init_waitqueue_head(&hdw->state_wait_data);
2447 hdw->tuner_signal_stale = !0;
2448 cx2341x_fill_defaults(&hdw->enc_ctl_state);
2450 /* Calculate which inputs are OK */
2452 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2453 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2454 m |= 1 << PVR2_CVAL_INPUT_DTV;
2456 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2457 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2458 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2459 hdw->input_avail_mask = m;
2460 hdw->input_allowed_mask = hdw->input_avail_mask;
2462 /* If not a hybrid device, pathway_state never changes. So
2463 initialize it here to what it should forever be. */
2464 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2465 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2466 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2467 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2470 hdw->control_cnt = CTRLDEF_COUNT;
2471 hdw->control_cnt += MPEGDEF_COUNT;
2472 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2474 if (!hdw->controls) goto fail;
2475 hdw->hdw_desc = hdw_desc;
2476 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2477 for (idx = 0; idx < hdw->control_cnt; idx++) {
2478 cptr = hdw->controls + idx;
2481 for (idx = 0; idx < 32; idx++) {
2482 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2484 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2485 cptr = hdw->controls + idx;
2486 cptr->info = control_defs+idx;
2489 /* Ensure that default input choice is a valid one. */
2490 m = hdw->input_avail_mask;
2491 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2492 if (!((1 << idx) & m)) continue;
2493 hdw->input_val = idx;
2497 /* Define and configure additional controls from cx2341x module. */
2498 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2499 sizeof(*(hdw->mpeg_ctrl_info)),
2501 if (!hdw->mpeg_ctrl_info) goto fail;
2502 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2503 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2504 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2505 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2506 ciptr->name = mpeg_ids[idx].strid;
2507 ciptr->v4l_id = mpeg_ids[idx].id;
2508 ciptr->skip_init = !0;
2509 ciptr->get_value = ctrl_cx2341x_get;
2510 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2511 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2512 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2513 qctrl.id = ciptr->v4l_id;
2514 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2515 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2516 ciptr->set_value = ctrl_cx2341x_set;
2518 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2519 PVR2_CTLD_INFO_DESC_SIZE);
2520 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2521 ciptr->default_value = qctrl.default_value;
2522 switch (qctrl.type) {
2524 case V4L2_CTRL_TYPE_INTEGER:
2525 ciptr->type = pvr2_ctl_int;
2526 ciptr->def.type_int.min_value = qctrl.minimum;
2527 ciptr->def.type_int.max_value = qctrl.maximum;
2529 case V4L2_CTRL_TYPE_BOOLEAN:
2530 ciptr->type = pvr2_ctl_bool;
2532 case V4L2_CTRL_TYPE_MENU:
2533 ciptr->type = pvr2_ctl_enum;
2534 ciptr->def.type_enum.value_names =
2535 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2538 ciptr->def.type_enum.value_names[cnt1] != NULL;
2540 ciptr->def.type_enum.count = cnt1;
2546 // Initialize control data regarding video standard masks
2547 valid_std_mask = pvr2_std_get_usable();
2548 for (idx = 0; idx < 32; idx++) {
2549 if (!(valid_std_mask & (1 << idx))) continue;
2550 cnt1 = pvr2_std_id_to_str(
2551 hdw->std_mask_names[idx],
2552 sizeof(hdw->std_mask_names[idx])-1,
2554 hdw->std_mask_names[idx][cnt1] = 0;
2556 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2558 memcpy(&hdw->std_info_avail,cptr->info,
2559 sizeof(hdw->std_info_avail));
2560 cptr->info = &hdw->std_info_avail;
2561 hdw->std_info_avail.def.type_bitmask.bit_names =
2563 hdw->std_info_avail.def.type_bitmask.valid_bits =
2566 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2568 memcpy(&hdw->std_info_cur,cptr->info,
2569 sizeof(hdw->std_info_cur));
2570 cptr->info = &hdw->std_info_cur;
2571 hdw->std_info_cur.def.type_bitmask.bit_names =
2573 hdw->std_info_cur.def.type_bitmask.valid_bits =
2576 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2578 memcpy(&hdw->std_info_detect,cptr->info,
2579 sizeof(hdw->std_info_detect));
2580 cptr->info = &hdw->std_info_detect;
2581 hdw->std_info_detect.def.type_bitmask.bit_names =
2583 hdw->std_info_detect.def.type_bitmask.valid_bits =
2587 hdw->cropcap_stale = !0;
2588 hdw->eeprom_addr = -1;
2589 hdw->unit_number = -1;
2590 hdw->v4l_minor_number_video = -1;
2591 hdw->v4l_minor_number_vbi = -1;
2592 hdw->v4l_minor_number_radio = -1;
2593 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2594 if (!hdw->ctl_write_buffer) goto fail;
2595 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2596 if (!hdw->ctl_read_buffer) goto fail;
2597 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2598 if (!hdw->ctl_write_urb) goto fail;
2599 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2600 if (!hdw->ctl_read_urb) goto fail;
2602 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2603 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2604 "Error registering with v4l core, giving up");
2607 mutex_lock(&pvr2_unit_mtx);
2609 for (idx = 0; idx < PVR_NUM; idx++) {
2610 if (unit_pointers[idx]) continue;
2611 hdw->unit_number = idx;
2612 unit_pointers[idx] = hdw;
2616 mutex_unlock(&pvr2_unit_mtx);
2619 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2621 if (hdw->unit_number >= 0) {
2622 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2623 ('a' + hdw->unit_number));
2626 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2627 hdw->name[cnt1] = 0;
2629 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2630 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2632 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2633 hdw->unit_number,hdw->name);
2635 hdw->tuner_type = -1;
2638 hdw->usb_intf = intf;
2639 hdw->usb_dev = usb_dev;
2641 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2643 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2644 usb_set_interface(hdw->usb_dev,ifnum,0);
2646 mutex_init(&hdw->ctl_lock_mutex);
2647 mutex_init(&hdw->big_lock_mutex);
2652 del_timer_sync(&hdw->quiescent_timer);
2653 del_timer_sync(&hdw->decoder_stabilization_timer);
2654 del_timer_sync(&hdw->encoder_run_timer);
2655 del_timer_sync(&hdw->encoder_wait_timer);
2656 if (hdw->workqueue) {
2657 flush_workqueue(hdw->workqueue);
2658 destroy_workqueue(hdw->workqueue);
2659 hdw->workqueue = NULL;
2661 usb_free_urb(hdw->ctl_read_urb);
2662 usb_free_urb(hdw->ctl_write_urb);
2663 kfree(hdw->ctl_read_buffer);
2664 kfree(hdw->ctl_write_buffer);
2665 kfree(hdw->controls);
2666 kfree(hdw->mpeg_ctrl_info);
2673 /* Remove _all_ associations between this driver and the underlying USB
2675 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2677 if (hdw->flag_disconnected) return;
2678 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2679 if (hdw->ctl_read_urb) {
2680 usb_kill_urb(hdw->ctl_read_urb);
2681 usb_free_urb(hdw->ctl_read_urb);
2682 hdw->ctl_read_urb = NULL;
2684 if (hdw->ctl_write_urb) {
2685 usb_kill_urb(hdw->ctl_write_urb);
2686 usb_free_urb(hdw->ctl_write_urb);
2687 hdw->ctl_write_urb = NULL;
2689 if (hdw->ctl_read_buffer) {
2690 kfree(hdw->ctl_read_buffer);
2691 hdw->ctl_read_buffer = NULL;
2693 if (hdw->ctl_write_buffer) {
2694 kfree(hdw->ctl_write_buffer);
2695 hdw->ctl_write_buffer = NULL;
2697 hdw->flag_disconnected = !0;
2698 /* If we don't do this, then there will be a dangling struct device
2699 reference to our disappearing device persisting inside the V4L
2701 v4l2_device_disconnect(&hdw->v4l2_dev);
2702 hdw->usb_dev = NULL;
2703 hdw->usb_intf = NULL;
2704 pvr2_hdw_render_useless(hdw);
2707 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2709 vdev->v4l2_dev = &hdw->v4l2_dev;
2712 /* Destroy hardware interaction structure */
2713 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2716 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2717 if (hdw->workqueue) {
2718 flush_workqueue(hdw->workqueue);
2719 destroy_workqueue(hdw->workqueue);
2720 hdw->workqueue = NULL;
2722 del_timer_sync(&hdw->quiescent_timer);
2723 del_timer_sync(&hdw->decoder_stabilization_timer);
2724 del_timer_sync(&hdw->encoder_run_timer);
2725 del_timer_sync(&hdw->encoder_wait_timer);
2726 if (hdw->fw_buffer) {
2727 kfree(hdw->fw_buffer);
2728 hdw->fw_buffer = NULL;
2730 if (hdw->vid_stream) {
2731 pvr2_stream_destroy(hdw->vid_stream);
2732 hdw->vid_stream = NULL;
2734 v4l2_device_unregister(&hdw->v4l2_dev);
2735 pvr2_hdw_disconnect(hdw);
2736 mutex_lock(&pvr2_unit_mtx);
2738 if ((hdw->unit_number >= 0) &&
2739 (hdw->unit_number < PVR_NUM) &&
2740 (unit_pointers[hdw->unit_number] == hdw)) {
2741 unit_pointers[hdw->unit_number] = NULL;
2744 mutex_unlock(&pvr2_unit_mtx);
2745 kfree(hdw->controls);
2746 kfree(hdw->mpeg_ctrl_info);
2751 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2753 return (hdw && hdw->flag_ok);
2757 /* Called when hardware has been unplugged */
2758 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2760 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2761 LOCK_TAKE(hdw->big_lock);
2762 pvr2_i2c_core_done(hdw);
2763 LOCK_TAKE(hdw->ctl_lock);
2764 pvr2_hdw_remove_usb_stuff(hdw);
2765 LOCK_GIVE(hdw->ctl_lock);
2766 LOCK_GIVE(hdw->big_lock);
2770 /* Get the number of defined controls */
2771 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2773 return hdw->control_cnt;
2777 /* Retrieve a control handle given its index (0..count-1) */
2778 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2781 if (idx >= hdw->control_cnt) return NULL;
2782 return hdw->controls + idx;
2786 /* Retrieve a control handle given its index (0..count-1) */
2787 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2788 unsigned int ctl_id)
2790 struct pvr2_ctrl *cptr;
2794 /* This could be made a lot more efficient, but for now... */
2795 for (idx = 0; idx < hdw->control_cnt; idx++) {
2796 cptr = hdw->controls + idx;
2797 i = cptr->info->internal_id;
2798 if (i && (i == ctl_id)) return cptr;
2804 /* Given a V4L ID, retrieve the control structure associated with it. */
2805 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2807 struct pvr2_ctrl *cptr;
2811 /* This could be made a lot more efficient, but for now... */
2812 for (idx = 0; idx < hdw->control_cnt; idx++) {
2813 cptr = hdw->controls + idx;
2814 i = cptr->info->v4l_id;
2815 if (i && (i == ctl_id)) return cptr;
2821 /* Given a V4L ID for its immediate predecessor, retrieve the control
2822 structure associated with it. */
2823 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2824 unsigned int ctl_id)
2826 struct pvr2_ctrl *cptr,*cp2;
2830 /* This could be made a lot more efficient, but for now... */
2832 for (idx = 0; idx < hdw->control_cnt; idx++) {
2833 cptr = hdw->controls + idx;
2834 i = cptr->info->v4l_id;
2836 if (i <= ctl_id) continue;
2837 if (cp2 && (cp2->info->v4l_id < i)) continue;
2845 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2848 case pvr2_ctl_int: return "integer";
2849 case pvr2_ctl_enum: return "enum";
2850 case pvr2_ctl_bool: return "boolean";
2851 case pvr2_ctl_bitmask: return "bitmask";
2857 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2858 const char *name, int val)
2860 struct v4l2_control ctrl;
2861 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2862 memset(&ctrl, 0, sizeof(ctrl));
2865 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2868 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2869 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2870 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2873 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2876 std = (v4l2_std_id)hdw->std_mask_avail;
2877 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2878 video, querystd, &std);
2882 /* Execute whatever commands are required to update the state of all the
2883 sub-devices so that they match our current control values. */
2884 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2886 struct v4l2_subdev *sd;
2888 pvr2_subdev_update_func fp;
2890 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2892 if (hdw->tuner_updated || hdw->force_dirty) {
2893 struct tuner_setup setup;
2894 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2896 if (((int)(hdw->tuner_type)) >= 0) {
2897 memset(&setup, 0, sizeof(setup));
2898 setup.addr = ADDR_UNSET;
2899 setup.type = hdw->tuner_type;
2900 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2901 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2902 tuner, s_type_addr, &setup);
2906 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2907 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2908 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2909 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2913 vs = hdw->std_mask_cur;
2914 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2916 pvr2_hdw_cx25840_vbi_hack(hdw);
2918 hdw->tuner_signal_stale = !0;
2919 hdw->cropcap_stale = !0;
2922 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2923 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2924 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2925 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2926 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2927 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2928 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2929 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2930 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2932 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2933 struct v4l2_tuner vt;
2934 memset(&vt, 0, sizeof(vt));
2935 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2936 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2937 vt.audmode = hdw->audiomode_val;
2938 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2941 if (hdw->freqDirty || hdw->force_dirty) {
2943 struct v4l2_frequency freq;
2944 fv = pvr2_hdw_get_cur_freq(hdw);
2945 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2946 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2947 memset(&freq, 0, sizeof(freq));
2948 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2949 /* ((fv * 1000) / 62500) */
2950 freq.frequency = (fv * 2) / 125;
2952 freq.frequency = fv / 62500;
2954 /* tuner-core currently doesn't seem to care about this, but
2955 let's set it anyway for completeness. */
2956 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2957 freq.type = V4L2_TUNER_RADIO;
2959 freq.type = V4L2_TUNER_ANALOG_TV;
2962 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2963 s_frequency, &freq);
2966 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2967 struct v4l2_subdev_format format = {
2968 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2971 format.format.width = hdw->res_hor_val;
2972 format.format.height = hdw->res_ver_val;
2973 format.format.code = MEDIA_BUS_FMT_FIXED;
2974 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2975 format.format.width, format.format.height);
2976 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2980 if (hdw->srate_dirty || hdw->force_dirty) {
2982 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2984 switch (hdw->srate_val) {
2986 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2989 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2992 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2996 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2997 audio, s_clock_freq, val);
3000 /* Unable to set crop parameters; there is apparently no equivalent
3001 for VIDIOC_S_CROP */
3003 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3005 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3006 fp = pvr2_module_update_functions[id];
3011 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3012 pvr2_hdw_status_poll(hdw);
3017 /* Figure out if we need to commit control changes. If so, mark internal
3018 state flags to indicate this fact and return true. Otherwise do nothing
3019 else and return false. */
3020 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3023 struct pvr2_ctrl *cptr;
3025 int commit_flag = hdw->force_dirty;
3027 unsigned int bcnt,ccnt;
3029 for (idx = 0; idx < hdw->control_cnt; idx++) {
3030 cptr = hdw->controls + idx;
3031 if (!cptr->info->is_dirty) continue;
3032 if (!cptr->info->is_dirty(cptr)) continue;
3035 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3036 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3039 cptr->info->get_value(cptr,&value);
3040 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3042 sizeof(buf)-bcnt,&ccnt);
3044 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3045 get_ctrl_typename(cptr->info->type));
3046 pvr2_trace(PVR2_TRACE_CTL,
3047 "/*--TRACE_COMMIT--*/ %.*s",
3052 /* Nothing has changed */
3056 hdw->state_pipeline_config = 0;
3057 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3058 pvr2_hdw_state_sched(hdw);
3064 /* Perform all operations needed to commit all control changes. This must
3065 be performed in synchronization with the pipeline state and is thus
3066 expected to be called as part of the driver's worker thread. Return
3067 true if commit successful, otherwise return false to indicate that
3068 commit isn't possible at this time. */
3069 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3072 struct pvr2_ctrl *cptr;
3073 int disruptive_change;
3075 if (hdw->input_dirty && hdw->state_pathway_ok &&
3076 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3077 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3078 hdw->pathway_state)) {
3079 /* Change of mode being asked for... */
3080 hdw->state_pathway_ok = 0;
3081 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3083 if (!hdw->state_pathway_ok) {
3084 /* Can't commit anything until pathway is ok. */
3088 /* Handle some required side effects when the video standard is
3090 if (hdw->std_dirty) {
3093 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3100 /* Rewrite the vertical resolution to be appropriate to the
3101 video standard that has been selected. */
3102 if (nvres != hdw->res_ver_val) {
3103 hdw->res_ver_val = nvres;
3104 hdw->res_ver_dirty = !0;
3106 /* Rewrite the GOP size to be appropriate to the video
3107 standard that has been selected. */
3108 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3109 struct v4l2_ext_controls cs;
3110 struct v4l2_ext_control c1;
3111 memset(&cs, 0, sizeof(cs));
3112 memset(&c1, 0, sizeof(c1));
3115 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3116 c1.value = gop_size;
3117 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3118 VIDIOC_S_EXT_CTRLS);
3122 /* The broadcast decoder can only scale down, so if
3123 * res_*_dirty && crop window < output format ==> enlarge crop.
3125 * The mpeg encoder receives fields of res_hor_val dots and
3126 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3128 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3129 hdw->cropw_val = hdw->res_hor_val;
3130 hdw->cropw_dirty = !0;
3131 } else if (hdw->cropw_dirty) {
3132 hdw->res_hor_dirty = !0; /* must rescale */
3133 hdw->res_hor_val = min(720, hdw->cropw_val);
3135 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3136 hdw->croph_val = hdw->res_ver_val;
3137 hdw->croph_dirty = !0;
3138 } else if (hdw->croph_dirty) {
3139 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3140 hdw->res_ver_dirty = !0;
3141 hdw->res_ver_val = min(nvres, hdw->croph_val);
3144 /* If any of the below has changed, then we can't do the update
3145 while the pipeline is running. Pipeline must be paused first
3146 and decoder -> encoder connection be made quiescent before we
3150 hdw->enc_unsafe_stale ||
3152 hdw->res_ver_dirty ||
3153 hdw->res_hor_dirty ||
3157 (hdw->active_stream_type != hdw->desired_stream_type));
3158 if (disruptive_change && !hdw->state_pipeline_idle) {
3159 /* Pipeline is not idle; we can't proceed. Arrange to
3160 cause pipeline to stop so that we can try this again
3162 hdw->state_pipeline_pause = !0;
3166 if (hdw->srate_dirty) {
3167 /* Write new sample rate into control structure since
3168 * the master copy is stale. We must track srate
3169 * separate from the mpeg control structure because
3170 * other logic also uses this value. */
3171 struct v4l2_ext_controls cs;
3172 struct v4l2_ext_control c1;
3173 memset(&cs,0,sizeof(cs));
3174 memset(&c1,0,sizeof(c1));
3177 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3178 c1.value = hdw->srate_val;
3179 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3182 if (hdw->active_stream_type != hdw->desired_stream_type) {
3183 /* Handle any side effects of stream config here */
3184 hdw->active_stream_type = hdw->desired_stream_type;
3187 if (hdw->hdw_desc->signal_routing_scheme ==
3188 PVR2_ROUTING_SCHEME_GOTVIEW) {
3190 /* Handle GOTVIEW audio switching */
3191 pvr2_hdw_gpio_get_out(hdw,&b);
3192 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3194 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3197 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3201 /* Check and update state for all sub-devices. */
3202 pvr2_subdev_update(hdw);
3204 hdw->tuner_updated = 0;
3205 hdw->force_dirty = 0;
3206 for (idx = 0; idx < hdw->control_cnt; idx++) {
3207 cptr = hdw->controls + idx;
3208 if (!cptr->info->clear_dirty) continue;
3209 cptr->info->clear_dirty(cptr);
3212 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3213 hdw->state_encoder_run) {
3214 /* If encoder isn't running or it can't be touched, then
3215 this will get worked out later when we start the
3217 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3220 hdw->state_pipeline_config = !0;
3221 /* Hardware state may have changed in a way to cause the cropping
3222 capabilities to have changed. So mark it stale, which will
3223 cause a later re-fetch. */
3224 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3229 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3232 LOCK_TAKE(hdw->big_lock);
3233 fl = pvr2_hdw_commit_setup(hdw);
3234 LOCK_GIVE(hdw->big_lock);
3236 return pvr2_hdw_wait(hdw,0);
3240 static void pvr2_hdw_worker_poll(struct work_struct *work)
3243 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3244 LOCK_TAKE(hdw->big_lock); do {
3245 fl = pvr2_hdw_state_eval(hdw);
3246 } while (0); LOCK_GIVE(hdw->big_lock);
3247 if (fl && hdw->state_func) {
3248 hdw->state_func(hdw->state_data);
3253 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3255 return wait_event_interruptible(
3256 hdw->state_wait_data,
3257 (hdw->state_stale == 0) &&
3258 (!state || (hdw->master_state != state)));
3262 /* Return name for this driver instance */
3263 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3269 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3271 return hdw->hdw_desc->description;
3275 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3277 return hdw->hdw_desc->shortname;
3281 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3284 LOCK_TAKE(hdw->ctl_lock); do {
3285 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3286 result = pvr2_send_request(hdw,
3289 if (result < 0) break;
3290 result = (hdw->cmd_buffer[0] != 0);
3291 } while(0); LOCK_GIVE(hdw->ctl_lock);
3296 /* Execute poll of tuner status */
3297 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3299 LOCK_TAKE(hdw->big_lock); do {
3300 pvr2_hdw_status_poll(hdw);
3301 } while (0); LOCK_GIVE(hdw->big_lock);
3305 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3307 if (!hdw->cropcap_stale) {
3310 pvr2_hdw_status_poll(hdw);
3311 if (hdw->cropcap_stale) {
3318 /* Return information about cropping capabilities */
3319 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3322 LOCK_TAKE(hdw->big_lock);
3323 stat = pvr2_hdw_check_cropcap(hdw);
3325 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3327 LOCK_GIVE(hdw->big_lock);
3332 /* Return information about the tuner */
3333 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3335 LOCK_TAKE(hdw->big_lock); do {
3336 if (hdw->tuner_signal_stale) {
3337 pvr2_hdw_status_poll(hdw);
3339 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3340 } while (0); LOCK_GIVE(hdw->big_lock);
3345 /* Get handle to video output stream */
3346 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3348 return hp->vid_stream;
3352 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3354 int nr = pvr2_hdw_get_unit_number(hdw);
3355 LOCK_TAKE(hdw->big_lock);
3357 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
3358 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3359 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3360 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3361 pvr2_hdw_state_log_state(hdw);
3362 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
3364 LOCK_GIVE(hdw->big_lock);
3368 /* Grab EEPROM contents, needed for direct method. */
3369 #define EEPROM_SIZE 8192
3370 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3371 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3373 struct i2c_msg msg[2];
3382 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3384 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3385 "Failed to allocate memory"
3386 " required to read eeprom");
3390 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3392 addr = hdw->eeprom_addr;
3393 /* Seems that if the high bit is set, then the *real* eeprom
3394 address is shifted right now bit position (noticed this in
3395 newer PVR USB2 hardware) */
3396 if (addr & 0x80) addr >>= 1;
3398 /* FX2 documentation states that a 16bit-addressed eeprom is
3399 expected if the I2C address is an odd number (yeah, this is
3400 strange but it's what they do) */
3401 mode16 = (addr & 1);
3402 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3403 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3404 " using %d bit addressing",eepromSize,addr,
3409 msg[0].len = mode16 ? 2 : 1;
3412 msg[1].flags = I2C_M_RD;
3414 /* We have to do the actual eeprom data fetch ourselves, because
3415 (1) we're only fetching part of the eeprom, and (2) if we were
3416 getting the whole thing our I2C driver can't grab it in one
3417 pass - which is what tveeprom is otherwise going to attempt */
3418 memset(eeprom,0,EEPROM_SIZE);
3419 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3421 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3422 offs = tcnt + (eepromSize - EEPROM_SIZE);
3424 iadd[0] = offs >> 8;
3430 msg[1].buf = eeprom+tcnt;
3431 if ((ret = i2c_transfer(&hdw->i2c_adap,
3432 msg,ARRAY_SIZE(msg))) != 2) {
3433 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3434 "eeprom fetch set offs err=%d",ret);
3443 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3450 LOCK_TAKE(hdw->big_lock); do {
3451 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3454 pvr2_trace(PVR2_TRACE_FIRMWARE,
3455 "Cleaning up after CPU firmware fetch");
3456 kfree(hdw->fw_buffer);
3457 hdw->fw_buffer = NULL;
3459 if (hdw->fw_cpu_flag) {
3460 /* Now release the CPU. It will disconnect
3461 and reconnect later. */
3462 pvr2_hdw_cpureset_assert(hdw,0);
3467 hdw->fw_cpu_flag = (mode != 2);
3468 if (hdw->fw_cpu_flag) {
3469 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3470 pvr2_trace(PVR2_TRACE_FIRMWARE,
3471 "Preparing to suck out CPU firmware"
3472 " (size=%u)", hdw->fw_size);
3473 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3474 if (!hdw->fw_buffer) {
3479 /* We have to hold the CPU during firmware upload. */
3480 pvr2_hdw_cpureset_assert(hdw,1);
3482 /* download the firmware from address 0000-1fff in 2048
3483 (=0x800) bytes chunk. */
3485 pvr2_trace(PVR2_TRACE_FIRMWARE,
3486 "Grabbing CPU firmware");
3487 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3488 for(address = 0; address < hdw->fw_size;
3490 ret = usb_control_msg(hdw->usb_dev,pipe,
3493 hdw->fw_buffer+address,
3498 pvr2_trace(PVR2_TRACE_FIRMWARE,
3499 "Done grabbing CPU firmware");
3501 pvr2_trace(PVR2_TRACE_FIRMWARE,
3502 "Sucking down EEPROM contents");
3503 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3504 if (!hdw->fw_buffer) {
3505 pvr2_trace(PVR2_TRACE_FIRMWARE,
3506 "EEPROM content suck failed.");
3509 hdw->fw_size = EEPROM_SIZE;
3510 pvr2_trace(PVR2_TRACE_FIRMWARE,
3511 "Done sucking down EEPROM contents");
3514 } while (0); LOCK_GIVE(hdw->big_lock);
3518 /* Return true if we're in a mode for retrieval CPU firmware */
3519 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3521 return hdw->fw_buffer != NULL;
3525 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3526 char *buf,unsigned int cnt)
3529 LOCK_TAKE(hdw->big_lock); do {
3533 if (!hdw->fw_buffer) {
3538 if (offs >= hdw->fw_size) {
3539 pvr2_trace(PVR2_TRACE_FIRMWARE,
3540 "Read firmware data offs=%d EOF",
3546 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3548 memcpy(buf,hdw->fw_buffer+offs,cnt);
3550 pvr2_trace(PVR2_TRACE_FIRMWARE,
3551 "Read firmware data offs=%d cnt=%d",
3554 } while (0); LOCK_GIVE(hdw->big_lock);
3560 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3561 enum pvr2_v4l_type index)
3564 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3565 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3566 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3572 /* Store a v4l minor device number */
3573 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3574 enum pvr2_v4l_type index,int v)
3577 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3578 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3579 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3585 static void pvr2_ctl_write_complete(struct urb *urb)
3587 struct pvr2_hdw *hdw = urb->context;
3588 hdw->ctl_write_pend_flag = 0;
3589 if (hdw->ctl_read_pend_flag) return;
3590 complete(&hdw->ctl_done);
3594 static void pvr2_ctl_read_complete(struct urb *urb)
3596 struct pvr2_hdw *hdw = urb->context;
3597 hdw->ctl_read_pend_flag = 0;
3598 if (hdw->ctl_write_pend_flag) return;
3599 complete(&hdw->ctl_done);
3603 static void pvr2_ctl_timeout(unsigned long data)
3605 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3606 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3607 hdw->ctl_timeout_flag = !0;
3608 if (hdw->ctl_write_pend_flag)
3609 usb_unlink_urb(hdw->ctl_write_urb);
3610 if (hdw->ctl_read_pend_flag)
3611 usb_unlink_urb(hdw->ctl_read_urb);
3616 /* Issue a command and get a response from the device. This extended
3617 version includes a probe flag (which if set means that device errors
3618 should not be logged or treated as fatal) and a timeout in jiffies.
3619 This can be used to non-lethally probe the health of endpoint 1. */
3620 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3621 unsigned int timeout,int probe_fl,
3622 void *write_data,unsigned int write_len,
3623 void *read_data,unsigned int read_len)
3627 struct timer_list timer;
3628 if (!hdw->ctl_lock_held) {
3629 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3630 "Attempted to execute control transfer"
3634 if (!hdw->flag_ok && !probe_fl) {
3635 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3636 "Attempted to execute control transfer"
3637 " when device not ok");
3640 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3642 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3643 "Attempted to execute control transfer"
3644 " when USB is disconnected");
3649 /* Ensure that we have sane parameters */
3650 if (!write_data) write_len = 0;
3651 if (!read_data) read_len = 0;
3652 if (write_len > PVR2_CTL_BUFFSIZE) {
3654 PVR2_TRACE_ERROR_LEGS,
3655 "Attempted to execute %d byte"
3656 " control-write transfer (limit=%d)",
3657 write_len,PVR2_CTL_BUFFSIZE);
3660 if (read_len > PVR2_CTL_BUFFSIZE) {
3662 PVR2_TRACE_ERROR_LEGS,
3663 "Attempted to execute %d byte"
3664 " control-read transfer (limit=%d)",
3665 write_len,PVR2_CTL_BUFFSIZE);
3668 if ((!write_len) && (!read_len)) {
3670 PVR2_TRACE_ERROR_LEGS,
3671 "Attempted to execute null control transfer?");
3676 hdw->cmd_debug_state = 1;
3678 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3680 hdw->cmd_debug_code = 0;
3682 hdw->cmd_debug_write_len = write_len;
3683 hdw->cmd_debug_read_len = read_len;
3685 /* Initialize common stuff */
3686 init_completion(&hdw->ctl_done);
3687 hdw->ctl_timeout_flag = 0;
3688 hdw->ctl_write_pend_flag = 0;
3689 hdw->ctl_read_pend_flag = 0;
3690 setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw);
3691 timer.expires = jiffies + timeout;
3694 hdw->cmd_debug_state = 2;
3695 /* Transfer write data to internal buffer */
3696 for (idx = 0; idx < write_len; idx++) {
3697 hdw->ctl_write_buffer[idx] =
3698 ((unsigned char *)write_data)[idx];
3700 /* Initiate a write request */
3701 usb_fill_bulk_urb(hdw->ctl_write_urb,
3703 usb_sndbulkpipe(hdw->usb_dev,
3704 PVR2_CTL_WRITE_ENDPOINT),
3705 hdw->ctl_write_buffer,
3707 pvr2_ctl_write_complete,
3709 hdw->ctl_write_urb->actual_length = 0;
3710 hdw->ctl_write_pend_flag = !0;
3711 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3713 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3714 "Failed to submit write-control"
3715 " URB status=%d",status);
3716 hdw->ctl_write_pend_flag = 0;
3722 hdw->cmd_debug_state = 3;
3723 memset(hdw->ctl_read_buffer,0x43,read_len);
3724 /* Initiate a read request */
3725 usb_fill_bulk_urb(hdw->ctl_read_urb,
3727 usb_rcvbulkpipe(hdw->usb_dev,
3728 PVR2_CTL_READ_ENDPOINT),
3729 hdw->ctl_read_buffer,
3731 pvr2_ctl_read_complete,
3733 hdw->ctl_read_urb->actual_length = 0;
3734 hdw->ctl_read_pend_flag = !0;
3735 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3737 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3738 "Failed to submit read-control"
3739 " URB status=%d",status);
3740 hdw->ctl_read_pend_flag = 0;
3748 /* Now wait for all I/O to complete */
3749 hdw->cmd_debug_state = 4;
3750 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3751 wait_for_completion(&hdw->ctl_done);
3753 hdw->cmd_debug_state = 5;
3756 del_timer_sync(&timer);
3758 hdw->cmd_debug_state = 6;
3761 if (hdw->ctl_timeout_flag) {
3762 status = -ETIMEDOUT;
3764 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3765 "Timed out control-write");
3771 /* Validate results of write request */
3772 if ((hdw->ctl_write_urb->status != 0) &&
3773 (hdw->ctl_write_urb->status != -ENOENT) &&
3774 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3775 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3776 /* USB subsystem is reporting some kind of failure
3778 status = hdw->ctl_write_urb->status;
3780 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3781 "control-write URB failure,"
3787 if (hdw->ctl_write_urb->actual_length < write_len) {
3788 /* Failed to write enough data */
3791 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3792 "control-write URB short,"
3793 " expected=%d got=%d",
3795 hdw->ctl_write_urb->actual_length);
3801 /* Validate results of read request */
3802 if ((hdw->ctl_read_urb->status != 0) &&
3803 (hdw->ctl_read_urb->status != -ENOENT) &&
3804 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3805 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3806 /* USB subsystem is reporting some kind of failure
3808 status = hdw->ctl_read_urb->status;
3810 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3811 "control-read URB failure,"
3817 if (hdw->ctl_read_urb->actual_length < read_len) {
3818 /* Failed to read enough data */
3821 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3822 "control-read URB short,"
3823 " expected=%d got=%d",
3825 hdw->ctl_read_urb->actual_length);
3829 /* Transfer retrieved data out from internal buffer */
3830 for (idx = 0; idx < read_len; idx++) {
3831 ((unsigned char *)read_data)[idx] =
3832 hdw->ctl_read_buffer[idx];
3838 hdw->cmd_debug_state = 0;
3839 if ((status < 0) && (!probe_fl)) {
3840 pvr2_hdw_render_useless(hdw);
3846 int pvr2_send_request(struct pvr2_hdw *hdw,
3847 void *write_data,unsigned int write_len,
3848 void *read_data,unsigned int read_len)
3850 return pvr2_send_request_ex(hdw,HZ*4,0,
3851 write_data,write_len,
3852 read_data,read_len);
3856 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3859 unsigned int cnt = 1;
3860 unsigned int args = 0;
3861 LOCK_TAKE(hdw->ctl_lock);
3862 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3863 args = (cmdcode >> 8) & 0xffu;
3864 args = (args > 2) ? 2 : args;
3867 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3869 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3872 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3874 unsigned int ccnt,bcnt;
3878 ccnt = scnprintf(tbuf+bcnt,
3880 "Sending FX2 command 0x%x",cmdcode);
3882 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3883 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3884 ccnt = scnprintf(tbuf+bcnt,
3887 pvr2_fx2cmd_desc[idx].desc);
3893 ccnt = scnprintf(tbuf+bcnt,
3895 " (%u",hdw->cmd_buffer[1]);
3898 ccnt = scnprintf(tbuf+bcnt,
3900 ",%u",hdw->cmd_buffer[2]);
3903 ccnt = scnprintf(tbuf+bcnt,
3908 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3910 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3911 LOCK_GIVE(hdw->ctl_lock);
3916 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3920 LOCK_TAKE(hdw->ctl_lock);
3922 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3923 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3924 hdw->cmd_buffer[5] = 0;
3925 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3926 hdw->cmd_buffer[7] = reg & 0xff;
3929 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3931 LOCK_GIVE(hdw->ctl_lock);
3937 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3941 LOCK_TAKE(hdw->ctl_lock);
3943 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3944 hdw->cmd_buffer[1] = 0;
3945 hdw->cmd_buffer[2] = 0;
3946 hdw->cmd_buffer[3] = 0;
3947 hdw->cmd_buffer[4] = 0;
3948 hdw->cmd_buffer[5] = 0;
3949 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3950 hdw->cmd_buffer[7] = reg & 0xff;
3952 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3953 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3955 LOCK_GIVE(hdw->ctl_lock);
3961 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3963 if (!hdw->flag_ok) return;
3964 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3965 "Device being rendered inoperable");
3966 if (hdw->vid_stream) {
3967 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3970 trace_stbit("flag_ok",hdw->flag_ok);
3971 pvr2_hdw_state_sched(hdw);
3975 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3978 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3979 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3981 ret = usb_reset_device(hdw->usb_dev);
3982 usb_unlock_device(hdw->usb_dev);
3984 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3985 "Failed to lock USB device ret=%d",ret);
3987 if (init_pause_msec) {
3988 pvr2_trace(PVR2_TRACE_INFO,
3989 "Waiting %u msec for hardware to settle",
3991 msleep(init_pause_msec);
3997 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4003 if (!hdw->usb_dev) return;
4005 da = kmalloc(16, GFP_KERNEL);
4008 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4009 "Unable to allocate memory to control CPU reset");
4013 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4015 da[0] = val ? 0x01 : 0x00;
4017 /* Write the CPUCS register on the 8051. The lsb of the register
4018 is the reset bit; a 1 asserts reset while a 0 clears it. */
4019 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4020 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4022 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4023 "cpureset_assert(%d) error=%d",val,ret);
4024 pvr2_hdw_render_useless(hdw);
4031 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4033 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4037 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4039 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4044 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4046 pvr2_trace(PVR2_TRACE_INIT,
4047 "Requesting decoder reset");
4048 if (hdw->decoder_client_id) {
4049 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4051 pvr2_hdw_cx25840_vbi_hack(hdw);
4054 pvr2_trace(PVR2_TRACE_INIT,
4055 "Unable to reset decoder: nothing attached");
4060 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4063 return pvr2_issue_simple_cmd(hdw,
4064 FX2CMD_HCW_DEMOD_RESETIN |
4066 ((onoff ? 1 : 0) << 16));
4070 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4073 return pvr2_issue_simple_cmd(hdw,(onoff ?
4074 FX2CMD_ONAIR_DTV_POWER_ON :
4075 FX2CMD_ONAIR_DTV_POWER_OFF));
4079 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4082 return pvr2_issue_simple_cmd(hdw,(onoff ?
4083 FX2CMD_ONAIR_DTV_STREAMING_ON :
4084 FX2CMD_ONAIR_DTV_STREAMING_OFF));
4088 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4091 /* Compare digital/analog desired setting with current setting. If
4092 they don't match, fix it... */
4093 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4094 if (cmode == hdw->pathway_state) {
4095 /* They match; nothing to do */
4099 switch (hdw->hdw_desc->digital_control_scheme) {
4100 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4101 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4102 if (cmode == PVR2_PATHWAY_ANALOG) {
4103 /* If moving to analog mode, also force the decoder
4104 to reset. If no decoder is attached, then it's
4105 ok to ignore this because if/when the decoder
4106 attaches, it will reset itself at that time. */
4107 pvr2_hdw_cmd_decoder_reset(hdw);
4110 case PVR2_DIGITAL_SCHEME_ONAIR:
4111 /* Supposedly we should always have the power on whether in
4112 digital or analog mode. But for now do what appears to
4114 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4119 pvr2_hdw_untrip_unlocked(hdw);
4120 hdw->pathway_state = cmode;
4124 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4126 /* change some GPIO data
4128 * note: bit d7 of dir appears to control the LED,
4129 * so we shut it off here.
4133 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4135 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4137 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4141 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4143 static led_method_func led_methods[] = {
4144 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4149 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4151 unsigned int scheme_id;
4154 if ((!onoff) == (!hdw->led_on)) return;
4156 hdw->led_on = onoff != 0;
4158 scheme_id = hdw->hdw_desc->led_scheme;
4159 if (scheme_id < ARRAY_SIZE(led_methods)) {
4160 fp = led_methods[scheme_id];
4165 if (fp) (*fp)(hdw,onoff);
4169 /* Stop / start video stream transport */
4170 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4174 /* If we're in analog mode, then just issue the usual analog
4176 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4177 return pvr2_issue_simple_cmd(hdw,
4179 FX2CMD_STREAMING_ON :
4180 FX2CMD_STREAMING_OFF));
4181 /*Note: Not reached */
4184 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4185 /* Whoops, we don't know what mode we're in... */
4189 /* To get here we have to be in digital mode. The mechanism here
4190 is unfortunately different for different vendors. So we switch
4191 on the device's digital scheme attribute in order to figure out
4193 switch (hdw->hdw_desc->digital_control_scheme) {
4194 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4195 return pvr2_issue_simple_cmd(hdw,
4197 FX2CMD_HCW_DTV_STREAMING_ON :
4198 FX2CMD_HCW_DTV_STREAMING_OFF));
4199 case PVR2_DIGITAL_SCHEME_ONAIR:
4200 ret = pvr2_issue_simple_cmd(hdw,
4202 FX2CMD_STREAMING_ON :
4203 FX2CMD_STREAMING_OFF));
4204 if (ret) return ret;
4205 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4212 /* Evaluate whether or not state_pathway_ok can change */
4213 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4215 if (hdw->state_pathway_ok) {
4216 /* Nothing to do if pathway is already ok */
4219 if (!hdw->state_pipeline_idle) {
4220 /* Not allowed to change anything if pipeline is not idle */
4223 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4224 hdw->state_pathway_ok = !0;
4225 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4230 /* Evaluate whether or not state_encoder_ok can change */
4231 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4233 if (hdw->state_encoder_ok) return 0;
4234 if (hdw->flag_tripped) return 0;
4235 if (hdw->state_encoder_run) return 0;
4236 if (hdw->state_encoder_config) return 0;
4237 if (hdw->state_decoder_run) return 0;
4238 if (hdw->state_usbstream_run) return 0;
4239 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4240 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4241 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4245 if (pvr2_upload_firmware2(hdw) < 0) {
4246 hdw->flag_tripped = !0;
4247 trace_stbit("flag_tripped",hdw->flag_tripped);
4250 hdw->state_encoder_ok = !0;
4251 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4256 /* Evaluate whether or not state_encoder_config can change */
4257 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4259 if (hdw->state_encoder_config) {
4260 if (hdw->state_encoder_ok) {
4261 if (hdw->state_pipeline_req &&
4262 !hdw->state_pipeline_pause) return 0;
4264 hdw->state_encoder_config = 0;
4265 hdw->state_encoder_waitok = 0;
4266 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4267 /* paranoia - solve race if timer just completed */
4268 del_timer_sync(&hdw->encoder_wait_timer);
4270 if (!hdw->state_pathway_ok ||
4271 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4272 !hdw->state_encoder_ok ||
4273 !hdw->state_pipeline_idle ||
4274 hdw->state_pipeline_pause ||
4275 !hdw->state_pipeline_req ||
4276 !hdw->state_pipeline_config) {
4277 /* We must reset the enforced wait interval if
4278 anything has happened that might have disturbed
4279 the encoder. This should be a rare case. */
4280 if (timer_pending(&hdw->encoder_wait_timer)) {
4281 del_timer_sync(&hdw->encoder_wait_timer);
4283 if (hdw->state_encoder_waitok) {
4284 /* Must clear the state - therefore we did
4285 something to a state bit and must also
4287 hdw->state_encoder_waitok = 0;
4288 trace_stbit("state_encoder_waitok",
4289 hdw->state_encoder_waitok);
4294 if (!hdw->state_encoder_waitok) {
4295 if (!timer_pending(&hdw->encoder_wait_timer)) {
4296 /* waitok flag wasn't set and timer isn't
4297 running. Check flag once more to avoid
4298 a race then start the timer. This is
4299 the point when we measure out a minimal
4300 quiet interval before doing something to
4302 if (!hdw->state_encoder_waitok) {
4303 hdw->encoder_wait_timer.expires =
4304 jiffies + msecs_to_jiffies(
4305 TIME_MSEC_ENCODER_WAIT);
4306 add_timer(&hdw->encoder_wait_timer);
4309 /* We can't continue until we know we have been
4310 quiet for the interval measured by this
4314 pvr2_encoder_configure(hdw);
4315 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4317 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4322 /* Return true if the encoder should not be running. */
4323 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4325 if (!hdw->state_encoder_ok) {
4326 /* Encoder isn't healthy at the moment, so stop it. */
4329 if (!hdw->state_pathway_ok) {
4330 /* Mode is not understood at the moment (i.e. it wants to
4331 change), so encoder must be stopped. */
4335 switch (hdw->pathway_state) {
4336 case PVR2_PATHWAY_ANALOG:
4337 if (!hdw->state_decoder_run) {
4338 /* We're in analog mode and the decoder is not
4339 running; thus the encoder should be stopped as
4344 case PVR2_PATHWAY_DIGITAL:
4345 if (hdw->state_encoder_runok) {
4346 /* This is a funny case. We're in digital mode so
4347 really the encoder should be stopped. However
4348 if it really is running, only kill it after
4349 runok has been set. This gives a chance for the
4350 onair quirk to function (encoder must run
4351 briefly first, at least once, before onair
4352 digital streaming can work). */
4357 /* Unknown mode; so encoder should be stopped. */
4361 /* If we get here, we haven't found a reason to stop the
4367 /* Return true if the encoder should be running. */
4368 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4370 if (!hdw->state_encoder_ok) {
4371 /* Don't run the encoder if it isn't healthy... */
4374 if (!hdw->state_pathway_ok) {
4375 /* Don't run the encoder if we don't (yet) know what mode
4376 we need to be in... */
4380 switch (hdw->pathway_state) {
4381 case PVR2_PATHWAY_ANALOG:
4382 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4383 /* In analog mode, if the decoder is running, then
4388 case PVR2_PATHWAY_DIGITAL:
4389 if ((hdw->hdw_desc->digital_control_scheme ==
4390 PVR2_DIGITAL_SCHEME_ONAIR) &&
4391 !hdw->state_encoder_runok) {
4392 /* This is a quirk. OnAir hardware won't stream
4393 digital until the encoder has been run at least
4394 once, for a minimal period of time (empiricially
4395 measured to be 1/4 second). So if we're on
4396 OnAir hardware and the encoder has never been
4397 run at all, then start the encoder. Normal
4398 state machine logic in the driver will
4399 automatically handle the remaining bits. */
4404 /* For completeness (unknown mode; encoder won't run ever) */
4407 /* If we get here, then we haven't found any reason to run the
4408 encoder, so don't run it. */
4413 /* Evaluate whether or not state_encoder_run can change */
4414 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4416 if (hdw->state_encoder_run) {
4417 if (!state_check_disable_encoder_run(hdw)) return 0;
4418 if (hdw->state_encoder_ok) {
4419 del_timer_sync(&hdw->encoder_run_timer);
4420 if (pvr2_encoder_stop(hdw) < 0) return !0;
4422 hdw->state_encoder_run = 0;
4424 if (!state_check_enable_encoder_run(hdw)) return 0;
4425 if (pvr2_encoder_start(hdw) < 0) return !0;
4426 hdw->state_encoder_run = !0;
4427 if (!hdw->state_encoder_runok) {
4428 hdw->encoder_run_timer.expires = jiffies +
4429 msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4430 add_timer(&hdw->encoder_run_timer);
4433 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4438 /* Timeout function for quiescent timer. */
4439 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4441 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4442 hdw->state_decoder_quiescent = !0;
4443 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4444 hdw->state_stale = !0;
4445 queue_work(hdw->workqueue,&hdw->workpoll);
4449 /* Timeout function for decoder stabilization timer. */
4450 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4452 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4453 hdw->state_decoder_ready = !0;
4454 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4455 hdw->state_stale = !0;
4456 queue_work(hdw->workqueue, &hdw->workpoll);
4460 /* Timeout function for encoder wait timer. */
4461 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4463 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4464 hdw->state_encoder_waitok = !0;
4465 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4466 hdw->state_stale = !0;
4467 queue_work(hdw->workqueue,&hdw->workpoll);
4471 /* Timeout function for encoder run timer. */
4472 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4474 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4475 if (!hdw->state_encoder_runok) {
4476 hdw->state_encoder_runok = !0;
4477 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4478 hdw->state_stale = !0;
4479 queue_work(hdw->workqueue,&hdw->workpoll);
4484 /* Evaluate whether or not state_decoder_run can change */
4485 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4487 if (hdw->state_decoder_run) {
4488 if (hdw->state_encoder_ok) {
4489 if (hdw->state_pipeline_req &&
4490 !hdw->state_pipeline_pause &&
4491 hdw->state_pathway_ok) return 0;
4493 if (!hdw->flag_decoder_missed) {
4494 pvr2_decoder_enable(hdw,0);
4496 hdw->state_decoder_quiescent = 0;
4497 hdw->state_decoder_run = 0;
4498 /* paranoia - solve race if timer(s) just completed */
4499 del_timer_sync(&hdw->quiescent_timer);
4500 /* Kill the stabilization timer, in case we're killing the
4501 encoder before the previous stabilization interval has
4502 been properly timed. */
4503 del_timer_sync(&hdw->decoder_stabilization_timer);
4504 hdw->state_decoder_ready = 0;
4506 if (!hdw->state_decoder_quiescent) {
4507 if (!timer_pending(&hdw->quiescent_timer)) {
4508 /* We don't do something about the
4509 quiescent timer until right here because
4510 we also want to catch cases where the
4511 decoder was already not running (like
4512 after initialization) as opposed to
4513 knowing that we had just stopped it.
4514 The second flag check is here to cover a
4515 race - the timer could have run and set
4516 this flag just after the previous check
4517 but before we did the pending check. */
4518 if (!hdw->state_decoder_quiescent) {
4519 hdw->quiescent_timer.expires =
4520 jiffies + msecs_to_jiffies(
4521 TIME_MSEC_DECODER_WAIT);
4522 add_timer(&hdw->quiescent_timer);
4525 /* Don't allow decoder to start again until it has
4526 been quiesced first. This little detail should
4527 hopefully further stabilize the encoder. */
4530 if (!hdw->state_pathway_ok ||
4531 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4532 !hdw->state_pipeline_req ||
4533 hdw->state_pipeline_pause ||
4534 !hdw->state_pipeline_config ||
4535 !hdw->state_encoder_config ||
4536 !hdw->state_encoder_ok) return 0;
4537 del_timer_sync(&hdw->quiescent_timer);
4538 if (hdw->flag_decoder_missed) return 0;
4539 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4540 hdw->state_decoder_quiescent = 0;
4541 hdw->state_decoder_ready = 0;
4542 hdw->state_decoder_run = !0;
4543 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4544 hdw->decoder_stabilization_timer.expires =
4545 jiffies + msecs_to_jiffies(
4546 TIME_MSEC_DECODER_STABILIZATION_WAIT);
4547 add_timer(&hdw->decoder_stabilization_timer);
4549 hdw->state_decoder_ready = !0;
4552 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4553 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4554 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4559 /* Evaluate whether or not state_usbstream_run can change */
4560 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4562 if (hdw->state_usbstream_run) {
4564 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4565 fl = (hdw->state_encoder_ok &&
4566 hdw->state_encoder_run);
4567 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4568 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4569 fl = hdw->state_encoder_ok;
4572 hdw->state_pipeline_req &&
4573 !hdw->state_pipeline_pause &&
4574 hdw->state_pathway_ok) {
4577 pvr2_hdw_cmd_usbstream(hdw,0);
4578 hdw->state_usbstream_run = 0;
4580 if (!hdw->state_pipeline_req ||
4581 hdw->state_pipeline_pause ||
4582 !hdw->state_pathway_ok) return 0;
4583 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4584 if (!hdw->state_encoder_ok ||
4585 !hdw->state_encoder_run) return 0;
4586 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4587 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4588 if (!hdw->state_encoder_ok) return 0;
4589 if (hdw->state_encoder_run) return 0;
4590 if (hdw->hdw_desc->digital_control_scheme ==
4591 PVR2_DIGITAL_SCHEME_ONAIR) {
4592 /* OnAir digital receivers won't stream
4593 unless the analog encoder has run first.
4594 Why? I have no idea. But don't even
4595 try until we know the analog side is
4596 known to have run. */
4597 if (!hdw->state_encoder_runok) return 0;
4600 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4601 hdw->state_usbstream_run = !0;
4603 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4608 /* Attempt to configure pipeline, if needed */
4609 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4611 if (hdw->state_pipeline_config ||
4612 hdw->state_pipeline_pause) return 0;
4613 pvr2_hdw_commit_execute(hdw);
4618 /* Update pipeline idle and pipeline pause tracking states based on other
4619 inputs. This must be called whenever the other relevant inputs have
4621 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4625 /* Update pipeline state */
4626 st = !(hdw->state_encoder_run ||
4627 hdw->state_decoder_run ||
4628 hdw->state_usbstream_run ||
4629 (!hdw->state_decoder_quiescent));
4630 if (!st != !hdw->state_pipeline_idle) {
4631 hdw->state_pipeline_idle = st;
4634 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4635 hdw->state_pipeline_pause = 0;
4642 typedef int (*state_eval_func)(struct pvr2_hdw *);
4644 /* Set of functions to be run to evaluate various states in the driver. */
4645 static const state_eval_func eval_funcs[] = {
4646 state_eval_pathway_ok,
4647 state_eval_pipeline_config,
4648 state_eval_encoder_ok,
4649 state_eval_encoder_config,
4650 state_eval_decoder_run,
4651 state_eval_encoder_run,
4652 state_eval_usbstream_run,
4656 /* Process various states and return true if we did anything interesting. */
4657 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4660 int state_updated = 0;
4663 if (!hdw->state_stale) return 0;
4664 if ((hdw->fw1_state != FW1_STATE_OK) ||
4666 hdw->state_stale = 0;
4669 /* This loop is the heart of the entire driver. It keeps trying to
4670 evaluate various bits of driver state until nothing changes for
4671 one full iteration. Each "bit of state" tracks some global
4672 aspect of the driver, e.g. whether decoder should run, if
4673 pipeline is configured, usb streaming is on, etc. We separately
4674 evaluate each of those questions based on other driver state to
4675 arrive at the correct running configuration. */
4678 state_update_pipeline_state(hdw);
4679 /* Iterate over each bit of state */
4680 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4681 if ((*eval_funcs[i])(hdw)) {
4684 state_update_pipeline_state(hdw);
4687 } while (check_flag && hdw->flag_ok);
4688 hdw->state_stale = 0;
4689 trace_stbit("state_stale",hdw->state_stale);
4690 return state_updated;
4694 static unsigned int print_input_mask(unsigned int msk,
4695 char *buf,unsigned int acnt)
4697 unsigned int idx,ccnt;
4698 unsigned int tcnt = 0;
4699 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4700 if (!((1 << idx) & msk)) continue;
4701 ccnt = scnprintf(buf+tcnt,
4705 control_values_input[idx]);
4712 static const char *pvr2_pathway_state_name(int id)
4715 case PVR2_PATHWAY_ANALOG: return "analog";
4716 case PVR2_PATHWAY_DIGITAL: return "digital";
4717 default: return "unknown";
4722 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4723 char *buf,unsigned int acnt)
4729 "driver:%s%s%s%s%s <mode=%s>",
4730 (hdw->flag_ok ? " <ok>" : " <fail>"),
4731 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4732 (hdw->flag_disconnected ? " <disconnected>" :
4734 (hdw->flag_tripped ? " <tripped>" : ""),
4735 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4736 pvr2_pathway_state_name(hdw->pathway_state));
4741 "pipeline:%s%s%s%s",
4742 (hdw->state_pipeline_idle ? " <idle>" : ""),
4743 (hdw->state_pipeline_config ?
4744 " <configok>" : " <stale>"),
4745 (hdw->state_pipeline_req ? " <req>" : ""),
4746 (hdw->state_pipeline_pause ? " <pause>" : ""));
4750 "worker:%s%s%s%s%s%s%s",
4751 (hdw->state_decoder_run ?
4752 (hdw->state_decoder_ready ?
4753 "<decode:run>" : " <decode:start>") :
4754 (hdw->state_decoder_quiescent ?
4755 "" : " <decode:stop>")),
4756 (hdw->state_decoder_quiescent ?
4757 " <decode:quiescent>" : ""),
4758 (hdw->state_encoder_ok ?
4759 "" : " <encode:init>"),
4760 (hdw->state_encoder_run ?
4761 (hdw->state_encoder_runok ?
4763 " <encode:firstrun>") :
4764 (hdw->state_encoder_runok ?
4766 " <encode:virgin>")),
4767 (hdw->state_encoder_config ?
4768 " <encode:configok>" :
4769 (hdw->state_encoder_waitok ?
4770 "" : " <encode:waitok>")),
4771 (hdw->state_usbstream_run ?
4772 " <usb:run>" : " <usb:stop>"),
4773 (hdw->state_pathway_ok ?
4774 " <pathway:ok>" : ""));
4779 pvr2_get_state_name(hdw->master_state));
4781 unsigned int tcnt = 0;
4784 ccnt = scnprintf(buf,
4786 "Hardware supported inputs: ");
4788 tcnt += print_input_mask(hdw->input_avail_mask,
4791 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4792 ccnt = scnprintf(buf+tcnt,
4794 "; allowed inputs: ");
4796 tcnt += print_input_mask(hdw->input_allowed_mask,
4803 struct pvr2_stream_stats stats;
4804 if (!hdw->vid_stream) break;
4805 pvr2_stream_get_stats(hdw->vid_stream,
4811 " URBs: queued=%u idle=%u ready=%u"
4812 " processed=%u failed=%u",
4813 stats.bytes_processed,
4814 stats.buffers_in_queue,
4815 stats.buffers_in_idle,
4816 stats.buffers_in_ready,
4817 stats.buffers_processed,
4818 stats.buffers_failed);
4821 unsigned int id = hdw->ir_scheme_active;
4822 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4823 (id >= ARRAY_SIZE(ir_scheme_names) ?
4824 "?" : ir_scheme_names[id]));
4832 /* Generate report containing info about attached sub-devices and attached
4833 i2c clients, including an indication of which attached i2c clients are
4834 actually sub-devices. */
4835 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4836 char *buf, unsigned int acnt)
4838 struct v4l2_subdev *sd;
4839 unsigned int tcnt = 0;
4841 struct i2c_client *client;
4845 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4847 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4850 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4852 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
4855 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4856 " (unknown id=%u):", id);
4859 client = v4l2_get_subdevdata(sd);
4861 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4862 " %s @ %02x\n", client->name,
4866 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4867 " no i2c client\n");
4875 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4876 char *buf,unsigned int acnt)
4878 unsigned int bcnt,ccnt,idx;
4880 LOCK_TAKE(hdw->big_lock);
4881 for (idx = 0; ; idx++) {
4882 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4884 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4886 buf[0] = '\n'; ccnt = 1;
4887 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4889 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4890 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4891 LOCK_GIVE(hdw->big_lock);
4896 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4899 unsigned int idx, ccnt;
4900 unsigned int lcnt, ucnt;
4902 for (idx = 0; ; idx++) {
4903 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4905 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4907 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4909 while (ucnt < ccnt) {
4911 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4914 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4920 /* Evaluate and update the driver's current state, taking various actions
4921 as appropriate for the update. */
4922 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4925 int state_updated = 0;
4926 int callback_flag = 0;
4929 pvr2_trace(PVR2_TRACE_STBITS,
4930 "Drive state check START");
4931 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4932 pvr2_hdw_state_log_state(hdw);
4935 /* Process all state and get back over disposition */
4936 state_updated = pvr2_hdw_state_update(hdw);
4938 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4940 /* Update master state based upon all other states. */
4941 if (!hdw->flag_ok) {
4942 st = PVR2_STATE_DEAD;
4943 } else if (hdw->fw1_state != FW1_STATE_OK) {
4944 st = PVR2_STATE_COLD;
4945 } else if ((analog_mode ||
4946 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4947 !hdw->state_encoder_ok) {
4948 st = PVR2_STATE_WARM;
4949 } else if (hdw->flag_tripped ||
4950 (analog_mode && hdw->flag_decoder_missed)) {
4951 st = PVR2_STATE_ERROR;
4952 } else if (hdw->state_usbstream_run &&
4954 (hdw->state_encoder_run && hdw->state_decoder_run))) {
4955 st = PVR2_STATE_RUN;
4957 st = PVR2_STATE_READY;
4959 if (hdw->master_state != st) {
4960 pvr2_trace(PVR2_TRACE_STATE,
4961 "Device state change from %s to %s",
4962 pvr2_get_state_name(hdw->master_state),
4963 pvr2_get_state_name(st));
4964 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4965 hdw->master_state = st;
4969 if (state_updated) {
4970 /* Trigger anyone waiting on any state changes here. */
4971 wake_up(&hdw->state_wait_data);
4974 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4975 pvr2_hdw_state_log_state(hdw);
4977 pvr2_trace(PVR2_TRACE_STBITS,
4978 "Drive state check DONE callback=%d",callback_flag);
4980 return callback_flag;
4984 /* Cause kernel thread to check / update driver state */
4985 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4987 if (hdw->state_stale) return;
4988 hdw->state_stale = !0;
4989 trace_stbit("state_stale",hdw->state_stale);
4990 queue_work(hdw->workqueue,&hdw->workpoll);
4994 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4996 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5000 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5002 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5006 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5008 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5012 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5017 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5018 if (ret) return ret;
5019 nval = (cval & ~msk) | (val & msk);
5020 pvr2_trace(PVR2_TRACE_GPIO,
5021 "GPIO direction changing 0x%x:0x%x"
5022 " from 0x%x to 0x%x",
5026 pvr2_trace(PVR2_TRACE_GPIO,
5027 "GPIO direction changing to 0x%x",nval);
5029 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5033 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5038 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5039 if (ret) return ret;
5040 nval = (cval & ~msk) | (val & msk);
5041 pvr2_trace(PVR2_TRACE_GPIO,
5042 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5046 pvr2_trace(PVR2_TRACE_GPIO,
5047 "GPIO output changing to 0x%x",nval);
5049 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5053 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5055 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5056 memset(vtp, 0, sizeof(*vtp));
5057 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5058 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5059 hdw->tuner_signal_stale = 0;
5060 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5061 using v4l2-subdev - therefore we can't support that AT ALL right
5062 now. (Of course, no sub-drivers seem to implement it either.
5063 But now it's a a chicken and egg problem...) */
5064 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5065 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5066 " type=%u strength=%u audio=0x%x cap=0x%x"
5069 vtp->signal, vtp->rxsubchans, vtp->capability,
5070 vtp->rangelow, vtp->rangehigh);
5072 /* We have to do this to avoid getting into constant polling if
5073 there's nobody to answer a poll of cropcap info. */
5074 hdw->cropcap_stale = 0;
5078 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5080 return hdw->input_avail_mask;
5084 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5086 return hdw->input_allowed_mask;
5090 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5092 if (hdw->input_val != v) {
5094 hdw->input_dirty = !0;
5097 /* Handle side effects - if we switch to a mode that needs the RF
5098 tuner, then select the right frequency choice as well and mark
5100 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5101 hdw->freqSelector = 0;
5102 hdw->freqDirty = !0;
5103 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5104 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5105 hdw->freqSelector = 1;
5106 hdw->freqDirty = !0;
5112 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5113 unsigned int change_mask,
5114 unsigned int change_val)
5117 unsigned int nv,m,idx;
5118 LOCK_TAKE(hdw->big_lock);
5120 nv = hdw->input_allowed_mask & ~change_mask;
5121 nv |= (change_val & change_mask);
5122 nv &= hdw->input_avail_mask;
5124 /* No legal modes left; return error instead. */
5128 hdw->input_allowed_mask = nv;
5129 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5130 /* Current mode is still in the allowed mask, so
5134 /* Select and switch to a mode that is still in the allowed
5136 if (!hdw->input_allowed_mask) {
5137 /* Nothing legal; give up */
5140 m = hdw->input_allowed_mask;
5141 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5142 if (!((1 << idx) & m)) continue;
5143 pvr2_hdw_set_input(hdw,idx);
5147 LOCK_GIVE(hdw->big_lock);
5152 /* Find I2C address of eeprom */
5153 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5156 LOCK_TAKE(hdw->ctl_lock); do {
5157 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5158 result = pvr2_send_request(hdw,
5161 if (result < 0) break;
5162 result = hdw->cmd_buffer[0];
5163 } while(0); LOCK_GIVE(hdw->ctl_lock);