1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Frontend part of the Linux driver for the Afatech 9005
3 * USB1.1 DVB-T receiver.
5 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
7 * Thanks to Afatech who kindly provided information.
9 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
15 #include <asm/div64.h>
17 struct af9005_fe_state {
18 struct dvb_usb_device *d;
21 /* retraining parameters */
26 u16 original_aci0_if_top;
27 u16 original_aci1_if_top;
28 u16 original_aci0_if_min;
29 u8 original_if_unplug_th;
30 u8 original_rf_unplug_th;
31 u8 original_dtop_if_unplug_th;
32 u8 original_dtop_rf_unplug_th;
35 u32 pre_vit_error_count;
36 u32 pre_vit_bit_count;
38 u32 post_vit_error_count;
39 u32 post_vit_bit_count;
45 unsigned long next_status_check;
46 struct dvb_frontend frontend;
49 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
50 u16 reglo, u8 pos, u8 len, u16 value)
54 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
56 return af9005_write_register_bits(d, reghi, pos, len,
57 (u8) ((value & 0x300) >> 8));
60 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
61 u16 reglo, u8 pos, u8 len, u16 * value)
66 if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
68 if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
72 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
75 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
78 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
81 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
84 err("invalid pos in read word agc");
91 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
93 struct af9005_fe_state *state = fe->demodulator_priv;
99 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
100 fec_vtb_rsd_mon_en_pos,
101 fec_vtb_rsd_mon_en_len, &temp);
106 af9005_read_register_bits(state->d,
107 xd_p_reg_ofsm_read_rbc_en,
108 reg_ofsm_read_rbc_en_pos,
109 reg_ofsm_read_rbc_en_len, &temp);
119 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
120 u32 * post_err_count,
124 struct af9005_fe_state *state = fe->demodulator_priv;
128 u8 temp, temp0, temp1, temp2;
134 /* check if error bit count is ready */
136 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
137 fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
142 deb_info("rsd counter not ready\n");
145 /* get abort count */
147 af9005_read_ofdm_register(state->d,
148 xd_r_fec_rsd_abort_packet_cnt_7_0,
153 af9005_read_ofdm_register(state->d,
154 xd_r_fec_rsd_abort_packet_cnt_15_8,
158 loc_abort_count = ((u16) temp1 << 8) + temp0;
160 /* get error count */
162 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
167 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
172 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
176 err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
177 *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
179 /* get RSD packet number */
181 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
186 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
190 cw_count = ((u32) temp1 << 8) + temp0;
192 err("wrong RSD packet count");
195 deb_info("POST abort count %d err count %d rsd packets %d\n",
196 loc_abort_count, err_count, cw_count);
197 *post_cw_count = cw_count - (u32) loc_abort_count;
198 *abort_count = loc_abort_count;
203 static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
204 u32 * post_err_count, u32 * post_cw_count,
207 u32 loc_cw_count = 0, loc_err_count;
208 u16 loc_abort_count = 0;
212 af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
216 *post_err_count = loc_err_count;
217 *post_cw_count = loc_cw_count * 204 * 8;
218 *abort_count = loc_abort_count;
223 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
227 struct af9005_fe_state *state = fe->demodulator_priv;
228 u8 temp, temp0, temp1, temp2;
229 u32 super_frame_count, x, bits;
233 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
234 fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
239 deb_info("viterbi counter not ready\n");
240 return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
243 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
248 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
253 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
257 *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
260 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
265 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
269 super_frame_count = ((u32) temp1 << 8) + temp0;
270 if (super_frame_count == 0) {
271 deb_info("super frame count 0\n");
277 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
278 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
285 } else if (temp == 1) {
289 err("Invalid fft mode");
293 /* read modulation mode */
295 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
296 reg_tpsd_const_pos, reg_tpsd_const_len,
311 err("invalid modulation mode");
314 *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
315 deb_info("PRE err count %d frame count %d bit count %d\n",
316 *pre_err_count, super_frame_count, *pre_bit_count);
320 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
322 struct af9005_fe_state *state = fe->demodulator_priv;
325 /* set super frame count to 1 */
327 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
331 ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
335 /* reset pre viterbi error count */
337 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
338 fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
344 static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
346 struct af9005_fe_state *state = fe->demodulator_priv;
349 /* set packet unit */
351 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
356 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
360 /* reset post viterbi error count */
362 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
363 fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
369 static int af9005_get_statistic(struct dvb_frontend *fe)
371 struct af9005_fe_state *state = fe->demodulator_priv;
372 int ret, fecavailable;
373 u64 numerator, denominator;
375 deb_info("GET STATISTIC\n");
376 ret = af9005_is_fecmon_available(fe, &fecavailable);
380 deb_info("fecmon not available\n");
384 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
385 &state->pre_vit_bit_count);
387 af9005_reset_pre_viterbi(fe);
388 if (state->pre_vit_bit_count > 0) {
389 /* according to v 0.0.4 of the dvb api ber should be a multiple
390 of 10E-9 so we have to multiply the error count by
393 (u64) state->pre_vit_error_count * (u64) 1000000000;
394 denominator = (u64) state->pre_vit_bit_count;
395 state->ber = do_div(numerator, denominator);
397 state->ber = 0xffffffff;
401 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
402 &state->post_vit_bit_count,
403 &state->abort_count);
405 ret = af9005_reset_post_viterbi(fe);
406 state->unc += state->abort_count;
413 static int af9005_fe_refresh_state(struct dvb_frontend *fe)
415 struct af9005_fe_state *state = fe->demodulator_priv;
416 if (time_after(jiffies, state->next_status_check)) {
417 deb_info("REFRESH STATE\n");
420 if (af9005_get_statistic(fe))
421 err("get_statistic_failed");
422 state->next_status_check = jiffies + 250 * HZ / 1000;
427 static int af9005_fe_read_status(struct dvb_frontend *fe,
428 enum fe_status *stat)
430 struct af9005_fe_state *state = fe->demodulator_priv;
434 if (fe->ops.tuner_ops.release == NULL)
438 ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
439 agc_lock_pos, agc_lock_len, &temp);
443 *stat |= FE_HAS_SIGNAL;
445 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
446 fd_tpsd_lock_pos, fd_tpsd_lock_len,
451 *stat |= FE_HAS_CARRIER;
453 ret = af9005_read_register_bits(state->d,
454 xd_r_mp2if_sync_byte_locked,
455 mp2if_sync_byte_locked_pos,
456 mp2if_sync_byte_locked_pos, &temp);
460 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
462 af9005_led_control(state->d, *stat & FE_HAS_LOCK);
465 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
466 reg_strong_sginal_detected_pos,
467 reg_strong_sginal_detected_len, &temp);
470 if (temp != state->strong) {
471 deb_info("adjust for strong signal %d\n", temp);
472 state->strong = temp;
477 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
479 struct af9005_fe_state *state = fe->demodulator_priv;
480 if (fe->ops.tuner_ops.release == NULL)
482 af9005_fe_refresh_state(fe);
487 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
489 struct af9005_fe_state *state = fe->demodulator_priv;
490 if (fe->ops.tuner_ops.release == NULL)
492 af9005_fe_refresh_state(fe);
497 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
500 struct af9005_fe_state *state = fe->demodulator_priv;
504 if (fe->ops.tuner_ops.release == NULL)
507 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
512 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
516 /* this value has no real meaning, but i don't have the tables that relate
517 the rf and if gain with the dbm, so I just scale the value */
518 *strength = (512 - rf_gain - if_gain) << 7;
522 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
524 /* the snr can be derived from the ber and the modulation
525 but I don't think this kind of complex calculations belong
526 in the driver. I may be wrong.... */
530 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw)
532 u8 temp0, temp1, temp2, temp3, buf[4];
534 u32 NS_coeff1_2048Nu;
535 u32 NS_coeff1_8191Nu;
536 u32 NS_coeff1_8192Nu;
537 u32 NS_coeff1_8193Nu;
543 NS_coeff1_2048Nu = 0x2ADB6DC;
544 NS_coeff1_8191Nu = 0xAB7313;
545 NS_coeff1_8192Nu = 0xAB6DB7;
546 NS_coeff1_8193Nu = 0xAB685C;
547 NS_coeff2_2k = 0x156DB6E;
548 NS_coeff2_8k = 0x55B6DC;
552 NS_coeff1_2048Nu = 0x3200001;
553 NS_coeff1_8191Nu = 0xC80640;
554 NS_coeff1_8192Nu = 0xC80000;
555 NS_coeff1_8193Nu = 0xC7F9C0;
556 NS_coeff2_2k = 0x1900000;
557 NS_coeff2_8k = 0x640000;
561 NS_coeff1_2048Nu = 0x3924926;
562 NS_coeff1_8191Nu = 0xE4996E;
563 NS_coeff1_8192Nu = 0xE49249;
564 NS_coeff1_8193Nu = 0xE48B25;
565 NS_coeff2_2k = 0x1C92493;
566 NS_coeff2_8k = 0x724925;
569 err("Invalid bandwidth %d.", bw);
574 * write NS_coeff1_2048Nu
577 temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
578 temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
579 temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
580 temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
582 /* big endian to make 8051 happy */
588 /* cfoe_NS_2k_coeff1_25_24 */
589 ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
593 /* cfoe_NS_2k_coeff1_23_16 */
594 ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
598 /* cfoe_NS_2k_coeff1_15_8 */
599 ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
603 /* cfoe_NS_2k_coeff1_7_0 */
604 ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
612 temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
613 temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
614 temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
615 temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
617 /* big endian to make 8051 happy */
623 ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
627 ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
631 ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
635 ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
640 * write NS_coeff1_8191Nu
643 temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
644 temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
645 temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
646 temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
648 /* big endian to make 8051 happy */
654 ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
658 ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
662 ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
666 ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
671 * write NS_coeff1_8192Nu
674 temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
675 temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
676 temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
677 temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
679 /* big endian to make 8051 happy */
685 ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
689 ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
693 ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
697 ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
702 * write NS_coeff1_8193Nu
705 temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
706 temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
707 temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
708 temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
710 /* big endian to make 8051 happy */
716 ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
720 ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
724 ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
728 ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
736 temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
737 temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
738 temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
739 temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
741 /* big endian to make 8051 happy */
747 ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
751 ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
755 ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
759 ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
764 static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw)
778 err("Invalid bandwidth %d.", bw);
781 return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
785 static int af9005_fe_power(struct dvb_frontend *fe, int on)
787 struct af9005_fe_state *state = fe->demodulator_priv;
790 deb_info("power %s tuner\n", on ? "on" : "off");
791 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
795 static struct mt2060_config af9005_mt2060_config = {
799 static struct qt1010_config af9005_qt1010_config = {
803 static int af9005_fe_init(struct dvb_frontend *fe)
805 struct af9005_fe_state *state = fe->demodulator_priv;
806 struct dvb_usb_adapter *adap = fe->dvb->priv;
807 int ret, i, scriptlen;
808 u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
812 deb_info("in af9005_fe_init\n");
817 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
820 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
822 /* clear ofdm reset */
823 deb_info("clear ofdm reset\n");
824 for (i = 0; i < 150; i++) {
826 af9005_read_ofdm_register(state->d,
827 xd_I2C_reg_ofdm_rst, &temp)))
829 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
838 write xd_g_reg_ofsm_clk 7
843 write xd_g_reg_ofsm_clk 0
846 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
849 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
853 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
856 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
859 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
863 temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
865 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
866 reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
868 ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
869 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
873 /* don't know what register aefc is, but this is what the windows driver does */
874 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
878 /* set stand alone chip */
879 deb_info("set stand alone chip\n");
881 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
882 reg_dca_stand_alone_pos,
883 reg_dca_stand_alone_len, 1)))
886 /* set dca upper & lower chip */
887 deb_info("set dca upper & lower chip\n");
889 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
890 reg_dca_upper_chip_pos,
891 reg_dca_upper_chip_len, 0)))
894 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
895 reg_dca_lower_chip_pos,
896 reg_dca_lower_chip_len, 0)))
899 /* set 2wire master clock to 0x14 (for 60KHz) */
900 deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
902 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
905 /* clear dca enable chip */
906 deb_info("clear dca enable chip\n");
908 af9005_write_register_bits(state->d, xd_p_reg_dca_en,
909 reg_dca_en_pos, reg_dca_en_len, 0)))
911 /* FIXME these are register bits, but I don't know which ones */
912 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
915 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
919 /* init other parameters: program cfoe and select bandwidth */
920 deb_info("program cfoe\n");
921 ret = af9005_fe_program_cfoe(state->d, 6000000);
924 /* set read-update bit for modulation */
925 deb_info("set read-update bit for modulation\n");
927 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
928 reg_feq_read_update_pos,
929 reg_feq_read_update_len, 1)))
932 /* sample code has a set MPEG TS code here
933 but sniffing reveals that it doesn't do it */
935 /* set read-update bit to 1 for DCA modulation */
936 deb_info("set read-update bit 1 for DCA modulation\n");
938 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
939 reg_dca_read_update_pos,
940 reg_dca_read_update_len, 1)))
943 /* enable fec monitor */
944 deb_info("enable fec monitor\n");
946 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
947 fec_vtb_rsd_mon_en_pos,
948 fec_vtb_rsd_mon_en_len, 1)))
951 /* FIXME should be register bits, I don't know which ones */
952 ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
954 /* set api_retrain_never_freeze */
955 deb_info("set api_retrain_never_freeze\n");
956 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
959 /* load init script */
961 err("Missing Free init script\n");
962 return scriptlen = ret = -EINVAL;
966 state->original_fcw =
967 ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
970 /* save original TOPs */
971 deb_info("save original TOPs\n");
975 af9005_read_word_agc(state->d,
976 xd_p_reg_aagc_rf_top_numerator_9_8,
977 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
978 &state->original_rf_top);
984 af9005_read_word_agc(state->d,
985 xd_p_reg_aagc_if_top_numerator_9_8,
986 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
987 &state->original_if_top);
993 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
994 &state->original_aci0_if_top);
1000 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1001 &state->original_aci1_if_top);
1005 /* attach tuner and init */
1006 if (fe->ops.tuner_ops.release == NULL) {
1007 /* read tuner and board id from eeprom */
1008 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1010 err("Impossible to read EEPROM\n");
1013 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1015 case 2: /* MT2060 */
1016 /* read if1 from eeprom */
1017 ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1019 err("Impossible to read EEPROM\n");
1022 if1 = (u16) (buf[0] << 8) + buf[1];
1023 if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1024 &af9005_mt2060_config, if1) == NULL) {
1025 deb_info("MT2060 attach failed\n");
1029 case 3: /* QT1010 */
1030 case 9: /* QT1010B */
1031 if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1032 &af9005_qt1010_config) ==NULL) {
1033 deb_info("QT1010 attach failed\n");
1038 err("Unsupported tuner type %d", buf[0]);
1041 ret = fe->ops.tuner_ops.init(fe);
1046 deb_info("profit!\n");
1050 static int af9005_fe_sleep(struct dvb_frontend *fe)
1052 return af9005_fe_power(fe, 0);
1055 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1057 struct af9005_fe_state *state = fe->demodulator_priv;
1065 af9005_led_control(state->d, 0);
1070 static int af9005_fe_set_frontend(struct dvb_frontend *fe)
1072 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1073 struct af9005_fe_state *state = fe->demodulator_priv;
1075 u8 temp, temp0, temp1, temp2;
1077 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1079 if (fe->ops.tuner_ops.release == NULL) {
1080 err("Tuner not attached");
1084 deb_info("turn off led\n");
1085 /* not in the log */
1086 ret = af9005_led_control(state->d, 0);
1089 /* not sure about the bits */
1090 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1094 /* set FCW to default value */
1095 deb_info("set FCW to default value\n");
1096 temp0 = (u8) (state->original_fcw & 0x000000ff);
1097 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1098 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1099 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1102 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1105 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1109 /* restore original TOPs */
1110 deb_info("restore original TOPs\n");
1112 af9005_write_word_agc(state->d,
1113 xd_p_reg_aagc_rf_top_numerator_9_8,
1114 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1115 state->original_rf_top);
1119 af9005_write_word_agc(state->d,
1120 xd_p_reg_aagc_if_top_numerator_9_8,
1121 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1122 state->original_if_top);
1126 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1127 state->original_aci0_if_top);
1131 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1132 state->original_aci1_if_top);
1136 /* select bandwidth */
1137 deb_info("select bandwidth");
1138 ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz);
1141 ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz);
1145 /* clear easy mode flag */
1146 deb_info("clear easy mode flag\n");
1147 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1151 /* set unplug threshold to original value */
1152 deb_info("set unplug threshold to original value\n");
1154 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1155 state->original_if_unplug_th);
1159 deb_info("set tuner\n");
1160 ret = fe->ops.tuner_ops.set_params(fe);
1165 deb_info("trigger ofsm\n");
1167 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1171 /* clear retrain and freeze flag */
1172 deb_info("clear retrain and freeze flag\n");
1174 af9005_write_register_bits(state->d,
1175 xd_p_reg_api_retrain_request,
1176 reg_api_retrain_request_pos, 2, 0);
1180 /* reset pre viterbi and post viterbi registers and statistics */
1181 af9005_reset_pre_viterbi(fe);
1182 af9005_reset_post_viterbi(fe);
1183 state->pre_vit_error_count = 0;
1184 state->pre_vit_bit_count = 0;
1186 state->post_vit_error_count = 0;
1187 /* state->unc = 0; commented out since it should be ever increasing */
1188 state->abort_count = 0;
1190 state->next_status_check = jiffies;
1196 static int af9005_fe_get_frontend(struct dvb_frontend *fe,
1197 struct dtv_frontend_properties *fep)
1199 struct af9005_fe_state *state = fe->demodulator_priv;
1205 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1206 reg_tpsd_const_pos, reg_tpsd_const_len,
1210 deb_info("===== fe_get_frontend_legacy = =============\n");
1211 deb_info("CONSTELLATION ");
1214 fep->modulation = QPSK;
1218 fep->modulation = QAM_16;
1219 deb_info("QAM_16\n");
1222 fep->modulation = QAM_64;
1223 deb_info("QAM_64\n");
1227 /* tps hierarchy and alpha value */
1229 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1230 reg_tpsd_hier_pos, reg_tpsd_hier_len,
1234 deb_info("HIERARCHY ");
1237 fep->hierarchy = HIERARCHY_NONE;
1241 fep->hierarchy = HIERARCHY_1;
1245 fep->hierarchy = HIERARCHY_2;
1249 fep->hierarchy = HIERARCHY_4;
1254 /* high/low priority */
1256 af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1257 reg_dec_pri_pos, reg_dec_pri_len, &temp);
1260 /* if temp is set = high priority */
1261 deb_info("PRIORITY %s\n", temp ? "high" : "low");
1265 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1266 reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1270 deb_info("CODERATE HP ");
1273 fep->code_rate_HP = FEC_1_2;
1274 deb_info("FEC_1_2\n");
1277 fep->code_rate_HP = FEC_2_3;
1278 deb_info("FEC_2_3\n");
1281 fep->code_rate_HP = FEC_3_4;
1282 deb_info("FEC_3_4\n");
1285 fep->code_rate_HP = FEC_5_6;
1286 deb_info("FEC_5_6\n");
1289 fep->code_rate_HP = FEC_7_8;
1290 deb_info("FEC_7_8\n");
1296 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1297 reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1301 deb_info("CODERATE LP ");
1304 fep->code_rate_LP = FEC_1_2;
1305 deb_info("FEC_1_2\n");
1308 fep->code_rate_LP = FEC_2_3;
1309 deb_info("FEC_2_3\n");
1312 fep->code_rate_LP = FEC_3_4;
1313 deb_info("FEC_3_4\n");
1316 fep->code_rate_LP = FEC_5_6;
1317 deb_info("FEC_5_6\n");
1320 fep->code_rate_LP = FEC_7_8;
1321 deb_info("FEC_7_8\n");
1325 /* guard interval */
1327 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1328 reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1331 deb_info("GUARD INTERVAL ");
1334 fep->guard_interval = GUARD_INTERVAL_1_32;
1338 fep->guard_interval = GUARD_INTERVAL_1_16;
1342 fep->guard_interval = GUARD_INTERVAL_1_8;
1346 fep->guard_interval = GUARD_INTERVAL_1_4;
1353 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1354 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1358 deb_info("TRANSMISSION MODE ");
1361 fep->transmission_mode = TRANSMISSION_MODE_2K;
1365 fep->transmission_mode = TRANSMISSION_MODE_8K;
1372 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1374 deb_info("BANDWIDTH ");
1377 fep->bandwidth_hz = 6000000;
1381 fep->bandwidth_hz = 7000000;
1385 fep->bandwidth_hz = 8000000;
1392 static void af9005_fe_release(struct dvb_frontend *fe)
1394 struct af9005_fe_state *state = fe->demodulator_priv;
1398 static const struct dvb_frontend_ops af9005_fe_ops;
1400 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1402 struct af9005_fe_state *state = NULL;
1404 /* allocate memory for the internal state */
1405 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1409 deb_info("attaching frontend af9005\n");
1414 memcpy(&state->frontend.ops, &af9005_fe_ops,
1415 sizeof(struct dvb_frontend_ops));
1416 state->frontend.demodulator_priv = state;
1418 return &state->frontend;
1423 static const struct dvb_frontend_ops af9005_fe_ops = {
1424 .delsys = { SYS_DVBT },
1426 .name = "AF9005 USB DVB-T",
1427 .frequency_min_hz = 44250 * kHz,
1428 .frequency_max_hz = 867250 * kHz,
1429 .frequency_stepsize_hz = 250 * kHz,
1430 .caps = FE_CAN_INVERSION_AUTO |
1431 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1432 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1433 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1434 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1435 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1436 FE_CAN_HIERARCHY_AUTO,
1439 .release = af9005_fe_release,
1441 .init = af9005_fe_init,
1442 .sleep = af9005_fe_sleep,
1443 .ts_bus_ctrl = af9005_ts_bus_ctrl,
1445 .set_frontend = af9005_fe_set_frontend,
1446 .get_frontend = af9005_fe_get_frontend,
1448 .read_status = af9005_fe_read_status,
1449 .read_ber = af9005_fe_read_ber,
1450 .read_signal_strength = af9005_fe_read_signal_strength,
1451 .read_snr = af9005_fe_read_snr,
1452 .read_ucblocks = af9005_fe_read_unc_blocks,