2 * NXP TDA18250 silicon tuner driver
4 * Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include "tda18250_priv.h"
19 #include <linux/regmap.h>
21 static const struct dvb_tuner_ops tda18250_ops;
23 static int tda18250_power_control(struct dvb_frontend *fe,
24 unsigned int power_state)
26 struct i2c_client *client = fe->tuner_priv;
27 struct tda18250_dev *dev = i2c_get_clientdata(client);
31 dev_dbg(&client->dev, "power state: %d", power_state);
33 switch (power_state) {
34 case TDA18250_POWER_NORMAL:
35 ret = regmap_write_bits(dev->regmap, R06_POWER2, 0x07, 0x00);
38 ret = regmap_write_bits(dev->regmap, R25_REF, 0xc0, 0xc0);
42 case TDA18250_POWER_STANDBY:
43 if (dev->loopthrough) {
44 ret = regmap_write_bits(dev->regmap,
48 ret = regmap_write_bits(dev->regmap,
49 R06_POWER2, 0x07, 0x02);
52 ret = regmap_write_bits(dev->regmap,
57 ret = regmap_write_bits(dev->regmap,
61 ret = regmap_write_bits(dev->regmap,
62 R06_POWER2, 0x07, 0x01);
65 ret = regmap_read(dev->regmap,
69 ret = regmap_write_bits(dev->regmap,
70 R0D_AGC12, 0x03, 0x03);
73 ret = regmap_write_bits(dev->regmap,
77 ret = regmap_write_bits(dev->regmap,
78 R0D_AGC12, 0x03, utmp & 0x03);
93 static int tda18250_wait_for_irq(struct dvb_frontend *fe,
94 int maxwait, int step, u8 irq)
96 struct i2c_client *client = fe->tuner_priv;
97 struct tda18250_dev *dev = i2c_get_clientdata(client);
99 unsigned long timeout;
104 timeout = jiffies + msecs_to_jiffies(maxwait);
105 while (!time_after(jiffies, timeout)) {
107 ret = regmap_read(dev->regmap, R08_IRQ1, &utmp);
110 if ((utmp & irq) == irq) {
117 dev_dbg(&client->dev, "waited IRQ (0x%02x) %d ms, triggered: %s", irq,
118 jiffies_to_msecs(jiffies) -
119 (jiffies_to_msecs(timeout) - maxwait),
120 triggered ? "true" : "false");
130 static int tda18250_init(struct dvb_frontend *fe)
132 struct i2c_client *client = fe->tuner_priv;
133 struct tda18250_dev *dev = i2c_get_clientdata(client);
136 /* default values for various regs */
137 static const u8 init_regs[][2] = {
150 { R1F_RF_BPF, 0x06 },
151 { R20_IR_MIX, 0xc6 },
152 { R21_IF_AGC, 0x00 },
157 { R31_IRQ_CTRL, 0x00 },
160 { R3C_RCCAL1, 0xa7 },
161 { R3F_IRCAL2, 0x85 },
162 { R40_IRCAL3, 0x87 },
163 { R41_IRCAL4, 0xc0 },
167 { R47_LNAPOL, 0x64 },
168 { R4B_XTALOSC1, 0x30 },
169 { R59_AGC2_UP2, 0x05 },
170 { R5B_AGC_AUTO, 0x07 },
171 { R5C_AGC_DEBUG, 0x00 },
174 /* crystal related regs depend on frequency */
175 static const u8 xtal_regs[][5] = {
176 /* reg: 4d 4e 4f 50 51 */
177 [TDA18250_XTAL_FREQ_16MHZ] = { 0x3e, 0x80, 0x50, 0x00, 0x20 },
178 [TDA18250_XTAL_FREQ_24MHZ] = { 0x5d, 0xc0, 0xec, 0x00, 0x18 },
179 [TDA18250_XTAL_FREQ_25MHZ] = { 0x61, 0xa8, 0xec, 0x80, 0x19 },
180 [TDA18250_XTAL_FREQ_27MHZ] = { 0x69, 0x78, 0x8d, 0x80, 0x1b },
181 [TDA18250_XTAL_FREQ_30MHZ] = { 0x75, 0x30, 0x8f, 0x00, 0x1e },
184 dev_dbg(&client->dev, "\n");
186 ret = tda18250_power_control(fe, TDA18250_POWER_NORMAL);
195 /* set initial register values */
196 for (i = 0; i < ARRAY_SIZE(init_regs); i++) {
197 ret = regmap_write(dev->regmap, init_regs[i][0],
203 /* set xtal related regs */
204 ret = regmap_bulk_write(dev->regmap, R4D_XTALFLX1,
205 xtal_regs[dev->xtal_freq], 5);
209 ret = regmap_write_bits(dev->regmap, R10_LT1, 0x80,
210 dev->loopthrough ? 0x00 : 0x80);
215 ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_HW_INIT);
220 ret = regmap_write(dev->regmap, R2A_MSM1, 0x70);
224 ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
228 ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_HW_INIT);
232 /* tuner calibration */
233 ret = regmap_write(dev->regmap, R2A_MSM1, 0x02);
237 ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
241 ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_CAL);
249 ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
255 dev_dbg(&client->dev, "failed=%d", ret);
259 static int tda18250_set_agc(struct dvb_frontend *fe)
261 struct i2c_client *client = fe->tuner_priv;
262 struct tda18250_dev *dev = i2c_get_clientdata(client);
263 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
267 dev_dbg(&client->dev, "\n");
269 ret = regmap_write_bits(dev->regmap, R1F_RF_BPF, 0x87, 0x06);
273 utmp = ((c->frequency < 100000000) &&
274 ((c->delivery_system == SYS_DVBC_ANNEX_A) ||
275 (c->delivery_system == SYS_DVBC_ANNEX_C)) &&
276 (c->bandwidth_hz == 6000000)) ? 0x80 : 0x00;
277 ret = regmap_write(dev->regmap, R5A_H3H5, utmp);
282 switch (c->delivery_system) {
288 default: /* DVB-C/QAM */
289 switch (c->bandwidth_hz) {
291 utmp = (c->frequency < 800000000) ? 6 : 4;
293 default: /* 7.935 and 8 MHz */
294 utmp = (c->frequency < 100000000) ? 2 : 3;
300 ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x07, utmp);
305 switch (c->delivery_system) {
309 utmp = (c->frequency < 320000000) ? 20 : 16;
310 utmp2 = (c->frequency < 320000000) ? 22 : 18;
312 default: /* DVB-C/QAM */
313 switch (c->bandwidth_hz) {
315 if (c->frequency < 600000000) {
318 } else if (c->frequency < 800000000) {
326 default: /* 7.935 and 8 MHz */
327 utmp = (c->frequency < 320000000) ? 16 : 18;
328 utmp2 = (c->frequency < 320000000) ? 18 : 20;
333 ret = regmap_write_bits(dev->regmap, R58_AGC2_UP1, 0x1f, utmp2+8);
336 ret = regmap_write_bits(dev->regmap, R13_AGC22, 0x1f, utmp);
339 ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x1f, utmp2);
343 switch (c->delivery_system) {
349 default: /* DVB-C/QAM */
353 ret = regmap_write_bits(dev->regmap, R16_AGC25, 0xf8, utmp);
357 ret = regmap_write_bits(dev->regmap, R12_AGC21, 0x60,
358 (c->frequency > 800000000) ? 0x40 : 0x20);
363 switch (c->delivery_system) {
367 utmp = (c->frequency < 320000000) ? 5 : 7;
368 utmp2 = (c->frequency < 320000000) ? 10 : 12;
370 default: /* DVB-C/QAM */
375 ret = regmap_write(dev->regmap, R17_AGC31, (utmp << 4) | utmp2);
380 switch (c->delivery_system) {
384 if (c->bandwidth_hz == 8000000)
387 utmp = (c->frequency < 320000000) ? 0x04 : 0x02;
389 default: /* DVB-C/QAM */
390 if (c->bandwidth_hz == 6000000)
391 utmp = ((c->frequency > 172544000) &&
392 (c->frequency < 320000000)) ? 0x04 : 0x02;
393 else /* 7.935 and 8 MHz */
394 utmp = ((c->frequency > 320000000) &&
395 (c->frequency < 600000000)) ? 0x02 : 0x04;
398 ret = regmap_write_bits(dev->regmap, R20_IR_MIX, 0x06, utmp);
402 switch (c->delivery_system) {
408 default: /* DVB-C/QAM */
409 utmp = (c->frequency < 600000000) ? 0 : 3;
412 ret = regmap_write_bits(dev->regmap, R16_AGC25, 0x03, utmp);
417 switch (c->delivery_system) {
421 if (c->bandwidth_hz == 8000000)
424 default: /* DVB-C/QAM */
428 ret = regmap_write_bits(dev->regmap, R0F_AGC14, 0x3f, utmp);
434 dev_dbg(&client->dev, "failed=%d", ret);
438 static int tda18250_pll_calc(struct dvb_frontend *fe, u8 *rdiv,
441 struct i2c_client *client = fe->tuner_priv;
442 struct tda18250_dev *dev = i2c_get_clientdata(client);
443 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
445 unsigned int uval, exp, lopd, scale;
448 ret = regmap_read(dev->regmap, R34_MD1, &uval);
452 exp = (uval & 0x70) >> 4;
455 lopd = 1 << (exp - 1);
457 fvco = lopd * scale * ((c->frequency / 1000) + dev->if_frequency);
459 switch (dev->xtal_freq) {
460 case TDA18250_XTAL_FREQ_16MHZ:
463 *icp = (fvco < 6622000) ? 0x05 : 0x02;
465 case TDA18250_XTAL_FREQ_24MHZ:
466 case TDA18250_XTAL_FREQ_25MHZ:
469 *icp = (fvco < 6622000) ? 0x05 : 0x02;
471 case TDA18250_XTAL_FREQ_27MHZ:
472 if (fvco < 6643000) {
476 } else if (fvco < 6811000) {
486 case TDA18250_XTAL_FREQ_30MHZ:
489 *icp = (fvco < 6811000) ? 0x05 : 0x02;
495 dev_dbg(&client->dev,
496 "lopd=%d scale=%u fvco=%lu, rdiv=%d ndiv=%d icp=%d",
497 lopd, scale, fvco, *rdiv, *ndiv, *icp);
503 static int tda18250_set_params(struct dvb_frontend *fe)
505 struct i2c_client *client = fe->tuner_priv;
506 struct tda18250_dev *dev = i2c_get_clientdata(client);
507 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
523 static const u8 delsys_params[][16] = {
524 [REG] = { 0x22, 0x23, 0x24, 0x21, 0x0d, 0x0c, 0x0f, 0x14,
525 0x0e, 0x12, 0x58, 0x59, 0x1a, 0x19, 0x1e, 0x30 },
526 [MASK] = { 0x77, 0xff, 0xff, 0x87, 0xf0, 0x78, 0x07, 0xe0,
527 0x60, 0x0f, 0x60, 0x0f, 0x33, 0x30, 0x80, 0x06 },
528 [DVBT_6] = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
529 0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
530 [DVBT_7] = { 0x52, 0x03, 0x85, 0x82, 0x40, 0x48, 0x01, 0xe0,
531 0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
532 [DVBT_8] = { 0x53, 0x03, 0x87, 0x82, 0x40, 0x48, 0x06, 0xe0,
533 0x60, 0x07, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
534 [DVBC_6] = { 0x32, 0x05, 0x86, 0x82, 0x50, 0x00, 0x06, 0x60,
535 0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
536 [DVBC_8] = { 0x53, 0x03, 0x88, 0x82, 0x50, 0x00, 0x06, 0x60,
537 0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
538 [ATSC] = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
539 0x40, 0x0e, 0x60, 0x05, 0x03, 0x00, 0x80, 0x04 },
542 dev_dbg(&client->dev,
543 "delivery_system=%d frequency=%u bandwidth_hz=%u",
544 c->delivery_system, c->frequency, c->bandwidth_hz);
547 switch (c->delivery_system) {
550 if_khz = dev->if_atsc;
554 if (c->bandwidth_hz == 0) {
557 } else if (c->bandwidth_hz <= 6000000) {
559 if_khz = dev->if_dvbt_6;
560 } else if (c->bandwidth_hz <= 7000000) {
562 if_khz = dev->if_dvbt_7;
563 } else if (c->bandwidth_hz <= 8000000) {
565 if_khz = dev->if_dvbt_8;
571 case SYS_DVBC_ANNEX_A:
572 case SYS_DVBC_ANNEX_C:
573 if (c->bandwidth_hz == 0) {
576 } else if (c->bandwidth_hz <= 6000000) {
578 if_khz = dev->if_dvbc_6;
579 } else if (c->bandwidth_hz <= 8000000) {
581 if_khz = dev->if_dvbc_8;
589 dev_err(&client->dev, "unsupported delivery system=%d",
594 /* set delivery system dependent registers */
595 for (i = 0; i < 16; i++) {
596 ret = regmap_write_bits(dev->regmap, delsys_params[REG][i],
597 delsys_params[MASK][i], delsys_params[j][i]);
602 /* set IF if needed */
603 if (dev->if_frequency != if_khz) {
604 utmp = DIV_ROUND_CLOSEST(if_khz, 50);
605 ret = regmap_write(dev->regmap, R26_IF, utmp);
608 dev->if_frequency = if_khz;
609 dev_dbg(&client->dev, "set IF=%u kHz", if_khz);
613 ret = tda18250_set_agc(fe);
617 ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x01);
621 ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x00);
626 buf[0] = ((c->frequency / 1000) >> 16) & 0xff;
627 buf[1] = ((c->frequency / 1000) >> 8) & 0xff;
628 buf[2] = ((c->frequency / 1000) >> 0) & 0xff;
629 ret = regmap_bulk_write(dev->regmap, R27_RF1, buf, 3);
633 ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
638 ret = regmap_write(dev->regmap, R2A_MSM1, 0x01);
642 ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
646 ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
650 /* calc ndiv and rdiv */
651 ret = tda18250_pll_calc(fe, &buf[0], &buf[1], &buf[2]);
655 ret = regmap_write_bits(dev->regmap, R4F_XTALFLX3, 0xe0,
656 (buf[0] << 6) | (buf[1] << 5));
661 ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
665 ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, 0x00);
669 ret = regmap_write_bits(dev->regmap, R39_SD5, 0x03, 0x00);
674 ret = regmap_write(dev->regmap, R2A_MSM1, 0x01); /* tune */
678 ret = regmap_write(dev->regmap, R2B_MSM2, 0x01); /* go */
682 ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
689 ret = regmap_write_bits(dev->regmap, R2B_MSM2, 0x04, 0x04);
696 ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x03);
700 ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x40);
705 ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, buf[2]);
712 static int tda18250_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
714 struct i2c_client *client = fe->tuner_priv;
715 struct tda18250_dev *dev = i2c_get_clientdata(client);
717 *frequency = dev->if_frequency * 1000;
721 static int tda18250_sleep(struct dvb_frontend *fe)
723 struct i2c_client *client = fe->tuner_priv;
724 struct tda18250_dev *dev = i2c_get_clientdata(client);
727 dev_dbg(&client->dev, "\n");
730 ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
734 /* set if freq to 0 in order to make sure it's set after wake up */
735 dev->if_frequency = 0;
737 ret = tda18250_power_control(fe, TDA18250_POWER_STANDBY);
741 static const struct dvb_tuner_ops tda18250_ops = {
743 .name = "NXP TDA18250",
744 .frequency_min_hz = 42 * MHz,
745 .frequency_max_hz = 870 * MHz,
748 .init = tda18250_init,
749 .set_params = tda18250_set_params,
750 .get_if_frequency = tda18250_get_if_frequency,
751 .sleep = tda18250_sleep,
754 static int tda18250_probe(struct i2c_client *client,
755 const struct i2c_device_id *id)
757 struct tda18250_config *cfg = client->dev.platform_data;
758 struct dvb_frontend *fe = cfg->fe;
759 struct tda18250_dev *dev;
761 unsigned char chip_id[3];
763 /* some registers are always read from HW */
764 static const struct regmap_range tda18250_yes_ranges[] = {
765 regmap_reg_range(R05_POWER1, R0B_IRQ4),
766 regmap_reg_range(R21_IF_AGC, R21_IF_AGC),
767 regmap_reg_range(R2A_MSM1, R2B_MSM2),
768 regmap_reg_range(R2F_RSSI1, R31_IRQ_CTRL),
771 static const struct regmap_access_table tda18250_volatile_table = {
772 .yes_ranges = tda18250_yes_ranges,
773 .n_yes_ranges = ARRAY_SIZE(tda18250_yes_ranges),
776 static const struct regmap_config tda18250_regmap_config = {
779 .max_register = TDA18250_NUM_REGS - 1,
780 .volatile_table = &tda18250_volatile_table,
783 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
789 i2c_set_clientdata(client, dev);
792 dev->loopthrough = cfg->loopthrough;
793 if (cfg->xtal_freq < TDA18250_XTAL_FREQ_MAX) {
794 dev->xtal_freq = cfg->xtal_freq;
797 dev_err(&client->dev, "xtal_freq invalid=%d", cfg->xtal_freq);
800 dev->if_dvbt_6 = cfg->if_dvbt_6;
801 dev->if_dvbt_7 = cfg->if_dvbt_7;
802 dev->if_dvbt_8 = cfg->if_dvbt_8;
803 dev->if_dvbc_6 = cfg->if_dvbc_6;
804 dev->if_dvbc_8 = cfg->if_dvbc_8;
805 dev->if_atsc = cfg->if_atsc;
807 dev->if_frequency = 0;
810 dev->regmap = devm_regmap_init_i2c(client, &tda18250_regmap_config);
811 if (IS_ERR(dev->regmap)) {
812 ret = PTR_ERR(dev->regmap);
816 /* read the three chip ID registers */
817 regmap_bulk_read(dev->regmap, R00_ID1, &chip_id, 3);
818 dev_dbg(&client->dev, "chip_id=%02x:%02x:%02x",
819 chip_id[0], chip_id[1], chip_id[2]);
821 switch (chip_id[0]) {
833 if (chip_id[1] != 0x4a) {
838 switch (chip_id[2]) {
840 dev_info(&client->dev,
841 "NXP TDA18250AHN/%s successfully identified",
842 dev->slave ? "S" : "M");
845 dev_info(&client->dev,
846 "NXP TDA18250BHN/%s successfully identified",
847 dev->slave ? "S" : "M");
854 fe->tuner_priv = client;
855 memcpy(&fe->ops.tuner_ops, &tda18250_ops,
856 sizeof(struct dvb_tuner_ops));
858 /* put the tuner in standby */
859 tda18250_power_control(fe, TDA18250_POWER_STANDBY);
865 dev_dbg(&client->dev, "failed=%d", ret);
869 static int tda18250_remove(struct i2c_client *client)
871 struct tda18250_dev *dev = i2c_get_clientdata(client);
872 struct dvb_frontend *fe = dev->fe;
874 dev_dbg(&client->dev, "\n");
876 memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
877 fe->tuner_priv = NULL;
883 static const struct i2c_device_id tda18250_id_table[] = {
887 MODULE_DEVICE_TABLE(i2c, tda18250_id_table);
889 static struct i2c_driver tda18250_driver = {
893 .probe = tda18250_probe,
894 .remove = tda18250_remove,
895 .id_table = tda18250_id_table,
898 module_i2c_driver(tda18250_driver);
900 MODULE_DESCRIPTION("NXP TDA18250 silicon tuner driver");
901 MODULE_AUTHOR("Olli Salonen <olli.salonen@iki.fi>");
902 MODULE_LICENSE("GPL");