2 * Rafael Micro R820T driver
4 * Copyright (C) 2013 Mauro Carvalho Chehab
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
21 * RF Gain set/get is not implemented.
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
40 #include "tuner-i2c.h"
44 * FIXME: I think that there are only 32 registers, but better safe than
45 * sorry. After finishing the driver, we may review it.
47 #define REG_SHADOW_START 5
55 module_param(debug, int, 0644);
56 MODULE_PARM_DESC(debug, "enable verbose debug messages");
58 static int no_imr_cal;
59 module_param(no_imr_cal, int, 0444);
60 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
64 * enums and structures
75 struct r820t_sect_type {
82 struct list_head hybrid_tuner_instance_list;
83 const struct r820t_config *cfg;
84 struct tuner_i2c_props i2c_props;
89 enum xtal_cap_value xtal_cap_sel;
96 struct r820t_sect_type imr_data[NUM_IMR];
98 /* Store current mode */
100 enum v4l2_tuner_type type;
105 struct r820t_freq_range {
113 u8 imr_mem; /* Not used, currently */
116 #define VCO_POWER_REF 0x02
117 #define DIP_FREQ 32000000
123 static LIST_HEAD(hybrid_tuner_instance_list);
124 static DEFINE_MUTEX(r820t_list_mutex);
126 /* Those initial values start from REG_SHADOW_START */
127 static const u8 r820t_init_array[NUM_REGS] = {
128 0x83, 0x32, 0x75, /* 05 to 07 */
129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
137 /* Tuner frequency ranges */
138 static const struct r820t_freq_range freq_ranges[] = {
141 .open_d = 0x08, /* low */
142 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
143 .tf_c = 0xdf, /* R27[7:0] band2,band0 */
144 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
149 .freq = 50, /* Start freq, in MHz */
150 .open_d = 0x08, /* low */
151 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
152 .tf_c = 0xbe, /* R27[7:0] band4,band1 */
153 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
158 .freq = 55, /* Start freq, in MHz */
159 .open_d = 0x08, /* low */
160 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
161 .tf_c = 0x8b, /* R27[7:0] band7,band4 */
162 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
167 .freq = 60, /* Start freq, in MHz */
168 .open_d = 0x08, /* low */
169 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
170 .tf_c = 0x7b, /* R27[7:0] band8,band4 */
171 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
176 .freq = 65, /* Start freq, in MHz */
177 .open_d = 0x08, /* low */
178 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
179 .tf_c = 0x69, /* R27[7:0] band9,band6 */
180 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
185 .freq = 70, /* Start freq, in MHz */
186 .open_d = 0x08, /* low */
187 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
188 .tf_c = 0x58, /* R27[7:0] band10,band7 */
189 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
194 .freq = 75, /* Start freq, in MHz */
195 .open_d = 0x00, /* high */
196 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
197 .tf_c = 0x44, /* R27[7:0] band11,band11 */
198 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
203 .freq = 80, /* Start freq, in MHz */
204 .open_d = 0x00, /* high */
205 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
206 .tf_c = 0x44, /* R27[7:0] band11,band11 */
207 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
212 .freq = 90, /* Start freq, in MHz */
213 .open_d = 0x00, /* high */
214 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
215 .tf_c = 0x34, /* R27[7:0] band12,band11 */
216 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
221 .freq = 100, /* Start freq, in MHz */
222 .open_d = 0x00, /* high */
223 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
224 .tf_c = 0x34, /* R27[7:0] band12,band11 */
225 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
230 .freq = 110, /* Start freq, in MHz */
231 .open_d = 0x00, /* high */
232 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
233 .tf_c = 0x24, /* R27[7:0] band13,band11 */
234 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
239 .freq = 120, /* Start freq, in MHz */
240 .open_d = 0x00, /* high */
241 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
242 .tf_c = 0x24, /* R27[7:0] band13,band11 */
243 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
248 .freq = 140, /* Start freq, in MHz */
249 .open_d = 0x00, /* high */
250 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
251 .tf_c = 0x14, /* R27[7:0] band14,band11 */
252 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
257 .freq = 180, /* Start freq, in MHz */
258 .open_d = 0x00, /* high */
259 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
260 .tf_c = 0x13, /* R27[7:0] band14,band12 */
261 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
266 .freq = 220, /* Start freq, in MHz */
267 .open_d = 0x00, /* high */
268 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
269 .tf_c = 0x13, /* R27[7:0] band14,band12 */
270 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
275 .freq = 250, /* Start freq, in MHz */
276 .open_d = 0x00, /* high */
277 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
278 .tf_c = 0x11, /* R27[7:0] highest,highest */
279 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
284 .freq = 280, /* Start freq, in MHz */
285 .open_d = 0x00, /* high */
286 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
287 .tf_c = 0x00, /* R27[7:0] highest,highest */
288 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
293 .freq = 310, /* Start freq, in MHz */
294 .open_d = 0x00, /* high */
295 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
296 .tf_c = 0x00, /* R27[7:0] highest,highest */
297 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
302 .freq = 450, /* Start freq, in MHz */
303 .open_d = 0x00, /* high */
304 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
305 .tf_c = 0x00, /* R27[7:0] highest,highest */
306 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
311 .freq = 588, /* Start freq, in MHz */
312 .open_d = 0x00, /* high */
313 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
314 .tf_c = 0x00, /* R27[7:0] highest,highest */
315 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
320 .freq = 650, /* Start freq, in MHz */
321 .open_d = 0x00, /* high */
322 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
323 .tf_c = 0x00, /* R27[7:0] highest,highest */
324 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
331 static int r820t_xtal_capacitor[][2] = {
332 { 0x0b, XTAL_LOW_CAP_30P },
333 { 0x02, XTAL_LOW_CAP_20P },
334 { 0x01, XTAL_LOW_CAP_10P },
335 { 0x00, XTAL_LOW_CAP_0P },
336 { 0x10, XTAL_HIGH_CAP_0P },
340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
341 * input power, for raw results see:
342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
345 static const int r820t_lna_gain_steps[] = {
346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
349 static const int r820t_mixer_gain_steps[] = {
350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
354 * I2C read/write code and shadow registers logic
356 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
359 int r = reg - REG_SHADOW_START;
367 if (len > NUM_REGS - r)
370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
371 __func__, r + REG_SHADOW_START, len, len, val);
373 memcpy(&priv->regs[r], val, len);
376 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
379 int rc, size, pos = 0;
381 /* Store the shadow registers */
382 shadow_store(priv, reg, val, len);
385 if (len > priv->cfg->max_i2c_msg_len - 1)
386 size = priv->cfg->max_i2c_msg_len - 1;
390 /* Fill I2C buffer */
392 memcpy(&priv->buf[1], &val[pos], size);
394 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
395 if (rc != size + 1) {
396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
397 __func__, rc, reg, size, size, &priv->buf[1]);
402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
403 __func__, reg, size, size, &priv->buf[1]);
413 static inline int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
415 u8 tmp = val; /* work around GCC PR81715 with asan-stack=1 */
417 return r820t_write(priv, reg, &tmp, 1);
420 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
422 reg -= REG_SHADOW_START;
424 if (reg >= 0 && reg < NUM_REGS)
425 return priv->regs[reg];
430 static inline int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
434 int rc = r820t_read_cache_reg(priv, reg);
439 tmp = (rc & ~bit_mask) | (tmp & bit_mask);
441 return r820t_write(priv, reg, &tmp, 1);
444 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
447 u8 *p = &priv->buf[1];
451 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
453 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
454 __func__, rc, reg, len, len, p);
460 /* Copy data to the output buffer */
461 for (i = 0; i < len; i++)
462 val[i] = bitrev8(p[i]);
464 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
465 __func__, reg, len, len, val);
474 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
476 const struct r820t_freq_range *range;
478 u8 val, reg08, reg09;
480 /* Get the proper frequency range */
481 freq = freq / 1000000;
482 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
483 if (freq < freq_ranges[i + 1].freq)
486 range = &freq_ranges[i];
488 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
491 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
496 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
501 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
505 /* XTAL CAP & Drive */
506 switch (priv->xtal_cap_sel) {
507 case XTAL_LOW_CAP_30P:
508 case XTAL_LOW_CAP_20P:
509 val = range->xtal_cap20p | 0x08;
511 case XTAL_LOW_CAP_10P:
512 val = range->xtal_cap10p | 0x08;
514 case XTAL_HIGH_CAP_0P:
515 val = range->xtal_cap0p | 0x00;
518 case XTAL_LOW_CAP_0P:
519 val = range->xtal_cap0p | 0x08;
522 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
526 if (priv->imr_done) {
527 reg08 = priv->imr_data[range->imr_mem].gain_x;
528 reg09 = priv->imr_data[range->imr_mem].phase_y;
533 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
537 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
542 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
547 unsigned sleep_time = 10000;
548 u32 vco_fra; /* VCO contribution by SDM (kHz) */
549 u32 vco_min = 1770000;
550 u32 vco_max = vco_min * 2;
558 u8 ni, si, nint, vco_fine_tune, val;
561 /* Frequency in kHz */
563 pll_ref = priv->cfg->xtal / 1000;
566 /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */
567 if ((priv->cfg->rafael_chip == CHIP_R620D) ||
568 (priv->cfg->rafael_chip == CHIP_R828D) ||
569 (priv->cfg->rafael_chip == CHIP_R828)) {
570 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
571 if (type != V4L2_TUNER_DIGITAL_TV) {
577 if (priv->cfg->xtal > 24000000) {
584 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
588 /* set pll autotune = 128kHz */
589 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
593 /* set VCO current = 100 */
594 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
598 /* Calculate divider */
599 while (mix_div <= 64) {
600 if (((freq * mix_div) >= vco_min) &&
601 ((freq * mix_div) < vco_max)) {
603 while (div_buf > 2) {
604 div_buf = div_buf >> 1;
609 mix_div = mix_div << 1;
612 rc = r820t_read(priv, 0x00, data, sizeof(data));
616 vco_fine_tune = (data[4] & 0x30) >> 4;
618 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
619 mix_div, div_num, vco_fine_tune);
622 * XXX: R828D/16MHz seems to have always vco_fine_tune=1.
623 * Due to that, this calculation goes wrong.
625 if (priv->cfg->rafael_chip != CHIP_R828D) {
626 if (vco_fine_tune > VCO_POWER_REF)
627 div_num = div_num - 1;
628 else if (vco_fine_tune < VCO_POWER_REF)
629 div_num = div_num + 1;
632 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
636 vco_freq = freq * mix_div;
637 nint = vco_freq / (2 * pll_ref);
638 vco_fra = vco_freq - 2 * pll_ref * nint;
640 /* boundary spur prevention */
641 if (vco_fra < pll_ref / 64) {
643 } else if (vco_fra > pll_ref * 127 / 64) {
646 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
647 vco_fra = pll_ref * 127 / 128;
648 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
649 vco_fra = pll_ref * 129 / 128;
652 ni = (nint - 13) / 4;
653 si = nint - 4 * ni - 13;
655 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
665 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
670 while (vco_fra > 1) {
671 if (vco_fra > (2 * pll_ref / n_sdm)) {
672 sdm = sdm + 32768 / (n_sdm / 2);
673 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
680 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
681 freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
683 rc = r820t_write_reg(priv, 0x16, sdm >> 8);
686 rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
690 for (i = 0; i < 2; i++) {
691 usleep_range(sleep_time, sleep_time + 1000);
693 /* Check if PLL has locked */
694 rc = r820t_read(priv, 0x00, data, 3);
701 /* Didn't lock. Increase VCO current */
702 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
708 if (!(data[2] & 0x40)) {
709 priv->has_lock = false;
713 priv->has_lock = true;
714 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
716 /* set pll autotune = 8kHz */
717 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
722 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
723 enum v4l2_tuner_type type,
728 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
729 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
731 tuner_dbg("adjusting tuner parameters for the standard\n");
735 if ((freq == 506000000) || (freq == 666000000) ||
736 (freq == 818000000)) {
737 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
738 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
739 cp_cur = 0x28; /* 101, 0.2 */
740 div_buf_cur = 0x20; /* 10, 200u */
742 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
743 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
744 cp_cur = 0x38; /* 111, auto */
745 div_buf_cur = 0x30; /* 11, 150u */
747 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
748 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
749 air_cable1_in = 0x00;
753 filter_cur = 0x40; /* 10, low */
756 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
757 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
758 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
759 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
760 air_cable1_in = 0x00;
764 cp_cur = 0x38; /* 111, auto */
765 div_buf_cur = 0x30; /* 11, 150u */
766 filter_cur = 0x40; /* 10, low */
769 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
770 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
771 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
772 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
773 air_cable1_in = 0x00;
777 cp_cur = 0x38; /* 111, auto */
778 div_buf_cur = 0x30; /* 11, 150u */
779 filter_cur = 0x40; /* 10, low */
781 case SYS_DVBC_ANNEX_A:
782 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
786 air_cable1_in = 0x60;
790 cp_cur = 0x38; /* 111, auto */
791 div_buf_cur = 0x30; /* 11, 150u */
792 filter_cur = 0x40; /* 10, low */
794 default: /* DVB-T 8M */
795 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
796 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
797 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
798 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
799 air_cable1_in = 0x00;
803 cp_cur = 0x38; /* 111, auto */
804 div_buf_cur = 0x30; /* 11, 150u */
805 filter_cur = 0x40; /* 10, low */
809 if (priv->cfg->use_diplexer &&
810 ((priv->cfg->rafael_chip == CHIP_R820T) ||
811 (priv->cfg->rafael_chip == CHIP_R828S) ||
812 (priv->cfg->rafael_chip == CHIP_R820C))) {
814 air_cable1_in = 0x00;
816 air_cable1_in = 0x60;
821 if (priv->cfg->use_predetect) {
822 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
827 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
830 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
833 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
836 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
840 /* Air-IN only for Astrometa */
841 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
844 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
848 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
851 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
854 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
858 * Original driver initializes regs 0x05 and 0x06 with the
859 * same value again on this point. Probably, it is just an
867 tuner_dbg("adjusting LNA parameters\n");
868 if (type != V4L2_TUNER_ANALOG_TV) {
869 /* LNA TOP: lowest */
870 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
875 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
879 /* 0: PRE_DECT off */
880 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
885 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
891 /* write LNA TOP = 3 */
892 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
897 * write discharge mode
898 * FIXME: IMHO, the mask here is wrong, but it matches
899 * what's there at the original driver
901 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
905 /* LNA discharge current */
906 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
911 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
916 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
921 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
926 * write discharge mode
927 * FIXME: IMHO, the mask here is wrong, but it matches
928 * what's there at the original driver
930 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
934 /* LNA discharge current */
935 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
939 /* agc clk 1Khz, external det1 cap 1u */
940 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
944 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
951 static int r820t_set_tv_standard(struct r820t_priv *priv,
953 enum v4l2_tuner_type type,
954 v4l2_std_id std, u32 delsys)
958 u32 if_khz, filt_cal_lo;
960 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
961 u8 lt_att, flt_ext_widest, polyfil_cur;
962 bool need_calibration;
964 tuner_dbg("selecting the delivery system\n");
966 if (delsys == SYS_ISDBT) {
969 filt_gain = 0x10; /* +3db, 6mhz on */
970 img_r = 0x00; /* image negative */
971 filt_q = 0x10; /* r10[4]:low q(1'b1) */
972 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
973 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
974 loop_through = 0x00; /* r5[7], lt on */
975 lt_att = 0x00; /* r31[7], lt att enable */
976 flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */
977 polyfil_cur = 0x60; /* r25[6:5]:min */
978 } else if (delsys == SYS_DVBC_ANNEX_A) {
981 filt_gain = 0x10; /* +3db, 6mhz on */
982 img_r = 0x00; /* image negative */
983 filt_q = 0x10; /* r10[4]:low q(1'b1) */
984 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
985 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
986 loop_through = 0x00; /* r5[7], lt on */
987 lt_att = 0x00; /* r31[7], lt att enable */
988 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
989 polyfil_cur = 0x60; /* r25[6:5]:min */
990 } else if (delsys == SYS_DVBC_ANNEX_C) {
993 filt_gain = 0x10; /* +3db, 6mhz on */
994 img_r = 0x00; /* image negative */
995 filt_q = 0x10; /* r10[4]:low q(1'b1) */
996 hp_cor = 0x6a; /* 1.7m disable, +0cap, 1.0mhz */
997 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
998 loop_through = 0x00; /* r5[7], lt on */
999 lt_att = 0x00; /* r31[7], lt att enable */
1000 flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */
1001 polyfil_cur = 0x60; /* r25[6:5]:min */
1005 filt_cal_lo = 56000; /* 52000->56000 */
1006 filt_gain = 0x10; /* +3db, 6mhz on */
1007 img_r = 0x00; /* image negative */
1008 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1009 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
1010 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1011 loop_through = 0x00; /* r5[7], lt on */
1012 lt_att = 0x00; /* r31[7], lt att enable */
1013 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1014 polyfil_cur = 0x60; /* r25[6:5]:min */
1015 } else if (bw == 7) {
1018 * There are two 7 MHz tables defined on the original
1019 * driver, but just the second one seems to be visible
1020 * by rtl2832. Keep this one here commented, as it
1021 * might be needed in the future
1025 filt_cal_lo = 60000;
1026 filt_gain = 0x10; /* +3db, 6mhz on */
1027 img_r = 0x00; /* image negative */
1028 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1029 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
1030 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1031 loop_through = 0x00; /* r5[7], lt on */
1032 lt_att = 0x00; /* r31[7], lt att enable */
1033 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1034 polyfil_cur = 0x60; /* r25[6:5]:min */
1036 /* 7 MHz, second table */
1038 filt_cal_lo = 63000;
1039 filt_gain = 0x10; /* +3db, 6mhz on */
1040 img_r = 0x00; /* image negative */
1041 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1042 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
1043 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1044 loop_through = 0x00; /* r5[7], lt on */
1045 lt_att = 0x00; /* r31[7], lt att enable */
1046 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1047 polyfil_cur = 0x60; /* r25[6:5]:min */
1050 filt_cal_lo = 68500;
1051 filt_gain = 0x10; /* +3db, 6mhz on */
1052 img_r = 0x00; /* image negative */
1053 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1054 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
1055 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1056 loop_through = 0x00; /* r5[7], lt on */
1057 lt_att = 0x00; /* r31[7], lt att enable */
1058 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1059 polyfil_cur = 0x60; /* r25[6:5]:min */
1063 /* Initialize the shadow registers */
1064 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1066 /* Init Flag & Xtal_check Result */
1068 val = 1 | priv->xtal_cap_sel << 1;
1071 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1076 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1080 /* for LT Gain test */
1081 if (type != V4L2_TUNER_ANALOG_TV) {
1082 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1085 usleep_range(1000, 2000);
1087 priv->int_freq = if_khz * 1000;
1089 /* Check if standard changed. If so, filter calibration is needed */
1090 if (type != priv->type)
1091 need_calibration = true;
1092 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1093 need_calibration = true;
1094 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1095 ((delsys != priv->delsys) || bw != priv->bw))
1096 need_calibration = true;
1098 need_calibration = false;
1100 if (need_calibration) {
1101 tuner_dbg("calibrating the tuner\n");
1102 for (i = 0; i < 2; i++) {
1104 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1108 /* set cali clk =on */
1109 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1113 /* X'tal cap 0pF for PLL */
1114 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1118 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
1119 if (rc < 0 || !priv->has_lock)
1123 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1127 usleep_range(1000, 2000);
1130 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1134 /* set cali clk =off */
1135 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1139 /* Check if calibration worked */
1140 rc = r820t_read(priv, 0x00, data, sizeof(data));
1144 priv->fil_cal_code = data[4] & 0x0f;
1145 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1149 if (priv->fil_cal_code == 0x0f)
1150 priv->fil_cal_code = 0;
1153 rc = r820t_write_reg_mask(priv, 0x0a,
1154 filt_q | priv->fil_cal_code, 0x1f);
1158 /* Set BW, Filter_gain, & HP corner */
1159 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
1165 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1169 /* Set filt_3dB, V6MHz */
1170 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1174 /* channel filter extension */
1175 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1180 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1184 /* Loop through attenuation */
1185 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1189 /* filter extension widest */
1190 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1194 /* RF poly filter current */
1195 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1199 /* Store current standard. If it changes, re-calibrate the tuner */
1200 priv->delsys = delsys;
1208 static int r820t_read_gain(struct r820t_priv *priv)
1213 rc = r820t_read(priv, 0x00, data, sizeof(data));
1217 return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4);
1221 /* FIXME: This routine requires more testing */
1222 static int r820t_set_gain_mode(struct r820t_priv *priv,
1223 bool set_manual_gain,
1228 if (set_manual_gain) {
1229 int i, total_gain = 0;
1230 uint8_t mix_index = 0, lna_index = 0;
1234 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1238 /* Mixer auto off */
1239 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1243 rc = r820t_read(priv, 0x00, data, sizeof(data));
1247 /* set fixed VGA gain for now (16.3 dB) */
1248 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1252 for (i = 0; i < 15; i++) {
1253 if (total_gain >= gain)
1256 total_gain += r820t_lna_gain_steps[++lna_index];
1258 if (total_gain >= gain)
1261 total_gain += r820t_mixer_gain_steps[++mix_index];
1265 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1269 /* set Mixer gain */
1270 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1275 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
1280 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
1284 /* set fixed VGA gain for now (26.5 dB) */
1285 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1294 static int generic_set_freq(struct dvb_frontend *fe,
1295 u32 freq /* in HZ */,
1297 enum v4l2_tuner_type type,
1298 v4l2_std_id std, u32 delsys)
1300 struct r820t_priv *priv = fe->tuner_priv;
1304 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1307 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1311 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1312 lo_freq = freq - priv->int_freq;
1314 lo_freq = freq + priv->int_freq;
1316 rc = r820t_set_mux(priv, lo_freq);
1320 rc = r820t_set_pll(priv, type, lo_freq);
1321 if (rc < 0 || !priv->has_lock)
1324 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1328 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1329 __func__, freq, r820t_read_gain(priv));
1334 tuner_dbg("%s: failed=%d\n", __func__, rc);
1339 * r820t standby logic
1342 static int r820t_standby(struct r820t_priv *priv)
1346 /* If device was not initialized yet, don't need to standby */
1347 if (!priv->init_done)
1350 rc = r820t_write_reg(priv, 0x06, 0xb1);
1353 rc = r820t_write_reg(priv, 0x05, 0x03);
1356 rc = r820t_write_reg(priv, 0x07, 0x3a);
1359 rc = r820t_write_reg(priv, 0x08, 0x40);
1362 rc = r820t_write_reg(priv, 0x09, 0xc0);
1365 rc = r820t_write_reg(priv, 0x0a, 0x36);
1368 rc = r820t_write_reg(priv, 0x0c, 0x35);
1371 rc = r820t_write_reg(priv, 0x0f, 0x68);
1374 rc = r820t_write_reg(priv, 0x11, 0x03);
1377 rc = r820t_write_reg(priv, 0x17, 0xf4);
1380 rc = r820t_write_reg(priv, 0x19, 0x0c);
1382 /* Force initial calibration */
1389 * r820t device init logic
1392 static int r820t_xtal_check(struct r820t_priv *priv)
1397 /* Initialize the shadow registers */
1398 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1400 /* cap 30pF & Drive Low */
1401 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1405 /* set pll autotune = 128kHz */
1406 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1410 /* set manual initial reg = 111111; */
1411 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1416 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1420 /* Try several xtal capacitor alternatives */
1421 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1422 rc = r820t_write_reg_mask(priv, 0x10,
1423 r820t_xtal_capacitor[i][0], 0x1b);
1427 usleep_range(5000, 6000);
1429 rc = r820t_read(priv, 0x00, data, sizeof(data));
1432 if (!(data[2] & 0x40))
1435 val = data[2] & 0x3f;
1437 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1444 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1447 return r820t_xtal_capacitor[i][1];
1450 static int r820t_imr_prepare(struct r820t_priv *priv)
1454 /* Initialize the shadow registers */
1455 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1457 /* lna off (air-in off) */
1458 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1462 /* mixer gain mode = manual */
1463 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1467 /* filter corner = lowest */
1468 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1472 /* filter bw=+2cap, hp=5M */
1473 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1477 /* adc=on, vga code mode, gain = 26.5dB */
1478 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1483 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1487 /* ring power = on */
1488 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1492 /* from ring = ring pll in */
1493 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1497 /* sw_pdect = det3 */
1498 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1503 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1508 static int r820t_multi_read(struct r820t_priv *priv)
1512 u8 data[2], min = 255, max = 0;
1514 usleep_range(5000, 6000);
1516 for (i = 0; i < 6; i++) {
1517 rc = r820t_read(priv, 0x00, data, sizeof(data));
1529 rc = sum - max - min;
1534 static int r820t_imr_cross(struct r820t_priv *priv,
1535 struct r820t_sect_type iq_point[3],
1538 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1539 struct r820t_sect_type tmp;
1543 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1544 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1550 for (i = 0; i < 5; i++) {
1553 cross[i].gain_x = reg08;
1554 cross[i].phase_y = reg09;
1557 cross[i].gain_x = reg08; /* 0 */
1558 cross[i].phase_y = reg09 + 1; /* Q-1 */
1561 cross[i].gain_x = reg08; /* 0 */
1562 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
1565 cross[i].gain_x = reg08 + 1; /* Q-1 */
1566 cross[i].phase_y = reg09;
1569 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
1570 cross[i].phase_y = reg09;
1573 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1577 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1581 rc = r820t_multi_read(priv);
1585 cross[i].value = rc;
1587 if (cross[i].value < tmp.value)
1591 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
1594 iq_point[0] = cross[0];
1595 iq_point[1] = cross[1];
1596 iq_point[2] = cross[2];
1597 } else { /* (0,0) or x-direction */
1600 iq_point[0] = cross[0];
1601 iq_point[1] = cross[3];
1602 iq_point[2] = cross[4];
1607 static void r820t_compre_cor(struct r820t_sect_type iq[3])
1611 for (i = 3; i > 0; i--) {
1612 if (iq[0].value > iq[i - 1].value)
1613 swap(iq[0], iq[i - 1]);
1617 static int r820t_compre_step(struct r820t_priv *priv,
1618 struct r820t_sect_type iq[3], u8 reg)
1621 struct r820t_sect_type tmp;
1624 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1626 * new < min => update to min and continue
1630 /* min value already saved in iq[0] */
1631 tmp.phase_y = iq[0].phase_y;
1632 tmp.gain_x = iq[0].gain_x;
1634 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1635 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1641 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1645 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1649 rc = r820t_multi_read(priv);
1654 if (tmp.value <= iq[0].value) {
1655 iq[0].gain_x = tmp.gain_x;
1656 iq[0].phase_y = tmp.phase_y;
1657 iq[0].value = tmp.value;
1667 static int r820t_iq_tree(struct r820t_priv *priv,
1668 struct r820t_sect_type iq[3],
1669 u8 fix_val, u8 var_val, u8 fix_reg)
1675 * record IMC results by input gain/phase location then adjust
1676 * gain or phase positive 1 step and negtive 1 step,
1677 * both record results
1680 if (fix_reg == 0x08)
1685 for (i = 0; i < 3; i++) {
1686 rc = r820t_write_reg(priv, fix_reg, fix_val);
1690 rc = r820t_write_reg(priv, var_reg, var_val);
1694 rc = r820t_multi_read(priv);
1699 if (fix_reg == 0x08) {
1700 iq[i].gain_x = fix_val;
1701 iq[i].phase_y = var_val;
1703 iq[i].phase_y = fix_val;
1704 iq[i].gain_x = var_val;
1707 if (i == 0) { /* try right-side point */
1709 } else if (i == 1) { /* try left-side point */
1710 /* if absolute location is 1, change I/Q direction */
1711 if ((var_val & 0x1f) < 0x02) {
1712 tmp = 2 - (var_val & 0x1f);
1714 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1715 if (var_val & 0x20) {
1719 var_val |= 0x20 | tmp;
1730 static int r820t_section(struct r820t_priv *priv,
1731 struct r820t_sect_type *iq_point)
1734 struct r820t_sect_type compare_iq[3], compare_bet[3];
1736 /* Try X-1 column and save min result to compare_bet[0] */
1737 if (!(iq_point->gain_x & 0x1f))
1738 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
1740 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
1741 compare_iq[0].phase_y = iq_point->phase_y;
1744 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1745 compare_iq[0].phase_y, 0x08);
1749 r820t_compre_cor(compare_iq);
1751 compare_bet[0] = compare_iq[0];
1753 /* Try X column and save min result to compare_bet[1] */
1754 compare_iq[0].gain_x = iq_point->gain_x;
1755 compare_iq[0].phase_y = iq_point->phase_y;
1757 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1758 compare_iq[0].phase_y, 0x08);
1762 r820t_compre_cor(compare_iq);
1764 compare_bet[1] = compare_iq[0];
1766 /* Try X+1 column and save min result to compare_bet[2] */
1767 if ((iq_point->gain_x & 0x1f) == 0x00)
1768 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
1770 compare_iq[0].gain_x = iq_point->gain_x + 1;
1771 compare_iq[0].phase_y = iq_point->phase_y;
1773 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1774 compare_iq[0].phase_y, 0x08);
1778 r820t_compre_cor(compare_iq);
1780 compare_bet[2] = compare_iq[0];
1782 r820t_compre_cor(compare_bet);
1784 *iq_point = compare_bet[0];
1789 static int r820t_vga_adjust(struct r820t_priv *priv)
1794 /* increase vga power to let image significant */
1795 for (vga_count = 12; vga_count < 16; vga_count++) {
1796 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1800 usleep_range(10000, 11000);
1802 rc = r820t_multi_read(priv);
1813 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1815 struct r820t_sect_type compare_iq[3];
1817 u8 x_direction = 0; /* 1:x, 0:y */
1818 u8 dir_reg, other_reg;
1820 r820t_vga_adjust(priv);
1822 rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1826 if (x_direction == 1) {
1834 /* compare and find min of 3 points. determine i/q direction */
1835 r820t_compre_cor(compare_iq);
1837 /* increase step to find min value of this direction */
1838 rc = r820t_compre_step(priv, compare_iq, dir_reg);
1842 /* the other direction */
1843 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1844 compare_iq[0].phase_y, dir_reg);
1848 /* compare and find min of 3 points. determine i/q direction */
1849 r820t_compre_cor(compare_iq);
1851 /* increase step to find min value on this direction */
1852 rc = r820t_compre_step(priv, compare_iq, other_reg);
1856 /* check 3 points again */
1857 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1858 compare_iq[0].phase_y, other_reg);
1862 r820t_compre_cor(compare_iq);
1864 /* section-9 check */
1865 rc = r820t_section(priv, compare_iq);
1867 *iq_pont = compare_iq[0];
1869 /* reset gain/phase control setting */
1870 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1874 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1879 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1883 r820t_vga_adjust(priv);
1886 * search surrounding points from previous point
1887 * try (x-1), (x), (x+1) columns, and find min IMR result point
1889 rc = r820t_section(priv, iq_pont);
1896 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1898 struct r820t_sect_type imr_point;
1900 u32 ring_vco, ring_freq, ring_ref;
1902 int reg18, reg19, reg1f;
1904 if (priv->cfg->xtal > 24000000)
1905 ring_ref = priv->cfg->xtal / 2000;
1907 ring_ref = priv->cfg->xtal / 1000;
1910 for (n = 0; n < 16; n++) {
1911 if ((16 + n) * 8 * ring_ref >= 3100000) {
1917 reg18 = r820t_read_cache_reg(priv, 0x18);
1918 reg19 = r820t_read_cache_reg(priv, 0x19);
1919 reg1f = r820t_read_cache_reg(priv, 0x1f);
1921 reg18 &= 0xf0; /* set ring[3:0] */
1924 ring_vco = (16 + n_ring) * 8 * ring_ref;
1926 reg18 &= 0xdf; /* clear ring_se23 */
1927 reg19 &= 0xfc; /* clear ring_seldiv */
1928 reg1f &= 0xfc; /* clear ring_att */
1932 ring_freq = ring_vco / 48;
1933 reg18 |= 0x20; /* ring_se23 = 1 */
1934 reg19 |= 0x03; /* ring_seldiv = 3 */
1935 reg1f |= 0x02; /* ring_att 10 */
1938 ring_freq = ring_vco / 16;
1939 reg18 |= 0x00; /* ring_se23 = 0 */
1940 reg19 |= 0x02; /* ring_seldiv = 2 */
1941 reg1f |= 0x00; /* pw_ring 00 */
1944 ring_freq = ring_vco / 8;
1945 reg18 |= 0x00; /* ring_se23 = 0 */
1946 reg19 |= 0x01; /* ring_seldiv = 1 */
1947 reg1f |= 0x03; /* pw_ring 11 */
1950 ring_freq = ring_vco / 6;
1951 reg18 |= 0x20; /* ring_se23 = 1 */
1952 reg19 |= 0x00; /* ring_seldiv = 0 */
1953 reg1f |= 0x03; /* pw_ring 11 */
1956 ring_freq = ring_vco / 4;
1957 reg18 |= 0x00; /* ring_se23 = 0 */
1958 reg19 |= 0x00; /* ring_seldiv = 0 */
1959 reg1f |= 0x01; /* pw_ring 01 */
1962 ring_freq = ring_vco / 4;
1963 reg18 |= 0x00; /* ring_se23 = 0 */
1964 reg19 |= 0x00; /* ring_seldiv = 0 */
1965 reg1f |= 0x01; /* pw_ring 01 */
1970 /* write pw_ring, n_ring, ringdiv2 registers */
1972 /* n_ring, ring_se23 */
1973 rc = r820t_write_reg(priv, 0x18, reg18);
1978 rc = r820t_write_reg(priv, 0x19, reg19);
1983 rc = r820t_write_reg(priv, 0x1f, reg1f);
1987 /* mux input freq ~ rf_in freq */
1988 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1992 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1993 (ring_freq - 5300) * 1000);
1994 if (!priv->has_lock)
2000 rc = r820t_iq(priv, &imr_point);
2002 imr_point.gain_x = priv->imr_data[3].gain_x;
2003 imr_point.phase_y = priv->imr_data[3].phase_y;
2004 imr_point.value = priv->imr_data[3].value;
2006 rc = r820t_f_imr(priv, &imr_point);
2011 /* save IMR value */
2014 priv->imr_data[0].gain_x = imr_point.gain_x;
2015 priv->imr_data[0].phase_y = imr_point.phase_y;
2016 priv->imr_data[0].value = imr_point.value;
2019 priv->imr_data[1].gain_x = imr_point.gain_x;
2020 priv->imr_data[1].phase_y = imr_point.phase_y;
2021 priv->imr_data[1].value = imr_point.value;
2024 priv->imr_data[2].gain_x = imr_point.gain_x;
2025 priv->imr_data[2].phase_y = imr_point.phase_y;
2026 priv->imr_data[2].value = imr_point.value;
2029 priv->imr_data[3].gain_x = imr_point.gain_x;
2030 priv->imr_data[3].phase_y = imr_point.phase_y;
2031 priv->imr_data[3].value = imr_point.value;
2034 priv->imr_data[4].gain_x = imr_point.gain_x;
2035 priv->imr_data[4].phase_y = imr_point.phase_y;
2036 priv->imr_data[4].value = imr_point.value;
2039 priv->imr_data[4].gain_x = imr_point.gain_x;
2040 priv->imr_data[4].phase_y = imr_point.phase_y;
2041 priv->imr_data[4].value = imr_point.value;
2048 static int r820t_imr_callibrate(struct r820t_priv *priv)
2053 if (priv->init_done)
2056 /* Detect Xtal capacitance */
2057 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2058 (priv->cfg->rafael_chip == CHIP_R828S) ||
2059 (priv->cfg->rafael_chip == CHIP_R820C)) {
2060 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2062 /* Initialize registers */
2063 rc = r820t_write(priv, 0x05,
2064 r820t_init_array, sizeof(r820t_init_array));
2067 for (i = 0; i < 3; i++) {
2068 rc = r820t_xtal_check(priv);
2071 if (!i || rc > xtal_cap)
2074 priv->xtal_cap_sel = xtal_cap;
2078 * Disables IMR callibration. That emulates the same behaviour
2079 * as what is done by rtl-sdr userspace library. Useful for testing
2082 priv->init_done = true;
2087 /* Initialize registers */
2088 rc = r820t_write(priv, 0x05,
2089 r820t_init_array, sizeof(r820t_init_array));
2093 rc = r820t_imr_prepare(priv);
2097 rc = r820t_imr(priv, 3, true);
2100 rc = r820t_imr(priv, 1, false);
2103 rc = r820t_imr(priv, 0, false);
2106 rc = r820t_imr(priv, 2, false);
2109 rc = r820t_imr(priv, 4, false);
2113 priv->init_done = true;
2114 priv->imr_done = true;
2120 /* Not used, for now */
2121 static int r820t_gpio(struct r820t_priv *priv, bool enable)
2123 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2128 * r820t frontend operations and tuner attach code
2130 * All driver locks and i2c control are only in this part of the code
2133 static int r820t_init(struct dvb_frontend *fe)
2135 struct r820t_priv *priv = fe->tuner_priv;
2138 tuner_dbg("%s:\n", __func__);
2140 mutex_lock(&priv->lock);
2141 if (fe->ops.i2c_gate_ctrl)
2142 fe->ops.i2c_gate_ctrl(fe, 1);
2144 rc = r820t_imr_callibrate(priv);
2148 /* Initialize registers */
2149 rc = r820t_write(priv, 0x05,
2150 r820t_init_array, sizeof(r820t_init_array));
2153 if (fe->ops.i2c_gate_ctrl)
2154 fe->ops.i2c_gate_ctrl(fe, 0);
2155 mutex_unlock(&priv->lock);
2158 tuner_dbg("%s: failed=%d\n", __func__, rc);
2162 static int r820t_sleep(struct dvb_frontend *fe)
2164 struct r820t_priv *priv = fe->tuner_priv;
2167 tuner_dbg("%s:\n", __func__);
2169 mutex_lock(&priv->lock);
2170 if (fe->ops.i2c_gate_ctrl)
2171 fe->ops.i2c_gate_ctrl(fe, 1);
2173 rc = r820t_standby(priv);
2175 if (fe->ops.i2c_gate_ctrl)
2176 fe->ops.i2c_gate_ctrl(fe, 0);
2177 mutex_unlock(&priv->lock);
2179 tuner_dbg("%s: failed=%d\n", __func__, rc);
2183 static int r820t_set_analog_freq(struct dvb_frontend *fe,
2184 struct analog_parameters *p)
2186 struct r820t_priv *priv = fe->tuner_priv;
2190 tuner_dbg("%s called\n", __func__);
2192 /* if std is not defined, choose one */
2194 p->std = V4L2_STD_MN;
2196 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2201 mutex_lock(&priv->lock);
2202 if (fe->ops.i2c_gate_ctrl)
2203 fe->ops.i2c_gate_ctrl(fe, 1);
2205 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2206 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2208 if (fe->ops.i2c_gate_ctrl)
2209 fe->ops.i2c_gate_ctrl(fe, 0);
2210 mutex_unlock(&priv->lock);
2215 static int r820t_set_params(struct dvb_frontend *fe)
2217 struct r820t_priv *priv = fe->tuner_priv;
2218 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2222 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2223 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2225 mutex_lock(&priv->lock);
2226 if (fe->ops.i2c_gate_ctrl)
2227 fe->ops.i2c_gate_ctrl(fe, 1);
2229 bw = (c->bandwidth_hz + 500000) / 1000000;
2233 rc = generic_set_freq(fe, c->frequency, bw,
2234 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2236 if (fe->ops.i2c_gate_ctrl)
2237 fe->ops.i2c_gate_ctrl(fe, 0);
2238 mutex_unlock(&priv->lock);
2241 tuner_dbg("%s: failed=%d\n", __func__, rc);
2245 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2247 struct r820t_priv *priv = fe->tuner_priv;
2250 mutex_lock(&priv->lock);
2251 if (fe->ops.i2c_gate_ctrl)
2252 fe->ops.i2c_gate_ctrl(fe, 1);
2254 if (priv->has_lock) {
2255 rc = r820t_read_gain(priv);
2259 /* A higher gain at LNA means a lower signal strength */
2260 *strength = (45 - rc) << 4 | 0xff;
2261 if (*strength == 0xff)
2268 if (fe->ops.i2c_gate_ctrl)
2269 fe->ops.i2c_gate_ctrl(fe, 0);
2270 mutex_unlock(&priv->lock);
2272 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2274 priv->has_lock ? "PLL locked" : "no signal",
2280 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2282 struct r820t_priv *priv = fe->tuner_priv;
2284 tuner_dbg("%s:\n", __func__);
2286 *frequency = priv->int_freq;
2291 static int r820t_release(struct dvb_frontend *fe)
2293 struct r820t_priv *priv = fe->tuner_priv;
2295 tuner_dbg("%s:\n", __func__);
2297 mutex_lock(&r820t_list_mutex);
2300 hybrid_tuner_release_state(priv);
2302 mutex_unlock(&r820t_list_mutex);
2304 fe->tuner_priv = NULL;
2309 static const struct dvb_tuner_ops r820t_tuner_ops = {
2311 .name = "Rafael Micro R820T",
2312 .frequency_min = 42000000,
2313 .frequency_max = 1002000000,
2316 .release = r820t_release,
2317 .sleep = r820t_sleep,
2318 .set_params = r820t_set_params,
2319 .set_analog_params = r820t_set_analog_freq,
2320 .get_if_frequency = r820t_get_if_frequency,
2321 .get_rf_strength = r820t_signal,
2324 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2325 struct i2c_adapter *i2c,
2326 const struct r820t_config *cfg)
2328 struct r820t_priv *priv;
2333 mutex_lock(&r820t_list_mutex);
2335 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2336 hybrid_tuner_instance_list,
2341 /* memory allocation failure */
2344 /* new tuner instance */
2347 mutex_init(&priv->lock);
2349 fe->tuner_priv = priv;
2352 /* existing tuner instance */
2353 fe->tuner_priv = priv;
2357 if (fe->ops.i2c_gate_ctrl)
2358 fe->ops.i2c_gate_ctrl(fe, 1);
2360 /* check if the tuner is there */
2361 rc = r820t_read(priv, 0x00, data, sizeof(data));
2365 rc = r820t_sleep(fe);
2369 tuner_info("Rafael Micro r820t successfully identified\n");
2371 if (fe->ops.i2c_gate_ctrl)
2372 fe->ops.i2c_gate_ctrl(fe, 0);
2374 mutex_unlock(&r820t_list_mutex);
2376 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2377 sizeof(struct dvb_tuner_ops));
2381 if (fe->ops.i2c_gate_ctrl)
2382 fe->ops.i2c_gate_ctrl(fe, 0);
2385 mutex_unlock(&r820t_list_mutex);
2387 tuner_info("%s: failed=%d\n", __func__, rc);
2391 EXPORT_SYMBOL_GPL(r820t_attach);
2393 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2394 MODULE_AUTHOR("Mauro Carvalho Chehab");
2395 MODULE_LICENSE("GPL");