2 * Fitipower FC0013 tuner driver
4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
5 * partially based on driver code from Fitipower
6 * Copyright (C) 2010 Fitipower Integrated Technology Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 #include "fc0013-priv.h"
23 static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val)
25 u8 buf[2] = {reg, val};
26 struct i2c_msg msg = {
27 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2
30 if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
31 err("I2C write reg failed, reg: %02x, val: %02x", reg, val);
37 static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val)
39 struct i2c_msg msg[2] = {
40 { .addr = priv->addr, .flags = 0, .buf = ®, .len = 1 },
41 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 },
44 if (i2c_transfer(priv->i2c, msg, 2) != 2) {
45 err("I2C read reg failed, reg: %02x", reg);
51 static void fc0013_release(struct dvb_frontend *fe)
53 kfree(fe->tuner_priv);
54 fe->tuner_priv = NULL;
57 static int fc0013_init(struct dvb_frontend *fe)
59 struct fc0013_priv *priv = fe->tuner_priv;
61 unsigned char reg[] = {
62 0x00, /* reg. 0x00: dummy */
69 0x0a, /* reg. 0x07: CHECK */
70 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
72 0x6f, /* reg. 0x09: enable LoopThrough */
73 0xb8, /* reg. 0x0a: Disable LO Test Buffer */
74 0x82, /* reg. 0x0b: CHECK */
75 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
76 0x01, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */
83 0x50, /* reg. 0x14: DVB-t High Gain, UHF.
84 Middle Gain: 0x48, Low Gain: 0x40 */
88 switch (priv->xtal_freq) {
90 case FC_XTAL_28_8_MHZ:
98 if (priv->dual_master)
101 if (fe->ops.i2c_gate_ctrl)
102 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
104 for (i = 1; i < sizeof(reg); i++) {
105 ret = fc0013_writereg(priv, i, reg[i]);
110 if (fe->ops.i2c_gate_ctrl)
111 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
114 err("fc0013_writereg failed: %d", ret);
119 static int fc0013_sleep(struct dvb_frontend *fe)
121 /* nothing to do here */
125 int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
127 struct fc0013_priv *priv = fe->tuner_priv;
132 if (fe->ops.i2c_gate_ctrl)
133 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
135 /* push rc_cal value, get rc_cal value */
136 ret = fc0013_writereg(priv, 0x10, 0x00);
140 /* get rc_cal value */
141 ret = fc0013_readreg(priv, 0x10, &rc_cal);
147 val = (int)rc_cal + rc_val;
150 ret = fc0013_writereg(priv, 0x0d, 0x11);
154 /* modify rc_cal value */
156 ret = fc0013_writereg(priv, 0x10, 0x0f);
158 ret = fc0013_writereg(priv, 0x10, 0x00);
160 ret = fc0013_writereg(priv, 0x10, (u8)val);
163 if (fe->ops.i2c_gate_ctrl)
164 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
168 EXPORT_SYMBOL(fc0013_rc_cal_add);
170 int fc0013_rc_cal_reset(struct dvb_frontend *fe)
172 struct fc0013_priv *priv = fe->tuner_priv;
175 if (fe->ops.i2c_gate_ctrl)
176 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
178 ret = fc0013_writereg(priv, 0x0d, 0x01);
180 ret = fc0013_writereg(priv, 0x10, 0x00);
182 if (fe->ops.i2c_gate_ctrl)
183 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
187 EXPORT_SYMBOL(fc0013_rc_cal_reset);
189 static int fc0013_set_vhf_track(struct fc0013_priv *priv, u32 freq)
194 ret = fc0013_readreg(priv, 0x1d, &tmp);
198 if (freq <= 177500) { /* VHF Track: 7 */
199 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
200 } else if (freq <= 184500) { /* VHF Track: 6 */
201 ret = fc0013_writereg(priv, 0x1d, tmp | 0x18);
202 } else if (freq <= 191500) { /* VHF Track: 5 */
203 ret = fc0013_writereg(priv, 0x1d, tmp | 0x14);
204 } else if (freq <= 198500) { /* VHF Track: 4 */
205 ret = fc0013_writereg(priv, 0x1d, tmp | 0x10);
206 } else if (freq <= 205500) { /* VHF Track: 3 */
207 ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c);
208 } else if (freq <= 219500) { /* VHF Track: 2 */
209 ret = fc0013_writereg(priv, 0x1d, tmp | 0x08);
210 } else if (freq < 300000) { /* VHF Track: 1 */
211 ret = fc0013_writereg(priv, 0x1d, tmp | 0x04);
212 } else { /* UHF and GPS */
213 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
219 static int fc0013_set_params(struct dvb_frontend *fe)
221 struct fc0013_priv *priv = fe->tuner_priv;
223 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
224 u32 freq = p->frequency / 1000;
225 u32 delsys = p->delivery_system;
226 unsigned char reg[7], am, pm, multi, tmp;
228 unsigned short xtal_freq_khz_2, xin, xdiv;
229 bool vco_select = false;
232 ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
233 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1));
238 switch (priv->xtal_freq) {
240 xtal_freq_khz_2 = 27000 / 2;
243 xtal_freq_khz_2 = 36000 / 2;
245 case FC_XTAL_28_8_MHZ:
247 xtal_freq_khz_2 = 28800 / 2;
251 if (fe->ops.i2c_gate_ctrl)
252 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
255 ret = fc0013_set_vhf_track(priv, freq);
260 /* enable VHF filter */
261 ret = fc0013_readreg(priv, 0x07, &tmp);
264 ret = fc0013_writereg(priv, 0x07, tmp | 0x10);
268 /* disable UHF & disable GPS */
269 ret = fc0013_readreg(priv, 0x14, &tmp);
272 ret = fc0013_writereg(priv, 0x14, tmp & 0x1f);
275 } else if (freq <= 862000) {
276 /* disable VHF filter */
277 ret = fc0013_readreg(priv, 0x07, &tmp);
280 ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
284 /* enable UHF & disable GPS */
285 ret = fc0013_readreg(priv, 0x14, &tmp);
288 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x40);
292 /* disable VHF filter */
293 ret = fc0013_readreg(priv, 0x07, &tmp);
296 ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
300 /* disable UHF & enable GPS */
301 ret = fc0013_readreg(priv, 0x14, &tmp);
304 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x20);
309 /* select frequency divider and the frequency of VCO */
310 if (freq < 37084) { /* freq * 96 < 3560000 */
314 } else if (freq < 55625) { /* freq * 64 < 3560000 */
318 } else if (freq < 74167) { /* freq * 48 < 3560000 */
322 } else if (freq < 111250) { /* freq * 32 < 3560000 */
326 } else if (freq < 148334) { /* freq * 24 < 3560000 */
330 } else if (freq < 222500) { /* freq * 16 < 3560000 */
334 } else if (freq < 296667) { /* freq * 12 < 3560000 */
338 } else if (freq < 445000) { /* freq * 8 < 3560000 */
342 } else if (freq < 593334) { /* freq * 6 < 3560000 */
346 } else if (freq < 950000) { /* freq * 4 < 3800000 */
356 f_vco = freq * multi;
358 if (f_vco >= 3060000) {
364 /* From divided value (XDIV) determined the FA and FP value */
365 xdiv = (unsigned short)(f_vco / xtal_freq_khz_2);
366 if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2))
369 pm = (unsigned char)(xdiv / 8);
370 am = (unsigned char)(xdiv - (8 * pm));
380 /* fix for frequency less than 45 MHz */
388 /* From VCO frequency determines the XIN ( fractional part of Delta
389 Sigma PLL) and divided value (XDIV) */
390 xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2);
391 xin = (xin << 15) / xtal_freq_khz_2;
398 if (delsys == SYS_DVBT) {
399 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
400 switch (p->bandwidth_hz) {
412 err("%s: modulation type not supported!", __func__);
416 /* modified for Realtek demod */
419 for (i = 1; i <= 6; i++) {
420 ret = fc0013_writereg(priv, i, reg[i]);
425 ret = fc0013_readreg(priv, 0x11, &tmp);
429 ret = fc0013_writereg(priv, 0x11, tmp | 0x04);
431 ret = fc0013_writereg(priv, 0x11, tmp & 0xfb);
435 /* VCO Calibration */
436 ret = fc0013_writereg(priv, 0x0e, 0x80);
438 ret = fc0013_writereg(priv, 0x0e, 0x00);
440 /* VCO Re-Calibration if needed */
442 ret = fc0013_writereg(priv, 0x0e, 0x00);
446 ret = fc0013_readreg(priv, 0x0e, &tmp);
457 ret = fc0013_writereg(priv, 0x06, reg[6]);
459 ret = fc0013_writereg(priv, 0x0e, 0x80);
461 ret = fc0013_writereg(priv, 0x0e, 0x00);
466 ret = fc0013_writereg(priv, 0x06, reg[6]);
468 ret = fc0013_writereg(priv, 0x0e, 0x80);
470 ret = fc0013_writereg(priv, 0x0e, 0x00);
474 priv->frequency = p->frequency;
475 priv->bandwidth = p->bandwidth_hz;
478 if (fe->ops.i2c_gate_ctrl)
479 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
481 warn("%s: failed: %d", __func__, ret);
485 static int fc0013_get_frequency(struct dvb_frontend *fe, u32 *frequency)
487 struct fc0013_priv *priv = fe->tuner_priv;
488 *frequency = priv->frequency;
492 static int fc0013_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
499 static int fc0013_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
501 struct fc0013_priv *priv = fe->tuner_priv;
502 *bandwidth = priv->bandwidth;
506 #define INPUT_ADC_LEVEL -8
508 static int fc0013_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
510 struct fc0013_priv *priv = fe->tuner_priv;
513 int int_temp, lna_gain, int_lna, tot_agc_gain, power;
514 static const int fc0013_lna_gain_table[] = {
526 if (fe->ops.i2c_gate_ctrl)
527 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
529 ret = fc0013_writereg(priv, 0x13, 0x00);
533 ret = fc0013_readreg(priv, 0x13, &tmp);
538 ret = fc0013_readreg(priv, 0x14, &tmp);
541 lna_gain = tmp & 0x1f;
543 if (fe->ops.i2c_gate_ctrl)
544 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
546 if (lna_gain < ARRAY_SIZE(fc0013_lna_gain_table)) {
547 int_lna = fc0013_lna_gain_table[lna_gain];
548 tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 +
549 (int_temp & 0x1f)) * 2;
550 power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10;
553 *strength = 255; /* 100% */
554 else if (power < -95)
557 *strength = (power + 95) * 255 / 140;
559 *strength |= *strength << 8;
567 if (fe->ops.i2c_gate_ctrl)
568 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
571 warn("%s: failed: %d", __func__, ret);
575 static const struct dvb_tuner_ops fc0013_tuner_ops = {
577 .name = "Fitipower FC0013",
579 .frequency_min = 37000000, /* estimate */
580 .frequency_max = 1680000000, /* CHECK */
584 .release = fc0013_release,
587 .sleep = fc0013_sleep,
589 .set_params = fc0013_set_params,
591 .get_frequency = fc0013_get_frequency,
592 .get_if_frequency = fc0013_get_if_frequency,
593 .get_bandwidth = fc0013_get_bandwidth,
595 .get_rf_strength = fc0013_get_rf_strength,
598 struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
599 struct i2c_adapter *i2c, u8 i2c_address, int dual_master,
600 enum fc001x_xtal_freq xtal_freq)
602 struct fc0013_priv *priv = NULL;
604 priv = kzalloc(sizeof(struct fc0013_priv), GFP_KERNEL);
609 priv->dual_master = dual_master;
610 priv->addr = i2c_address;
611 priv->xtal_freq = xtal_freq;
613 info("Fitipower FC0013 successfully attached.");
615 fe->tuner_priv = priv;
617 memcpy(&fe->ops.tuner_ops, &fc0013_tuner_ops,
618 sizeof(struct dvb_tuner_ops));
622 EXPORT_SYMBOL(fc0013_attach);
624 MODULE_DESCRIPTION("Fitipower FC0013 silicon tuner driver");
625 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
626 MODULE_LICENSE("GPL");
627 MODULE_VERSION("0.2");