2 * Fitipower FC0012 tuner driver
4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include "fc0012-priv.h"
20 static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val)
22 u8 buf[2] = {reg, val};
23 struct i2c_msg msg = {
24 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
27 if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
28 dev_err(&priv->i2c->dev,
29 "%s: I2C write reg failed, reg: %02x, val: %02x\n",
30 KBUILD_MODNAME, reg, val);
36 static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val)
38 struct i2c_msg msg[2] = {
39 { .addr = priv->cfg->i2c_address, .flags = 0,
40 .buf = ®, .len = 1 },
41 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
42 .buf = val, .len = 1 },
45 if (i2c_transfer(priv->i2c, msg, 2) != 2) {
46 dev_err(&priv->i2c->dev,
47 "%s: I2C read reg failed, reg: %02x\n",
54 static void fc0012_release(struct dvb_frontend *fe)
56 kfree(fe->tuner_priv);
57 fe->tuner_priv = NULL;
60 static int fc0012_init(struct dvb_frontend *fe)
62 struct fc0012_priv *priv = fe->tuner_priv;
64 unsigned char reg[] = {
65 0x00, /* dummy reg. 0 */
70 0x0f, /* reg. 0x05: may also be 0x0a */
71 0x00, /* reg. 0x06: divider 2, VCO slow */
72 0x00, /* reg. 0x07: may also be 0x0f */
73 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
75 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */
76 0xb8, /* reg. 0x0a: Disable LO Test Buffer */
77 0x82, /* reg. 0x0b: Output Clock is same as clock frequency,
79 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
80 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */
83 0x00, /* reg. 0x10: may also be 0x0d */
85 0x1f, /* reg. 0x12: Set to maximum gain */
86 0x08, /* reg. 0x13: Set to Middle Gain: 0x08,
87 Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */
89 0x04, /* reg. 0x15: Enable LNA COMPS */
92 switch (priv->cfg->xtal_freq) {
94 case FC_XTAL_28_8_MHZ:
102 if (priv->cfg->dual_master)
105 if (priv->cfg->loop_through)
108 if (fe->ops.i2c_gate_ctrl)
109 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
111 for (i = 1; i < sizeof(reg); i++) {
112 ret = fc0012_writereg(priv, i, reg[i]);
117 if (fe->ops.i2c_gate_ctrl)
118 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
121 dev_err(&priv->i2c->dev, "%s: fc0012_writereg failed: %d\n",
122 KBUILD_MODNAME, ret);
127 static int fc0012_set_params(struct dvb_frontend *fe)
129 struct fc0012_priv *priv = fe->tuner_priv;
131 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
132 u32 freq = p->frequency / 1000;
133 u32 delsys = p->delivery_system;
134 unsigned char reg[7], am, pm, multi, tmp;
136 unsigned short xtal_freq_khz_2, xin, xdiv;
137 bool vco_select = false;
140 ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
141 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1));
146 switch (priv->cfg->xtal_freq) {
148 xtal_freq_khz_2 = 27000 / 2;
151 xtal_freq_khz_2 = 36000 / 2;
153 case FC_XTAL_28_8_MHZ:
155 xtal_freq_khz_2 = 28800 / 2;
159 /* select frequency divider and the frequency of VCO */
160 if (freq < 37084) { /* freq * 96 < 3560000 */
164 } else if (freq < 55625) { /* freq * 64 < 3560000 */
168 } else if (freq < 74167) { /* freq * 48 < 3560000 */
172 } else if (freq < 111250) { /* freq * 32 < 3560000 */
176 } else if (freq < 148334) { /* freq * 24 < 3560000 */
180 } else if (freq < 222500) { /* freq * 16 < 3560000 */
184 } else if (freq < 296667) { /* freq * 12 < 3560000 */
188 } else if (freq < 445000) { /* freq * 8 < 3560000 */
192 } else if (freq < 593334) { /* freq * 6 < 3560000 */
202 f_vco = freq * multi;
204 if (f_vco >= 3060000) {
210 /* From divided value (XDIV) determined the FA and FP value */
211 xdiv = (unsigned short)(f_vco / xtal_freq_khz_2);
212 if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2))
215 pm = (unsigned char)(xdiv / 8);
216 am = (unsigned char)(xdiv - (8 * pm));
226 /* fix for frequency less than 45 MHz */
234 /* From VCO frequency determines the XIN ( fractional part of Delta
235 Sigma PLL) and divided value (XDIV) */
236 xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2);
237 xin = (xin << 15) / xtal_freq_khz_2;
241 reg[3] = xin >> 8; /* xin with 9 bit resolution */
244 if (delsys == SYS_DVBT) {
245 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
246 switch (p->bandwidth_hz) {
258 dev_err(&priv->i2c->dev, "%s: modulation type not supported!\n",
263 /* modified for Realtek demod */
266 if (fe->ops.i2c_gate_ctrl)
267 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
269 for (i = 1; i <= 6; i++) {
270 ret = fc0012_writereg(priv, i, reg[i]);
275 /* VCO Calibration */
276 ret = fc0012_writereg(priv, 0x0e, 0x80);
278 ret = fc0012_writereg(priv, 0x0e, 0x00);
280 /* VCO Re-Calibration if needed */
282 ret = fc0012_writereg(priv, 0x0e, 0x00);
286 ret = fc0012_readreg(priv, 0x0e, &tmp);
297 ret = fc0012_writereg(priv, 0x06, reg[6]);
299 ret = fc0012_writereg(priv, 0x0e, 0x80);
301 ret = fc0012_writereg(priv, 0x0e, 0x00);
306 ret = fc0012_writereg(priv, 0x06, reg[6]);
308 ret = fc0012_writereg(priv, 0x0e, 0x80);
310 ret = fc0012_writereg(priv, 0x0e, 0x00);
314 priv->frequency = p->frequency;
315 priv->bandwidth = p->bandwidth_hz;
318 if (fe->ops.i2c_gate_ctrl)
319 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
321 dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n",
322 KBUILD_MODNAME, __func__, ret);
326 static int fc0012_get_frequency(struct dvb_frontend *fe, u32 *frequency)
328 struct fc0012_priv *priv = fe->tuner_priv;
329 *frequency = priv->frequency;
333 static int fc0012_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
335 *frequency = 0; /* Zero-IF */
339 static int fc0012_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
341 struct fc0012_priv *priv = fe->tuner_priv;
342 *bandwidth = priv->bandwidth;
346 #define INPUT_ADC_LEVEL -8
348 static int fc0012_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
350 struct fc0012_priv *priv = fe->tuner_priv;
353 int int_temp, lna_gain, int_lna, tot_agc_gain, power;
354 static const int fc0012_lna_gain_table[] = {
366 if (fe->ops.i2c_gate_ctrl)
367 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
369 ret = fc0012_writereg(priv, 0x12, 0x00);
373 ret = fc0012_readreg(priv, 0x12, &tmp);
378 ret = fc0012_readreg(priv, 0x13, &tmp);
381 lna_gain = tmp & 0x1f;
383 if (fe->ops.i2c_gate_ctrl)
384 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
386 if (lna_gain < ARRAY_SIZE(fc0012_lna_gain_table)) {
387 int_lna = fc0012_lna_gain_table[lna_gain];
388 tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 +
389 (int_temp & 0x1f)) * 2;
390 power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10;
393 *strength = 255; /* 100% */
394 else if (power < -95)
397 *strength = (power + 95) * 255 / 140;
399 *strength |= *strength << 8;
407 if (fe->ops.i2c_gate_ctrl)
408 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
411 dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n",
412 KBUILD_MODNAME, __func__, ret);
416 static const struct dvb_tuner_ops fc0012_tuner_ops = {
418 .name = "Fitipower FC0012",
420 .frequency_min = 37000000, /* estimate */
421 .frequency_max = 862000000, /* estimate */
425 .release = fc0012_release,
429 .set_params = fc0012_set_params,
431 .get_frequency = fc0012_get_frequency,
432 .get_if_frequency = fc0012_get_if_frequency,
433 .get_bandwidth = fc0012_get_bandwidth,
435 .get_rf_strength = fc0012_get_rf_strength,
438 struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe,
439 struct i2c_adapter *i2c, const struct fc0012_config *cfg)
441 struct fc0012_priv *priv;
445 if (fe->ops.i2c_gate_ctrl)
446 fe->ops.i2c_gate_ctrl(fe, 1);
448 priv = kzalloc(sizeof(struct fc0012_priv), GFP_KERNEL);
451 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
458 /* check if the tuner is there */
459 ret = fc0012_readreg(priv, 0x00, &chip_id);
463 dev_dbg(&i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
473 dev_info(&i2c->dev, "%s: Fitipower FC0012 successfully identified\n",
476 if (priv->cfg->loop_through) {
477 ret = fc0012_writereg(priv, 0x09, 0x6f);
483 * TODO: Clock out en or div?
484 * For dual tuner configuration clearing bit [0] is required.
486 if (priv->cfg->clock_out) {
487 ret = fc0012_writereg(priv, 0x0b, 0x82);
492 fe->tuner_priv = priv;
493 memcpy(&fe->ops.tuner_ops, &fc0012_tuner_ops,
494 sizeof(struct dvb_tuner_ops));
497 if (fe->ops.i2c_gate_ctrl)
498 fe->ops.i2c_gate_ctrl(fe, 0);
501 dev_dbg(&i2c->dev, "%s: failed: %d\n", __func__, ret);
508 EXPORT_SYMBOL(fc0012_attach);
510 MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver");
511 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
512 MODULE_LICENSE("GPL");
513 MODULE_VERSION("0.6");