2 * Driver for Allwinner sunXi IR controller
4 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
5 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
8 * Copyright (C) 2007-2012 Daniel Wang
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/of_platform.h>
26 #include <linux/reset.h>
27 #include <media/rc-core.h>
29 #define SUNXI_IR_DEV "sunxi-ir"
33 #define SUNXI_IR_CTL_REG 0x00
35 #define REG_CTL_GEN BIT(0)
37 #define REG_CTL_RXEN BIT(1)
39 #define REG_CTL_MD (BIT(4) | BIT(5))
42 #define SUNXI_IR_RXCTL_REG 0x10
43 /* Pulse Polarity Invert flag */
44 #define REG_RXCTL_RPPI BIT(2)
47 #define SUNXI_IR_RXFIFO_REG 0x20
49 /* Rx Interrupt Enable */
50 #define SUNXI_IR_RXINT_REG 0x2C
51 /* Rx FIFO Overflow */
52 #define REG_RXINT_ROI_EN BIT(0)
54 #define REG_RXINT_RPEI_EN BIT(1)
55 /* Rx FIFO Data Available */
56 #define REG_RXINT_RAI_EN BIT(4)
58 /* Rx FIFO available byte level */
59 #define REG_RXINT_RAL(val) ((val) << 8)
61 /* Rx Interrupt Status */
62 #define SUNXI_IR_RXSTA_REG 0x30
63 /* RX FIFO Get Available Counter */
64 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
65 /* Clear all interrupt status value */
66 #define REG_RXSTA_CLEARALL 0xff
68 /* IR Sample Config */
69 #define SUNXI_IR_CIR_REG 0x34
70 /* CIR_REG register noise threshold */
71 #define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
72 /* CIR_REG register idle threshold */
73 #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
75 /* Required frequency for IR0 or IR1 clock in CIR mode (default) */
76 #define SUNXI_IR_BASE_CLK 8000000
77 /* Noise threshold in samples */
78 #define SUNXI_IR_RXNOISE 1
79 /* Idle Threshold in samples */
80 #define SUNXI_IR_RXIDLE 20
81 /* Time after which device stops sending data in ms */
82 #define SUNXI_IR_TIMEOUT 120
92 struct reset_control *rst;
96 static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
100 unsigned int cnt, rc;
101 struct sunxi_ir *ir = dev_id;
102 DEFINE_IR_RAW_EVENT(rawir);
104 spin_lock(&ir->ir_lock);
106 status = readl(ir->base + SUNXI_IR_RXSTA_REG);
108 /* clean all pending statuses */
109 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
111 if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
112 /* How many messages in fifo */
113 rc = REG_RXSTA_GET_AC(status);
115 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
116 /* If we have data */
117 for (cnt = 0; cnt < rc; cnt++) {
118 /* for each bit in fifo */
119 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
120 rawir.pulse = (dt & 0x80) != 0;
121 rawir.duration = ((dt & 0x7f) + 1) *
122 ir->rc->rx_resolution;
123 ir_raw_event_store_with_filter(ir->rc, &rawir);
127 if (status & REG_RXINT_ROI_EN) {
128 ir_raw_event_reset(ir->rc);
129 } else if (status & REG_RXINT_RPEI_EN) {
130 ir_raw_event_set_idle(ir->rc, true);
131 ir_raw_event_handle(ir->rc);
133 ir_raw_event_handle(ir->rc);
136 spin_unlock(&ir->ir_lock);
141 static int sunxi_ir_probe(struct platform_device *pdev)
144 unsigned long tmp = 0;
146 struct device *dev = &pdev->dev;
147 struct device_node *dn = dev->of_node;
148 struct resource *res;
150 u32 b_clk_freq = SUNXI_IR_BASE_CLK;
152 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
156 spin_lock_init(&ir->ir_lock);
158 if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
164 ir->apb_clk = devm_clk_get(dev, "apb");
165 if (IS_ERR(ir->apb_clk)) {
166 dev_err(dev, "failed to get a apb clock.\n");
167 return PTR_ERR(ir->apb_clk);
169 ir->clk = devm_clk_get(dev, "ir");
170 if (IS_ERR(ir->clk)) {
171 dev_err(dev, "failed to get a ir clock.\n");
172 return PTR_ERR(ir->clk);
175 /* Base clock frequency (optional) */
176 of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
178 /* Reset (optional) */
179 ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
181 return PTR_ERR(ir->rst);
182 ret = reset_control_deassert(ir->rst);
186 ret = clk_set_rate(ir->clk, b_clk_freq);
188 dev_err(dev, "set ir base clock failed!\n");
189 goto exit_reset_assert;
191 dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
193 if (clk_prepare_enable(ir->apb_clk)) {
194 dev_err(dev, "try to enable apb_ir_clk failed\n");
196 goto exit_reset_assert;
199 if (clk_prepare_enable(ir->clk)) {
200 dev_err(dev, "try to enable ir_clk failed\n");
202 goto exit_clkdisable_apb_clk;
206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
207 ir->base = devm_ioremap_resource(dev, res);
208 if (IS_ERR(ir->base)) {
209 dev_err(dev, "failed to map registers\n");
210 ret = PTR_ERR(ir->base);
211 goto exit_clkdisable_clk;
214 ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
216 dev_err(dev, "failed to allocate device\n");
218 goto exit_clkdisable_clk;
222 ir->rc->device_name = SUNXI_IR_DEV;
223 ir->rc->input_phys = "sunxi-ir/input0";
224 ir->rc->input_id.bustype = BUS_HOST;
225 ir->rc->input_id.vendor = 0x0001;
226 ir->rc->input_id.product = 0x0001;
227 ir->rc->input_id.version = 0x0100;
228 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
229 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
230 ir->rc->dev.parent = dev;
231 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
232 /* Frequency after IR internal divider with sample period in ns */
233 ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64));
234 ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
235 ir->rc->driver_name = SUNXI_IR_DEV;
237 ret = rc_register_device(ir->rc);
239 dev_err(dev, "failed to register rc device\n");
243 platform_set_drvdata(pdev, ir);
246 ir->irq = platform_get_irq(pdev, 0);
248 dev_err(dev, "no irq resource\n");
253 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
255 dev_err(dev, "failed request irq\n");
259 /* Enable CIR Mode */
260 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
262 /* Set noise threshold and idle threshold */
263 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
264 ir->base + SUNXI_IR_CIR_REG);
266 /* Invert Input Signal */
267 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
269 /* Clear All Rx Interrupt Status */
270 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
273 * Enable IRQ on overflow, packet end, FIFO available with trigger
276 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
277 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
278 ir->base + SUNXI_IR_RXINT_REG);
280 /* Enable IR Module */
281 tmp = readl(ir->base + SUNXI_IR_CTL_REG);
282 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
284 dev_info(dev, "initialized sunXi IR driver\n");
288 rc_free_device(ir->rc);
290 clk_disable_unprepare(ir->clk);
291 exit_clkdisable_apb_clk:
292 clk_disable_unprepare(ir->apb_clk);
294 reset_control_assert(ir->rst);
299 static int sunxi_ir_remove(struct platform_device *pdev)
302 struct sunxi_ir *ir = platform_get_drvdata(pdev);
304 clk_disable_unprepare(ir->clk);
305 clk_disable_unprepare(ir->apb_clk);
306 reset_control_assert(ir->rst);
308 spin_lock_irqsave(&ir->ir_lock, flags);
310 writel(0, ir->base + SUNXI_IR_RXINT_REG);
311 /* clear All Rx Interrupt Status */
312 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
314 writel(0, ir->base + SUNXI_IR_CTL_REG);
315 spin_unlock_irqrestore(&ir->ir_lock, flags);
317 rc_unregister_device(ir->rc);
321 static const struct of_device_id sunxi_ir_match[] = {
322 { .compatible = "allwinner,sun4i-a10-ir", },
323 { .compatible = "allwinner,sun5i-a13-ir", },
326 MODULE_DEVICE_TABLE(of, sunxi_ir_match);
328 static struct platform_driver sunxi_ir_driver = {
329 .probe = sunxi_ir_probe,
330 .remove = sunxi_ir_remove,
332 .name = SUNXI_IR_DEV,
333 .of_match_table = sunxi_ir_match,
337 module_platform_driver(sunxi_ir_driver);
339 MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
340 MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
341 MODULE_LICENSE("GPL");