drivers/media/rc/ir-hix5hd2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 Linaro Ltd.
   4  * Copyright (c) 2014 HiSilicon Limited.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/property.h>
  15 #include <linux/regmap.h>
  16 #include <media/rc-core.h>
  17
  18 #define IR_ENABLE               0x00
  19 #define IR_CONFIG               0x04
  20 #define CNT_LEADS               0x08
  21 #define CNT_LEADE               0x0c
  22 #define CNT_SLEADE              0x10
  23 #define CNT0_B                  0x14
  24 #define CNT1_B                  0x18
  25 #define IR_BUSY                 0x1c
  26 #define IR_DATAH                0x20
  27 #define IR_DATAL                0x24
  28 #define IR_INTM                 0x28
  29 #define IR_INTS                 0x2c
  30 #define IR_INTC                 0x30
  31 #define IR_START                0x34
  32
  33 /* interrupt mask */
  34 #define INTMS_SYMBRCV           (BIT(24) | BIT(8))
  35 #define INTMS_TIMEOUT           (BIT(25) | BIT(9))
  36 #define INTMS_OVERFLOW          (BIT(26) | BIT(10))
  37 #define INT_CLR_OVERFLOW        BIT(18)
  38 #define INT_CLR_TIMEOUT         BIT(17)
  39 #define INT_CLR_RCV             BIT(16)
  40 #define INT_CLR_RCVTIMEOUT      (BIT(16) | BIT(17))
  41
  42 #define IR_CLK_ENABLE           BIT(4)
  43 #define IR_CLK_RESET            BIT(5)
  44
  45 /* IR_ENABLE register bits */
  46 #define IR_ENABLE_EN            BIT(0)
  47 #define IR_ENABLE_EN_EXTRA      BIT(8)
  48
  49 #define IR_CFG_WIDTH_MASK       0xffff
  50 #define IR_CFG_WIDTH_SHIFT      16
  51 #define IR_CFG_FORMAT_MASK      0x3
  52 #define IR_CFG_FORMAT_SHIFT     14
  53 #define IR_CFG_INT_LEVEL_MASK   0x3f
  54 #define IR_CFG_INT_LEVEL_SHIFT  8
  55 /* only support raw mode */
  56 #define IR_CFG_MODE_RAW         BIT(7)
  57 #define IR_CFG_FREQ_MASK        0x7f
  58 #define IR_CFG_FREQ_SHIFT       0
  59 #define IR_CFG_INT_THRESHOLD    1
  60 /* symbol start from low to high, symbol stream end at high*/
  61 #define IR_CFG_SYMBOL_FMT       0
  62 #define IR_CFG_SYMBOL_MAXWIDTH  0x3e80
  63
  64 #define IR_HIX5HD2_NAME         "hix5hd2-ir"
  65
  66 /* Need to set extra bit for enabling IR */
  67 #define HIX5HD2_FLAG_EXTRA_ENABLE       BIT(0)
  68
  69 struct hix5hd2_soc_data {
  70         u32 clk_reg;
  71         u32 flags;
  72 };
  73
  74 static const struct hix5hd2_soc_data hix5hd2_data = {
  75         .clk_reg = 0x48,
  76 };
  77
  78 static const struct hix5hd2_soc_data hi3796cv300_data = {
  79         .clk_reg = 0x60,
  80         .flags = HIX5HD2_FLAG_EXTRA_ENABLE,
  81 };
  82
  83 struct hix5hd2_ir_priv {
  84         int                     irq;
  85         void __iomem            *base;
  86         struct device           *dev;
  87         struct rc_dev           *rdev;
  88         struct regmap           *regmap;
  89         struct clk              *clock;
  90         unsigned long           rate;
  91         const struct hix5hd2_soc_data *socdata;
  92 };
  93
  94 static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on)
  95 {
  96         u32 clk_reg = dev->socdata->clk_reg;
  97         u32 val;
  98         int ret = 0;
  99
 100         if (dev->regmap) {
 101                 regmap_read(dev->regmap, clk_reg, &val);
 102                 if (on) {
 103                         val &= ~IR_CLK_RESET;
 104                         val |= IR_CLK_ENABLE;
 105                 } else {
 106                         val &= ~IR_CLK_ENABLE;
 107                         val |= IR_CLK_RESET;
 108                 }
 109                 regmap_write(dev->regmap, clk_reg, val);
 110         } else {
 111                 if (on)
 112                         ret = clk_prepare_enable(dev->clock);
 113                 else
 114                         clk_disable_unprepare(dev->clock);
 115         }
 116         return ret;
 117 }
 118
 119 static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv)
 120 {
 121         u32 val = IR_ENABLE_EN;
 122
 123         if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE)
 124                 val |= IR_ENABLE_EN_EXTRA;
 125
 126         writel_relaxed(val, priv->base + IR_ENABLE);
 127 }
 128
 129 static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
 130 {
 131         int timeout = 10000;
 132         u32 val, rate;
 133
 134         hix5hd2_ir_enable(priv);
 135
 136         while (readl_relaxed(priv->base + IR_BUSY)) {
 137                 if (timeout--) {
 138                         udelay(1);
 139                 } else {
 140                         dev_err(priv->dev, "IR_BUSY timeout\n");
 141                         return -ETIMEDOUT;
 142                 }
 143         }
 144
 145         /* Now only support raw mode, with symbol start from low to high */
 146         rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
 147         val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT;
 148         val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT;
 149         val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK
 150                << IR_CFG_INT_LEVEL_SHIFT;
 151         val |= IR_CFG_MODE_RAW;
 152         val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT;
 153         writel_relaxed(val, priv->base + IR_CONFIG);
 154
 155         writel_relaxed(0x00, priv->base + IR_INTM);
 156         /* write arbitrary value to start  */
 157         writel_relaxed(0x01, priv->base + IR_START);
 158         return 0;
 159 }
 160
 161 static int hix5hd2_ir_open(struct rc_dev *rdev)
 162 {
 163         struct hix5hd2_ir_priv *priv = rdev->priv;
 164         int ret;
 165
 166         ret = hix5hd2_ir_clk_enable(priv, true);
 167         if (ret)
 168                 return ret;
 169
 170         ret = hix5hd2_ir_config(priv);
 171         if (ret) {
 172                 hix5hd2_ir_clk_enable(priv, false);
 173                 return ret;
 174         }
 175         return 0;
 176 }
 177
 178 static void hix5hd2_ir_close(struct rc_dev *rdev)
 179 {
 180         struct hix5hd2_ir_priv *priv = rdev->priv;
 181
 182         hix5hd2_ir_clk_enable(priv, false);
 183 }
 184
 185 static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
 186 {
 187         u32 symb_num, symb_val, symb_time;
 188         u32 data_l, data_h;
 189         u32 irq_sr, i;
 190         struct hix5hd2_ir_priv *priv = data;
 191
 192         irq_sr = readl_relaxed(priv->base + IR_INTS);
 193         if (irq_sr & INTMS_OVERFLOW) {
 194                 /*
 195                  * we must read IR_DATAL first, then we can clean up
 196                  * IR_INTS availably since logic would not clear
 197                  * fifo when overflow, drv do the job
 198                  */
 199                 ir_raw_event_overflow(priv->rdev);
 200                 symb_num = readl_relaxed(priv->base + IR_DATAH);
 201                 for (i = 0; i < symb_num; i++)
 202                         readl_relaxed(priv->base + IR_DATAL);
 203
 204                 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
 205                 dev_info(priv->dev, "overflow, level=%d\n",
 206                          IR_CFG_INT_THRESHOLD);
 207         }
 208
 209         if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) {
 210                 struct ir_raw_event ev = {};
 211
 212                 symb_num = readl_relaxed(priv->base + IR_DATAH);
 213                 for (i = 0; i < symb_num; i++) {
 214                         symb_val = readl_relaxed(priv->base + IR_DATAL);
 215                         data_l = ((symb_val & 0xffff) * 10);
 216                         data_h =  ((symb_val >> 16) & 0xffff) * 10;
 217                         symb_time = (data_l + data_h) / 10;
 218
 219                         ev.duration = data_l;
 220                         ev.pulse = true;
 221                         ir_raw_event_store(priv->rdev, &ev);
 222
 223                         if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) {
 224                                 ev.duration = data_h;
 225                                 ev.pulse = false;
 226                                 ir_raw_event_store(priv->rdev, &ev);
 227                         } else {
 228                                 ir_raw_event_set_idle(priv->rdev, true);
 229                         }
 230                 }
 231
 232                 if (irq_sr & INTMS_SYMBRCV)
 233                         writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
 234                 if (irq_sr & INTMS_TIMEOUT)
 235                         writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
 236         }
 237
 238         /* Empty software fifo */
 239         ir_raw_event_handle(priv->rdev);
 240         return IRQ_HANDLED;
 241 }
 242
 243 static const struct of_device_id hix5hd2_ir_table[] = {
 244         { .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, },
 245         { .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, },
 246         {},
 247 };
 248 MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
 249
 250 static int hix5hd2_ir_probe(struct platform_device *pdev)
 251 {
 252         struct rc_dev *rdev;
 253         struct device *dev = &pdev->dev;
 254         struct hix5hd2_ir_priv *priv;
 255         struct device_node *node = pdev->dev.of_node;
 256         const char *map_name;
 257         int ret;
 258
 259         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 260         if (!priv)
 261                 return -ENOMEM;
 262
 263         priv->socdata = device_get_match_data(dev);
 264         if (!priv->socdata) {
 265                 dev_err(dev, "Unable to initialize IR data\n");
 266                 return -ENODEV;
 267         }
 268
 269         priv->regmap = syscon_regmap_lookup_by_phandle(node,
 270                                                        "hisilicon,power-syscon");
 271         if (IS_ERR(priv->regmap)) {
 272                 dev_info(dev, "no power-reg\n");
 273                 priv->regmap = NULL;
 274         }
 275
 276         priv->base = devm_platform_ioremap_resource(pdev, 0);
 277         if (IS_ERR(priv->base))
 278                 return PTR_ERR(priv->base);
 279
 280         priv->irq = platform_get_irq(pdev, 0);
 281         if (priv->irq < 0)
 282                 return priv->irq;
 283
 284         rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
 285         if (!rdev)
 286                 return -ENOMEM;
 287
 288         priv->clock = devm_clk_get(dev, NULL);
 289         if (IS_ERR(priv->clock)) {
 290                 dev_err(dev, "clock not found\n");
 291                 ret = PTR_ERR(priv->clock);
 292                 goto err;
 293         }
 294         ret = clk_prepare_enable(priv->clock);
 295         if (ret)
 296                 goto err;
 297         priv->rate = clk_get_rate(priv->clock);
 298
 299         rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
 300         rdev->priv = priv;
 301         rdev->open = hix5hd2_ir_open;
 302         rdev->close = hix5hd2_ir_close;
 303         rdev->driver_name = IR_HIX5HD2_NAME;
 304         map_name = of_get_property(node, "linux,rc-map-name", NULL);
 305         rdev->map_name = map_name ?: RC_MAP_EMPTY;
 306         rdev->device_name = IR_HIX5HD2_NAME;
 307         rdev->input_phys = IR_HIX5HD2_NAME "/input0";
 308         rdev->input_id.bustype = BUS_HOST;
 309         rdev->input_id.vendor = 0x0001;
 310         rdev->input_id.product = 0x0001;
 311         rdev->input_id.version = 0x0100;
 312         rdev->rx_resolution = 10;
 313         rdev->timeout = IR_CFG_SYMBOL_MAXWIDTH * 10;
 314
 315         ret = rc_register_device(rdev);
 316         if (ret < 0)
 317                 goto clkerr;
 318
 319         if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,
 320                              0, pdev->name, priv) < 0) {
 321                 dev_err(dev, "IRQ %d register failed\n", priv->irq);
 322                 ret = -EINVAL;
 323                 goto regerr;
 324         }
 325
 326         priv->rdev = rdev;
 327         priv->dev = dev;
 328         platform_set_drvdata(pdev, priv);
 329
 330         return ret;
 331
 332 regerr:
 333         rc_unregister_device(rdev);
 334         rdev = NULL;
 335 clkerr:
 336         clk_disable_unprepare(priv->clock);
 337 err:
 338         rc_free_device(rdev);
 339         dev_err(dev, "Unable to register device (%d)\n", ret);
 340         return ret;
 341 }
 342
 343 static void hix5hd2_ir_remove(struct platform_device *pdev)
 344 {
 345         struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);
 346
 347         clk_disable_unprepare(priv->clock);
 348         rc_unregister_device(priv->rdev);
 349 }
 350
 351 #ifdef CONFIG_PM_SLEEP
 352 static int hix5hd2_ir_suspend(struct device *dev)
 353 {
 354         struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
 355
 356         clk_disable_unprepare(priv->clock);
 357         hix5hd2_ir_clk_enable(priv, false);
 358
 359         return 0;
 360 }
 361
 362 static int hix5hd2_ir_resume(struct device *dev)
 363 {
 364         struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
 365         int ret;
 366
 367         ret = hix5hd2_ir_clk_enable(priv, true);
 368         if (ret)
 369                 return ret;
 370
 371         ret = clk_prepare_enable(priv->clock);
 372         if (ret) {
 373                 hix5hd2_ir_clk_enable(priv, false);
 374                 return ret;
 375         }
 376
 377         hix5hd2_ir_enable(priv);
 378
 379         writel_relaxed(0x00, priv->base + IR_INTM);
 380         writel_relaxed(0xff, priv->base + IR_INTC);
 381         writel_relaxed(0x01, priv->base + IR_START);
 382
 383         return 0;
 384 }
 385 #endif
 386
 387 static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
 388                          hix5hd2_ir_resume);
 389
 390 static struct platform_driver hix5hd2_ir_driver = {
 391         .driver = {
 392                 .name = IR_HIX5HD2_NAME,
 393                 .of_match_table = hix5hd2_ir_table,
 394                 .pm     = &hix5hd2_ir_pm_ops,
 395         },
 396         .probe = hix5hd2_ir_probe,
 397         .remove_new = hix5hd2_ir_remove,
 398 };
 399
 400 module_platform_driver(hix5hd2_ir_driver);
 401
 402 MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms");
 403 MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>");
 404 MODULE_LICENSE("GPL v2");
 405 MODULE_ALIAS("platform:hix5hd2-ir");