drivers/media/platform/verisilicon/rockchip_vpu_hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  *      Jeffy Chen <jeffy.chen@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10
  11 #include "hantro.h"
  12 #include "hantro_jpeg.h"
  13 #include "hantro_g1_regs.h"
  14 #include "hantro_h1_regs.h"
  15 #include "rockchip_vpu2_regs.h"
  16 #include "rockchip_vpu981_regs.h"
  17
  18 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
  19 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
  20 #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
  21
  22 #define ROCKCHIP_VPU981_MIN_SIZE 64
  23
  24 /*
  25  * Supported formats.
  26  */
  27
  28 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
  29         {
  30                 .fourcc = V4L2_PIX_FMT_YUV420M,
  31                 .codec_mode = HANTRO_MODE_NONE,
  32                 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
  33         },
  34         {
  35                 .fourcc = V4L2_PIX_FMT_NV12M,
  36                 .codec_mode = HANTRO_MODE_NONE,
  37                 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
  38         },
  39         {
  40                 .fourcc = V4L2_PIX_FMT_YUYV,
  41                 .codec_mode = HANTRO_MODE_NONE,
  42                 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
  43         },
  44         {
  45                 .fourcc = V4L2_PIX_FMT_UYVY,
  46                 .codec_mode = HANTRO_MODE_NONE,
  47                 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
  48         },
  49         {
  50                 .fourcc = V4L2_PIX_FMT_JPEG,
  51                 .codec_mode = HANTRO_MODE_JPEG_ENC,
  52                 .max_depth = 2,
  53                 .header_size = JPEG_HEADER_SIZE,
  54                 .frmsize = {
  55                         .min_width = 96,
  56                         .max_width = 8192,
  57                         .step_width = MB_DIM,
  58                         .min_height = 32,
  59                         .max_height = 8192,
  60                         .step_height = MB_DIM,
  61                 },
  62         },
  63 };
  64
  65 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
  66         {
  67                 .fourcc = V4L2_PIX_FMT_YUYV,
  68                 .codec_mode = HANTRO_MODE_NONE,
  69                 .postprocessed = true,
  70                 .frmsize = {
  71                         .min_width = FMT_MIN_WIDTH,
  72                         .max_width = FMT_FHD_WIDTH,
  73                         .step_width = MB_DIM,
  74                         .min_height = FMT_MIN_HEIGHT,
  75                         .max_height = FMT_FHD_HEIGHT,
  76                         .step_height = MB_DIM,
  77                 },
  78         },
  79 };
  80
  81 static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
  82         {
  83                 .fourcc = V4L2_PIX_FMT_NV12,
  84                 .codec_mode = HANTRO_MODE_NONE,
  85                 .match_depth = true,
  86                 .postprocessed = true,
  87                 .frmsize = {
  88                         .min_width = ROCKCHIP_VPU981_MIN_SIZE,
  89                         .max_width = FMT_UHD_WIDTH,
  90                         .step_width = MB_DIM,
  91                         .min_height = ROCKCHIP_VPU981_MIN_SIZE,
  92                         .max_height = FMT_UHD_HEIGHT,
  93                         .step_height = MB_DIM,
  94                 },
  95         },
  96         {
  97                 .fourcc = V4L2_PIX_FMT_P010,
  98                 .codec_mode = HANTRO_MODE_NONE,
  99                 .match_depth = true,
 100                 .postprocessed = true,
 101                 .frmsize = {
 102                         .min_width = ROCKCHIP_VPU981_MIN_SIZE,
 103                         .max_width = FMT_UHD_WIDTH,
 104                         .step_width = MB_DIM,
 105                         .min_height = ROCKCHIP_VPU981_MIN_SIZE,
 106                         .max_height = FMT_UHD_HEIGHT,
 107                         .step_height = MB_DIM,
 108                 },
 109         },
 110 };
 111
 112 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
 113         {
 114                 .fourcc = V4L2_PIX_FMT_NV12,
 115                 .codec_mode = HANTRO_MODE_NONE,
 116                 .frmsize = {
 117                         .min_width = FMT_MIN_WIDTH,
 118                         .max_width = FMT_FHD_WIDTH,
 119                         .step_width = MB_DIM,
 120                         .min_height = FMT_MIN_HEIGHT,
 121                         .max_height = FMT_FHD_HEIGHT,
 122                         .step_height = MB_DIM,
 123                 },
 124         },
 125         {
 126                 .fourcc = V4L2_PIX_FMT_H264_SLICE,
 127                 .codec_mode = HANTRO_MODE_H264_DEC,
 128                 .max_depth = 2,
 129                 .frmsize = {
 130                         .min_width = FMT_MIN_WIDTH,
 131                         .max_width = FMT_FHD_WIDTH,
 132                         .step_width = MB_DIM,
 133                         .min_height = FMT_MIN_HEIGHT,
 134                         .max_height = FMT_FHD_HEIGHT,
 135                         .step_height = MB_DIM,
 136                 },
 137         },
 138         {
 139                 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
 140                 .codec_mode = HANTRO_MODE_MPEG2_DEC,
 141                 .max_depth = 2,
 142                 .frmsize = {
 143                         .min_width = FMT_MIN_WIDTH,
 144                         .max_width = FMT_FHD_WIDTH,
 145                         .step_width = MB_DIM,
 146                         .min_height = FMT_MIN_HEIGHT,
 147                         .max_height = FMT_FHD_HEIGHT,
 148                         .step_height = MB_DIM,
 149                 },
 150         },
 151         {
 152                 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
 153                 .codec_mode = HANTRO_MODE_VP8_DEC,
 154                 .max_depth = 2,
 155                 .frmsize = {
 156                         .min_width = FMT_MIN_WIDTH,
 157                         .max_width = FMT_FHD_WIDTH,
 158                         .step_width = MB_DIM,
 159                         .min_height = FMT_MIN_HEIGHT,
 160                         .max_height = FMT_FHD_HEIGHT,
 161                         .step_height = MB_DIM,
 162                 },
 163         },
 164 };
 165
 166 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
 167         {
 168                 .fourcc = V4L2_PIX_FMT_NV12,
 169                 .codec_mode = HANTRO_MODE_NONE,
 170                 .frmsize = {
 171                         .min_width = FMT_MIN_WIDTH,
 172                         .max_width = FMT_4K_WIDTH,
 173                         .step_width = MB_DIM,
 174                         .min_height = FMT_MIN_HEIGHT,
 175                         .max_height = FMT_4K_HEIGHT,
 176                         .step_height = MB_DIM,
 177                 },
 178         },
 179         {
 180                 .fourcc = V4L2_PIX_FMT_H264_SLICE,
 181                 .codec_mode = HANTRO_MODE_H264_DEC,
 182                 .max_depth = 2,
 183                 .frmsize = {
 184                         .min_width = FMT_MIN_WIDTH,
 185                         .max_width = FMT_4K_WIDTH,
 186                         .step_width = MB_DIM,
 187                         .min_height = FMT_MIN_HEIGHT,
 188                         .max_height = FMT_4K_HEIGHT,
 189                         .step_height = MB_DIM,
 190                 },
 191         },
 192         {
 193                 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
 194                 .codec_mode = HANTRO_MODE_MPEG2_DEC,
 195                 .max_depth = 2,
 196                 .frmsize = {
 197                         .min_width = FMT_MIN_WIDTH,
 198                         .max_width = FMT_FHD_WIDTH,
 199                         .step_width = MB_DIM,
 200                         .min_height = FMT_MIN_HEIGHT,
 201                         .max_height = FMT_FHD_HEIGHT,
 202                         .step_height = MB_DIM,
 203                 },
 204         },
 205         {
 206                 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
 207                 .codec_mode = HANTRO_MODE_VP8_DEC,
 208                 .max_depth = 2,
 209                 .frmsize = {
 210                         .min_width = FMT_MIN_WIDTH,
 211                         .max_width = FMT_UHD_WIDTH,
 212                         .step_width = MB_DIM,
 213                         .min_height = FMT_MIN_HEIGHT,
 214                         .max_height = FMT_UHD_HEIGHT,
 215                         .step_height = MB_DIM,
 216                 },
 217         },
 218 };
 219
 220 static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
 221         {
 222                 .fourcc = V4L2_PIX_FMT_NV12,
 223                 .codec_mode = HANTRO_MODE_NONE,
 224                 .frmsize = {
 225                         .min_width = FMT_MIN_WIDTH,
 226                         .max_width = FMT_FHD_WIDTH,
 227                         .step_width = MB_DIM,
 228                         .min_height = FMT_MIN_HEIGHT,
 229                         .max_height = FMT_FHD_HEIGHT,
 230                         .step_height = MB_DIM,
 231                 },
 232         },
 233         {
 234                 .fourcc = V4L2_PIX_FMT_H264_SLICE,
 235                 .codec_mode = HANTRO_MODE_H264_DEC,
 236                 .max_depth = 2,
 237                 .frmsize = {
 238                         .min_width = FMT_MIN_WIDTH,
 239                         .max_width = FMT_FHD_WIDTH,
 240                         .step_width = MB_DIM,
 241                         .min_height = FMT_MIN_HEIGHT,
 242                         .max_height = FMT_FHD_HEIGHT,
 243                         .step_height = MB_DIM,
 244                 },
 245         },
 246         {
 247                 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
 248                 .codec_mode = HANTRO_MODE_MPEG2_DEC,
 249                 .max_depth = 2,
 250                 .frmsize = {
 251                         .min_width = FMT_MIN_WIDTH,
 252                         .max_width = FMT_FHD_WIDTH,
 253                         .step_width = MB_DIM,
 254                         .min_height = FMT_MIN_HEIGHT,
 255                         .max_height = FMT_FHD_HEIGHT,
 256                         .step_height = MB_DIM,
 257                 },
 258         },
 259         {
 260                 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
 261                 .codec_mode = HANTRO_MODE_VP8_DEC,
 262                 .max_depth = 2,
 263                 .frmsize = {
 264                         .min_width = FMT_MIN_WIDTH,
 265                         .max_width = FMT_UHD_WIDTH,
 266                         .step_width = MB_DIM,
 267                         .min_height = FMT_MIN_HEIGHT,
 268                         .max_height = FMT_UHD_HEIGHT,
 269                         .step_height = MB_DIM,
 270                 },
 271         },
 272 };
 273
 274 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
 275         {
 276                 .fourcc = V4L2_PIX_FMT_NV12,
 277                 .codec_mode = HANTRO_MODE_NONE,
 278                 .frmsize = {
 279                         .min_width = FMT_MIN_WIDTH,
 280                         .max_width = FMT_FHD_WIDTH,
 281                         .step_width = MB_DIM,
 282                         .min_height = FMT_MIN_HEIGHT,
 283                         .max_height = FMT_FHD_HEIGHT,
 284                         .step_height = MB_DIM,
 285                 },
 286         },
 287         {
 288                 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
 289                 .codec_mode = HANTRO_MODE_MPEG2_DEC,
 290                 .max_depth = 2,
 291                 .frmsize = {
 292                         .min_width = FMT_MIN_WIDTH,
 293                         .max_width = FMT_FHD_WIDTH,
 294                         .step_width = MB_DIM,
 295                         .min_height = FMT_MIN_HEIGHT,
 296                         .max_height = FMT_FHD_HEIGHT,
 297                         .step_height = MB_DIM,
 298                 },
 299         },
 300         {
 301                 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
 302                 .codec_mode = HANTRO_MODE_VP8_DEC,
 303                 .max_depth = 2,
 304                 .frmsize = {
 305                         .min_width = FMT_MIN_WIDTH,
 306                         .max_width = FMT_UHD_WIDTH,
 307                         .step_width = MB_DIM,
 308                         .min_height = FMT_MIN_HEIGHT,
 309                         .max_height = FMT_UHD_HEIGHT,
 310                         .step_height = MB_DIM,
 311                 },
 312         },
 313 };
 314
 315 static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = {
 316         {
 317                 .fourcc = V4L2_PIX_FMT_NV12_4L4,
 318                 .codec_mode = HANTRO_MODE_NONE,
 319                 .match_depth = true,
 320                 .frmsize = {
 321                         .min_width = ROCKCHIP_VPU981_MIN_SIZE,
 322                         .max_width = FMT_UHD_WIDTH,
 323                         .step_width = MB_DIM,
 324                         .min_height = ROCKCHIP_VPU981_MIN_SIZE,
 325                         .max_height = FMT_UHD_HEIGHT,
 326                         .step_height = MB_DIM,
 327                 },
 328         },
 329         {
 330                 .fourcc = V4L2_PIX_FMT_NV15_4L4,
 331                 .codec_mode = HANTRO_MODE_NONE,
 332                 .match_depth = true,
 333                 .frmsize = {
 334                         .min_width = ROCKCHIP_VPU981_MIN_SIZE,
 335                         .max_width = FMT_UHD_WIDTH,
 336                         .step_width = MB_DIM,
 337                         .min_height = ROCKCHIP_VPU981_MIN_SIZE,
 338                         .max_height = FMT_UHD_HEIGHT,
 339                         .step_height = MB_DIM,
 340                 },
 341         },
 342         {
 343                 .fourcc = V4L2_PIX_FMT_AV1_FRAME,
 344                 .codec_mode = HANTRO_MODE_AV1_DEC,
 345                 .max_depth = 2,
 346                 .frmsize = {
 347                         .min_width = ROCKCHIP_VPU981_MIN_SIZE,
 348                         .max_width = FMT_UHD_WIDTH,
 349                         .step_width = MB_DIM,
 350                         .min_height = ROCKCHIP_VPU981_MIN_SIZE,
 351                         .max_height = FMT_UHD_HEIGHT,
 352                         .step_height = MB_DIM,
 353                 },
 354         },
 355 };
 356
 357 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
 358 {
 359         struct hantro_dev *vpu = dev_id;
 360         enum vb2_buffer_state state;
 361         u32 status;
 362
 363         status = vepu_read(vpu, H1_REG_INTERRUPT);
 364         state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
 365                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
 366
 367         vepu_write(vpu, 0, H1_REG_INTERRUPT);
 368         vepu_write(vpu, 0, H1_REG_AXI_CTRL);
 369
 370         hantro_irq_done(vpu, state);
 371
 372         return IRQ_HANDLED;
 373 }
 374
 375 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
 376 {
 377         struct hantro_dev *vpu = dev_id;
 378         enum vb2_buffer_state state;
 379         u32 status;
 380
 381         status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
 382         state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
 383                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
 384
 385         vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
 386         vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
 387
 388         hantro_irq_done(vpu, state);
 389
 390         return IRQ_HANDLED;
 391 }
 392
 393 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
 394 {
 395         struct hantro_dev *vpu = dev_id;
 396         enum vb2_buffer_state state;
 397         u32 status;
 398
 399         status = vepu_read(vpu, VEPU_REG_INTERRUPT);
 400         state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
 401                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
 402
 403         vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
 404         vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
 405
 406         hantro_irq_done(vpu, state);
 407
 408         return IRQ_HANDLED;
 409 }
 410
 411 static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id)
 412 {
 413         struct hantro_dev *vpu = dev_id;
 414         enum vb2_buffer_state state;
 415         u32 status;
 416
 417         status = vdpu_read(vpu, AV1_REG_INTERRUPT);
 418         state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ?
 419                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
 420
 421         vdpu_write(vpu, 0, AV1_REG_INTERRUPT);
 422         vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);
 423
 424         hantro_irq_done(vpu, state);
 425
 426         return IRQ_HANDLED;
 427 }
 428
 429 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
 430 {
 431         /* Bump ACLK to max. possible freq. to improve performance. */
 432         clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
 433         return 0;
 434 }
 435
 436 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
 437 {
 438         /* Bump ACLKs to max. possible freq. to improve performance. */
 439         clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
 440         clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
 441         return 0;
 442 }
 443
 444 static int rk3588_vpu981_hw_init(struct hantro_dev *vpu)
 445 {
 446         /* Bump ACLKs to max. possible freq. to improve performance. */
 447         clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);
 448         return 0;
 449 }
 450
 451 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
 452 {
 453         /* Bump ACLK to max. possible freq. to improve performance. */
 454         clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
 455         return 0;
 456 }
 457
 458 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
 459 {
 460         struct hantro_dev *vpu = ctx->dev;
 461
 462         vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
 463         vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
 464 }
 465
 466 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
 467 {
 468         struct hantro_dev *vpu = ctx->dev;
 469
 470         vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
 471         vepu_write(vpu, 0, H1_REG_ENC_CTRL);
 472         vepu_write(vpu, 0, H1_REG_AXI_CTRL);
 473 }
 474
 475 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
 476 {
 477         struct hantro_dev *vpu = ctx->dev;
 478
 479         vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
 480         vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
 481         vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
 482 }
 483
 484 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
 485 {
 486         struct hantro_dev *vpu = ctx->dev;
 487
 488         vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
 489         vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
 490         vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
 491 }
 492
 493 /*
 494  * Supported codec ops.
 495  */
 496 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
 497         [HANTRO_MODE_H264_DEC] = {
 498                 .run = hantro_g1_h264_dec_run,
 499                 .reset = hantro_g1_reset,
 500                 .init = hantro_h264_dec_init,
 501                 .exit = hantro_h264_dec_exit,
 502         },
 503         [HANTRO_MODE_MPEG2_DEC] = {
 504                 .run = hantro_g1_mpeg2_dec_run,
 505                 .reset = hantro_g1_reset,
 506                 .init = hantro_mpeg2_dec_init,
 507                 .exit = hantro_mpeg2_dec_exit,
 508         },
 509         [HANTRO_MODE_VP8_DEC] = {
 510                 .run = hantro_g1_vp8_dec_run,
 511                 .reset = hantro_g1_reset,
 512                 .init = hantro_vp8_dec_init,
 513                 .exit = hantro_vp8_dec_exit,
 514         },
 515 };
 516
 517 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
 518         [HANTRO_MODE_JPEG_ENC] = {
 519                 .run = hantro_h1_jpeg_enc_run,
 520                 .reset = rockchip_vpu1_enc_reset,
 521                 .done = hantro_h1_jpeg_enc_done,
 522         },
 523         [HANTRO_MODE_H264_DEC] = {
 524                 .run = hantro_g1_h264_dec_run,
 525                 .reset = rk3066_vpu_dec_reset,
 526                 .init = hantro_h264_dec_init,
 527                 .exit = hantro_h264_dec_exit,
 528         },
 529         [HANTRO_MODE_MPEG2_DEC] = {
 530                 .run = hantro_g1_mpeg2_dec_run,
 531                 .reset = rk3066_vpu_dec_reset,
 532                 .init = hantro_mpeg2_dec_init,
 533                 .exit = hantro_mpeg2_dec_exit,
 534         },
 535         [HANTRO_MODE_VP8_DEC] = {
 536                 .run = hantro_g1_vp8_dec_run,
 537                 .reset = rk3066_vpu_dec_reset,
 538                 .init = hantro_vp8_dec_init,
 539                 .exit = hantro_vp8_dec_exit,
 540         },
 541 };
 542
 543 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
 544         [HANTRO_MODE_JPEG_ENC] = {
 545                 .run = hantro_h1_jpeg_enc_run,
 546                 .reset = rockchip_vpu1_enc_reset,
 547                 .done = hantro_h1_jpeg_enc_done,
 548         },
 549         [HANTRO_MODE_H264_DEC] = {
 550                 .run = hantro_g1_h264_dec_run,
 551                 .reset = hantro_g1_reset,
 552                 .init = hantro_h264_dec_init,
 553                 .exit = hantro_h264_dec_exit,
 554         },
 555         [HANTRO_MODE_MPEG2_DEC] = {
 556                 .run = hantro_g1_mpeg2_dec_run,
 557                 .reset = hantro_g1_reset,
 558                 .init = hantro_mpeg2_dec_init,
 559                 .exit = hantro_mpeg2_dec_exit,
 560         },
 561         [HANTRO_MODE_VP8_DEC] = {
 562                 .run = hantro_g1_vp8_dec_run,
 563                 .reset = hantro_g1_reset,
 564                 .init = hantro_vp8_dec_init,
 565                 .exit = hantro_vp8_dec_exit,
 566         },
 567 };
 568
 569 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
 570         [HANTRO_MODE_JPEG_ENC] = {
 571                 .run = rockchip_vpu2_jpeg_enc_run,
 572                 .reset = rockchip_vpu2_enc_reset,
 573                 .done = rockchip_vpu2_jpeg_enc_done,
 574         },
 575         [HANTRO_MODE_H264_DEC] = {
 576                 .run = rockchip_vpu2_h264_dec_run,
 577                 .reset = rockchip_vpu2_dec_reset,
 578                 .init = hantro_h264_dec_init,
 579                 .exit = hantro_h264_dec_exit,
 580         },
 581         [HANTRO_MODE_MPEG2_DEC] = {
 582                 .run = rockchip_vpu2_mpeg2_dec_run,
 583                 .reset = rockchip_vpu2_dec_reset,
 584                 .init = hantro_mpeg2_dec_init,
 585                 .exit = hantro_mpeg2_dec_exit,
 586         },
 587         [HANTRO_MODE_VP8_DEC] = {
 588                 .run = rockchip_vpu2_vp8_dec_run,
 589                 .reset = rockchip_vpu2_dec_reset,
 590                 .init = hantro_vp8_dec_init,
 591                 .exit = hantro_vp8_dec_exit,
 592         },
 593 };
 594
 595 static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
 596         [HANTRO_MODE_JPEG_ENC] = {
 597                 .run = rockchip_vpu2_jpeg_enc_run,
 598                 .reset = rockchip_vpu2_enc_reset,
 599                 .done = rockchip_vpu2_jpeg_enc_done,
 600         },
 601 };
 602
 603 static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = {
 604         [HANTRO_MODE_AV1_DEC] = {
 605                 .run = rockchip_vpu981_av1_dec_run,
 606                 .init = rockchip_vpu981_av1_dec_init,
 607                 .exit = rockchip_vpu981_av1_dec_exit,
 608                 .done = rockchip_vpu981_av1_dec_done,
 609         },
 610 };
 611 /*
 612  * VPU variant.
 613  */
 614
 615 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
 616         { "vdpu", hantro_g1_irq },
 617 };
 618
 619 static const struct hantro_irq rockchip_vpu1_irqs[] = {
 620         { "vepu", rockchip_vpu1_vepu_irq },
 621         { "vdpu", hantro_g1_irq },
 622 };
 623
 624 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
 625         { "vdpu", rockchip_vpu2_vdpu_irq },
 626 };
 627
 628 static const struct hantro_irq rockchip_vpu2_irqs[] = {
 629         { "vepu", rockchip_vpu2_vepu_irq },
 630         { "vdpu", rockchip_vpu2_vdpu_irq },
 631 };
 632
 633 static const struct hantro_irq rk3568_vepu_irqs[] = {
 634         { "vepu", rockchip_vpu2_vepu_irq },
 635 };
 636
 637 static const char * const rk3066_vpu_clk_names[] = {
 638         "aclk_vdpu", "hclk_vdpu",
 639         "aclk_vepu", "hclk_vepu"
 640 };
 641
 642 static const struct hantro_irq rk3588_vpu981_irqs[] = {
 643         { "vdpu", rk3588_vpu981_irq },
 644 };
 645
 646 static const char * const rockchip_vpu_clk_names[] = {
 647         "aclk", "hclk"
 648 };
 649
 650 static const char * const rk3588_vpu981_vpu_clk_names[] = {
 651         "aclk", "hclk",
 652 };
 653
 654 /* VDPU1/VEPU1 */
 655
 656 const struct hantro_variant rk3036_vpu_variant = {
 657         .dec_offset = 0x400,
 658         .dec_fmts = rk3066_vpu_dec_fmts,
 659         .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
 660         .postproc_fmts = rockchip_vpu1_postproc_fmts,
 661         .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
 662         .postproc_ops = &hantro_g1_postproc_ops,
 663         .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
 664                  HANTRO_H264_DECODER,
 665         .codec_ops = rk3036_vpu_codec_ops,
 666         .irqs = rockchip_vdpu1_irqs,
 667         .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
 668         .init = rk3036_vpu_hw_init,
 669         .clk_names = rockchip_vpu_clk_names,
 670         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
 671 };
 672
 673 /*
 674  * Despite this variant has separate clocks for decoder and encoder,
 675  * it's still required to enable all four of them for either decoding
 676  * or encoding and we can't split it in separate g1/h1 variants.
 677  */
 678 const struct hantro_variant rk3066_vpu_variant = {
 679         .enc_offset = 0x0,
 680         .enc_fmts = rockchip_vpu_enc_fmts,
 681         .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
 682         .dec_offset = 0x400,
 683         .dec_fmts = rk3066_vpu_dec_fmts,
 684         .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
 685         .postproc_fmts = rockchip_vpu1_postproc_fmts,
 686         .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
 687         .postproc_ops = &hantro_g1_postproc_ops,
 688         .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
 689                  HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
 690         .codec_ops = rk3066_vpu_codec_ops,
 691         .irqs = rockchip_vpu1_irqs,
 692         .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
 693         .init = rk3066_vpu_hw_init,
 694         .clk_names = rk3066_vpu_clk_names,
 695         .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
 696 };
 697
 698 const struct hantro_variant rk3288_vpu_variant = {
 699         .enc_offset = 0x0,
 700         .enc_fmts = rockchip_vpu_enc_fmts,
 701         .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
 702         .dec_offset = 0x400,
 703         .dec_fmts = rk3288_vpu_dec_fmts,
 704         .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
 705         .postproc_fmts = rockchip_vpu1_postproc_fmts,
 706         .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
 707         .postproc_ops = &hantro_g1_postproc_ops,
 708         .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
 709                  HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
 710         .codec_ops = rk3288_vpu_codec_ops,
 711         .irqs = rockchip_vpu1_irqs,
 712         .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
 713         .init = rockchip_vpu_hw_init,
 714         .clk_names = rockchip_vpu_clk_names,
 715         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
 716 };
 717
 718 /* VDPU2/VEPU2 */
 719
 720 const struct hantro_variant rk3328_vpu_variant = {
 721         .dec_offset = 0x400,
 722         .dec_fmts = rockchip_vdpu2_dec_fmts,
 723         .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
 724         .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
 725                  HANTRO_H264_DECODER,
 726         .codec_ops = rk3399_vpu_codec_ops,
 727         .irqs = rockchip_vdpu2_irqs,
 728         .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
 729         .init = rockchip_vpu_hw_init,
 730         .clk_names = rockchip_vpu_clk_names,
 731         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
 732 };
 733
 734 /*
 735  * H.264 decoding explicitly disabled in RK3399.
 736  * This ensures userspace applications use the Rockchip VDEC core,
 737  * which has better performance.
 738  */
 739 const struct hantro_variant rk3399_vpu_variant = {
 740         .enc_offset = 0x0,
 741         .enc_fmts = rockchip_vpu_enc_fmts,
 742         .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
 743         .dec_offset = 0x400,
 744         .dec_fmts = rk3399_vpu_dec_fmts,
 745         .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
 746         .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
 747                  HANTRO_VP8_DECODER,
 748         .codec_ops = rk3399_vpu_codec_ops,
 749         .irqs = rockchip_vpu2_irqs,
 750         .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
 751         .init = rockchip_vpu_hw_init,
 752         .clk_names = rockchip_vpu_clk_names,
 753         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
 754 };
 755
 756 const struct hantro_variant rk3568_vepu_variant = {
 757         .enc_offset = 0x0,
 758         .enc_fmts = rockchip_vpu_enc_fmts,
 759         .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
 760         .codec = HANTRO_JPEG_ENCODER,
 761         .codec_ops = rk3568_vepu_codec_ops,
 762         .irqs = rk3568_vepu_irqs,
 763         .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
 764         .init = rockchip_vpu_hw_init,
 765         .clk_names = rockchip_vpu_clk_names,
 766         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
 767 };
 768
 769 const struct hantro_variant rk3568_vpu_variant = {
 770         .dec_offset = 0x400,
 771         .dec_fmts = rockchip_vdpu2_dec_fmts,
 772         .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
 773         .codec = HANTRO_MPEG2_DECODER |
 774                  HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
 775         .codec_ops = rk3399_vpu_codec_ops,
 776         .irqs = rockchip_vdpu2_irqs,
 777         .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
 778         .init = rockchip_vpu_hw_init,
 779         .clk_names = rockchip_vpu_clk_names,
 780         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
 781 };
 782
 783 const struct hantro_variant px30_vpu_variant = {
 784         .enc_offset = 0x0,
 785         .enc_fmts = rockchip_vpu_enc_fmts,
 786         .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
 787         .dec_offset = 0x400,
 788         .dec_fmts = rockchip_vdpu2_dec_fmts,
 789         .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
 790         .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
 791                  HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
 792         .codec_ops = rk3399_vpu_codec_ops,
 793         .irqs = rockchip_vpu2_irqs,
 794         .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
 795         .init = rk3036_vpu_hw_init,
 796         .clk_names = rockchip_vpu_clk_names,
 797         .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
 798 };
 799
 800 const struct hantro_variant rk3588_vpu981_variant = {
 801         .dec_offset = 0x0,
 802         .dec_fmts = rockchip_vpu981_dec_fmts,
 803         .num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts),
 804         .postproc_fmts = rockchip_vpu981_postproc_fmts,
 805         .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts),
 806         .postproc_ops = &rockchip_vpu981_postproc_ops,
 807         .codec = HANTRO_AV1_DECODER,
 808         .codec_ops = rk3588_vpu981_codec_ops,
 809         .irqs = rk3588_vpu981_irqs,
 810         .num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
 811         .init = rk3588_vpu981_hw_init,
 812         .clk_names = rk3588_vpu981_vpu_clk_names,
 813         .num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
 814 };