1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
5 * Copyright (c) 2013 Texas Instruments Inc.
6 * David Griego, <dagriego@biglakesoftware.com>
7 * Dale Farnsworth, <dale@farnsworth.org>
8 * Archit Taneja, <archit@ti.com>
10 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
11 * Pawel Osciak, <pawel@osciak.com>
12 * Marek Szyprowski, <m.szyprowski@samsung.com>
14 * Based on the virtual v4l2-mem2mem example device
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
21 #include <linux/interrupt.h>
23 #include <linux/ioctl.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/videodev2.h>
31 #include <linux/log2.h>
32 #include <linux/sizes.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-device.h>
37 #include <media/v4l2-event.h>
38 #include <media/v4l2-ioctl.h>
39 #include <media/v4l2-mem2mem.h>
40 #include <media/videobuf2-v4l2.h>
41 #include <media/videobuf2-dma-contig.h>
44 #include "vpdma_priv.h"
49 #define VPE_MODULE_NAME "vpe"
51 /* minimum and maximum frame sizes */
57 /* required alignments */
58 #define S_ALIGN 0 /* multiple of 1 */
59 #define H_ALIGN 1 /* multiple of 2 */
61 /* flags that indicate a format can be used for capture/output */
62 #define VPE_FMT_TYPE_CAPTURE (1 << 0)
63 #define VPE_FMT_TYPE_OUTPUT (1 << 1)
65 /* used as plane indices */
66 #define VPE_MAX_PLANES 2
70 /* per m2m context info */
71 #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
73 #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
76 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
77 * 3 output descriptors, and 10 control descriptors
79 #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
80 13 * VPDMA_CFD_CTD_DESC_SIZE)
82 #define vpe_dbg(vpedev, fmt, arg...) \
83 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
84 #define vpe_err(vpedev, fmt, arg...) \
85 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
87 struct vpe_us_coeffs {
88 unsigned short anchor_fid0_c0;
89 unsigned short anchor_fid0_c1;
90 unsigned short anchor_fid0_c2;
91 unsigned short anchor_fid0_c3;
92 unsigned short interp_fid0_c0;
93 unsigned short interp_fid0_c1;
94 unsigned short interp_fid0_c2;
95 unsigned short interp_fid0_c3;
96 unsigned short anchor_fid1_c0;
97 unsigned short anchor_fid1_c1;
98 unsigned short anchor_fid1_c2;
99 unsigned short anchor_fid1_c3;
100 unsigned short interp_fid1_c0;
101 unsigned short interp_fid1_c1;
102 unsigned short interp_fid1_c2;
103 unsigned short interp_fid1_c3;
107 * Default upsampler coefficients
109 static const struct vpe_us_coeffs us_coeffs[] = {
111 /* Coefficients for progressive input */
112 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
113 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
116 /* Coefficients for Top Field Interlaced input */
117 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
118 /* Coefficients for Bottom Field Interlaced input */
119 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
124 * the following registers are for configuring some of the parameters of the
125 * motion and edge detection blocks inside DEI, these generally remain the same,
126 * these could be passed later via userspace if some one needs to tweak these.
128 struct vpe_dei_regs {
129 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
130 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
131 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
132 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
133 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
134 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
138 * default expert DEI register values, unlikely to be modified.
140 static const struct vpe_dei_regs dei_regs = {
141 .mdt_spacial_freq_thr_reg = 0x020C0804u,
142 .edi_config_reg = 0x0118100Cu,
143 .edi_lut_reg0 = 0x08040200u,
144 .edi_lut_reg1 = 0x1010100Cu,
145 .edi_lut_reg2 = 0x10101010u,
146 .edi_lut_reg3 = 0x10101010u,
150 * The port_data structure contains per-port data.
152 struct vpe_port_data {
153 enum vpdma_channel channel; /* VPDMA channel */
154 u8 vb_index; /* input frame f, f-1, f-2 index */
155 u8 vb_part; /* plane index for co-panar formats */
159 * Define indices into the port_data tables
161 #define VPE_PORT_LUMA1_IN 0
162 #define VPE_PORT_CHROMA1_IN 1
163 #define VPE_PORT_LUMA2_IN 2
164 #define VPE_PORT_CHROMA2_IN 3
165 #define VPE_PORT_LUMA3_IN 4
166 #define VPE_PORT_CHROMA3_IN 5
167 #define VPE_PORT_MV_IN 6
168 #define VPE_PORT_MV_OUT 7
169 #define VPE_PORT_LUMA_OUT 8
170 #define VPE_PORT_CHROMA_OUT 9
171 #define VPE_PORT_RGB_OUT 10
173 static const struct vpe_port_data port_data[11] = {
174 [VPE_PORT_LUMA1_IN] = {
175 .channel = VPE_CHAN_LUMA1_IN,
179 [VPE_PORT_CHROMA1_IN] = {
180 .channel = VPE_CHAN_CHROMA1_IN,
182 .vb_part = VPE_CHROMA,
184 [VPE_PORT_LUMA2_IN] = {
185 .channel = VPE_CHAN_LUMA2_IN,
189 [VPE_PORT_CHROMA2_IN] = {
190 .channel = VPE_CHAN_CHROMA2_IN,
192 .vb_part = VPE_CHROMA,
194 [VPE_PORT_LUMA3_IN] = {
195 .channel = VPE_CHAN_LUMA3_IN,
199 [VPE_PORT_CHROMA3_IN] = {
200 .channel = VPE_CHAN_CHROMA3_IN,
202 .vb_part = VPE_CHROMA,
205 .channel = VPE_CHAN_MV_IN,
207 [VPE_PORT_MV_OUT] = {
208 .channel = VPE_CHAN_MV_OUT,
210 [VPE_PORT_LUMA_OUT] = {
211 .channel = VPE_CHAN_LUMA_OUT,
214 [VPE_PORT_CHROMA_OUT] = {
215 .channel = VPE_CHAN_CHROMA_OUT,
216 .vb_part = VPE_CHROMA,
218 [VPE_PORT_RGB_OUT] = {
219 .channel = VPE_CHAN_RGB_OUT,
225 /* driver info for each of the supported video formats */
227 u32 fourcc; /* standard format identifier */
228 u8 types; /* CAPTURE and/or OUTPUT */
229 u8 coplanar; /* set for unpacked Luma and Chroma */
230 /* vpdma format info for each plane */
231 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
234 static struct vpe_fmt vpe_formats[] = {
236 .fourcc = V4L2_PIX_FMT_NV16,
237 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
239 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
240 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
244 .fourcc = V4L2_PIX_FMT_NV12,
245 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
247 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
248 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
252 .fourcc = V4L2_PIX_FMT_NV21,
253 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
255 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
256 &vpdma_yuv_fmts[VPDMA_DATA_FMT_CB420],
260 .fourcc = V4L2_PIX_FMT_YUYV,
261 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
263 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
267 .fourcc = V4L2_PIX_FMT_UYVY,
268 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
270 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
274 .fourcc = V4L2_PIX_FMT_RGB24,
275 .types = VPE_FMT_TYPE_CAPTURE,
277 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
281 .fourcc = V4L2_PIX_FMT_RGB32,
282 .types = VPE_FMT_TYPE_CAPTURE,
284 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
288 .fourcc = V4L2_PIX_FMT_BGR24,
289 .types = VPE_FMT_TYPE_CAPTURE,
291 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
295 .fourcc = V4L2_PIX_FMT_BGR32,
296 .types = VPE_FMT_TYPE_CAPTURE,
298 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
302 .fourcc = V4L2_PIX_FMT_RGB565,
303 .types = VPE_FMT_TYPE_CAPTURE,
305 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
309 .fourcc = V4L2_PIX_FMT_RGB555,
310 .types = VPE_FMT_TYPE_CAPTURE,
312 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
318 * per-queue, driver-specific private data.
319 * there is one source queue and one destination queue for each m2m context.
322 /* current v4l2 format info */
323 struct v4l2_format format;
325 struct v4l2_rect c_rect; /* crop/compose rectangle */
326 struct vpe_fmt *fmt; /* format info */
329 /* vpe_q_data flag bits */
330 #define Q_DATA_FRAME_1D BIT(0)
331 #define Q_DATA_MODE_TILED BIT(1)
332 #define Q_DATA_INTERLACED_ALTERNATE BIT(2)
333 #define Q_DATA_INTERLACED_SEQ_TB BIT(3)
334 #define Q_DATA_INTERLACED_SEQ_BT BIT(4)
336 #define Q_IS_SEQ_XX (Q_DATA_INTERLACED_SEQ_TB | \
337 Q_DATA_INTERLACED_SEQ_BT)
339 #define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \
340 Q_DATA_INTERLACED_SEQ_TB | \
341 Q_DATA_INTERLACED_SEQ_BT)
348 /* find our format description corresponding to the passed v4l2_format */
349 static struct vpe_fmt *__find_format(u32 fourcc)
354 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
355 fmt = &vpe_formats[k];
356 if (fmt->fourcc == fourcc)
363 static struct vpe_fmt *find_format(struct v4l2_format *f)
365 return __find_format(f->fmt.pix.pixelformat);
369 * there is one vpe_dev structure in the driver, it is shared by
373 struct v4l2_device v4l2_dev;
374 struct video_device vfd;
375 struct v4l2_m2m_dev *m2m_dev;
377 atomic_t num_instances; /* count of driver instances */
378 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
379 struct mutex dev_mutex;
384 struct resource *res;
386 struct vpdma_data vpdma_data;
387 struct vpdma_data *vpdma; /* vpdma data handle */
388 struct sc_data *sc; /* scaler data handle */
389 struct csc_data *csc; /* csc data handle */
393 * There is one vpe_ctx structure for each m2m context.
398 struct v4l2_ctrl_handler hdl;
400 unsigned int field; /* current field */
401 unsigned int sequence; /* current frame/field seq */
402 unsigned int aborting; /* abort after next irq */
404 unsigned int bufs_per_job; /* input buffers per batch */
405 unsigned int bufs_completed; /* bufs done in this batch */
407 struct vpe_q_data q_data[2]; /* src & dst queue data */
408 struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
409 struct vb2_v4l2_buffer *dst_vb;
411 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
412 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
413 size_t mv_buf_size; /* current motion vector buffer size */
414 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
415 struct vpdma_buf sc_coeff_h; /* h coeff buffer */
416 struct vpdma_buf sc_coeff_v; /* v coeff buffer */
417 struct vpdma_desc_list desc_list; /* DMA descriptor list */
419 bool deinterlacing; /* using de-interlacer */
420 bool load_mmrs; /* have new shadow reg values */
422 unsigned int src_mv_buf_selector;
427 * M2M devices get 2 queues.
428 * Return the queue given the type.
430 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
431 enum v4l2_buf_type type)
434 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
435 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
436 return &ctx->q_data[Q_DATA_SRC];
437 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
438 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
439 return &ctx->q_data[Q_DATA_DST];
446 static u32 read_reg(struct vpe_dev *dev, int offset)
448 return ioread32(dev->base + offset);
451 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
453 iowrite32(value, dev->base + offset);
456 /* register field read/write helpers */
457 static int get_field(u32 value, u32 mask, int shift)
459 return (value & (mask << shift)) >> shift;
462 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
464 return get_field(read_reg(dev, offset), mask, shift);
467 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
471 val &= ~(mask << shift);
472 val |= (field & mask) << shift;
476 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
479 u32 val = read_reg(dev, offset);
481 write_field(&val, field, mask, shift);
483 write_reg(dev, offset, val);
487 * DMA address/data block for the shadow registers
490 struct vpdma_adb_hdr out_fmt_hdr;
493 struct vpdma_adb_hdr us1_hdr;
495 struct vpdma_adb_hdr us2_hdr;
497 struct vpdma_adb_hdr us3_hdr;
499 struct vpdma_adb_hdr dei_hdr;
501 struct vpdma_adb_hdr sc_hdr0;
504 struct vpdma_adb_hdr sc_hdr8;
507 struct vpdma_adb_hdr sc_hdr17;
510 struct vpdma_adb_hdr csc_hdr;
515 #define GET_OFFSET_TOP(ctx, obj, reg) \
516 ((obj)->res->start - ctx->dev->res->start + reg)
518 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
519 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
521 * Set the headers for all of the address/data block structures.
523 static void init_adb_hdrs(struct vpe_ctx *ctx)
525 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
526 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
527 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
528 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
529 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
530 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
531 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
532 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
533 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
534 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
535 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
536 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
537 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
541 * Allocate or re-allocate the motion vector DMA buffers
542 * There are two buffers, one for input and one for output.
543 * However, the roles are reversed after each field is processed.
544 * In other words, after each field is processed, the previous
545 * output (dst) MV buffer becomes the new input (src) MV buffer.
547 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
549 struct device *dev = ctx->dev->v4l2_dev.dev;
551 if (ctx->mv_buf_size == size)
555 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
559 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
565 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
567 if (!ctx->mv_buf[0]) {
568 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
572 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
574 if (!ctx->mv_buf[1]) {
575 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
576 dma_free_coherent(dev, size, ctx->mv_buf[0],
582 ctx->mv_buf_size = size;
583 ctx->src_mv_buf_selector = 0;
588 static void free_mv_buffers(struct vpe_ctx *ctx)
590 realloc_mv_buffers(ctx, 0);
594 * While de-interlacing, we keep the two most recent input buffers
595 * around. This function frees those two buffers when we have
596 * finished processing the current stream.
598 static void free_vbs(struct vpe_ctx *ctx)
600 struct vpe_dev *dev = ctx->dev;
603 if (ctx->src_vbs[2] == NULL)
606 spin_lock_irqsave(&dev->lock, flags);
607 if (ctx->src_vbs[2]) {
608 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
609 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
610 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
611 ctx->src_vbs[2] = NULL;
612 ctx->src_vbs[1] = NULL;
614 spin_unlock_irqrestore(&dev->lock, flags);
618 * Enable or disable the VPE clocks
620 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
625 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
626 write_reg(dev, VPE_CLK_ENABLE, val);
629 static void vpe_top_reset(struct vpe_dev *dev)
632 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
633 VPE_DATA_PATH_CLK_RESET_SHIFT);
635 usleep_range(100, 150);
637 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
638 VPE_DATA_PATH_CLK_RESET_SHIFT);
641 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
643 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
644 VPE_VPDMA_CLK_RESET_SHIFT);
646 usleep_range(100, 150);
648 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
649 VPE_VPDMA_CLK_RESET_SHIFT);
653 * Load the correct of upsampler coefficients into the shadow MMRs
655 static void set_us_coefficients(struct vpe_ctx *ctx)
657 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
658 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
659 u32 *us1_reg = &mmr_adb->us1_regs[0];
660 u32 *us2_reg = &mmr_adb->us2_regs[0];
661 u32 *us3_reg = &mmr_adb->us3_regs[0];
662 const unsigned short *cp, *end_cp;
664 cp = &us_coeffs[0].anchor_fid0_c0;
666 if (s_q_data->flags & Q_IS_INTERLACED) /* interlaced */
667 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
669 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
671 while (cp < end_cp) {
672 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
673 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
674 *us2_reg++ = *us1_reg;
675 *us3_reg++ = *us1_reg++;
677 ctx->load_mmrs = true;
681 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
683 static void set_cfg_modes(struct vpe_ctx *ctx)
685 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
686 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
687 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
688 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
689 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
693 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
694 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
697 if (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
698 fmt->fourcc == V4L2_PIX_FMT_NV21)
701 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
702 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
703 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
705 ctx->load_mmrs = true;
708 static void set_line_modes(struct vpe_ctx *ctx)
710 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
713 if (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
714 fmt->fourcc == V4L2_PIX_FMT_NV21)
715 line_mode = 0; /* double lines to line buffer */
718 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
719 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
720 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
722 /* frame start for input luma */
723 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
725 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
727 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
730 /* frame start for input chroma */
731 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
732 VPE_CHAN_CHROMA1_IN);
733 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
734 VPE_CHAN_CHROMA2_IN);
735 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
736 VPE_CHAN_CHROMA3_IN);
738 /* frame start for MV in client */
739 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
744 * Set the shadow registers that are modified when the source
747 static void set_src_registers(struct vpe_ctx *ctx)
749 set_us_coefficients(ctx);
753 * Set the shadow registers that are modified when the destination
756 static void set_dst_registers(struct vpe_ctx *ctx)
758 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
759 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
760 const struct v4l2_format_info *finfo;
763 finfo = v4l2_format_info(fmt->fourcc);
764 if (v4l2_is_format_rgb(finfo)) {
765 val |= VPE_RGB_OUT_SELECT;
766 vpdma_set_bg_color(ctx->dev->vpdma,
767 (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
768 } else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
769 val |= VPE_COLOR_SEPARATE_422;
772 * the source of CHR_DS and CSC is always the scaler, irrespective of
773 * whether it's used or not
775 val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
777 if (fmt->fourcc != V4L2_PIX_FMT_NV12 &&
778 fmt->fourcc != V4L2_PIX_FMT_NV21)
779 val |= VPE_DS_BYPASS;
781 mmr_adb->out_fmt_reg[0] = val;
783 ctx->load_mmrs = true;
787 * Set the de-interlacer shadow register values
789 static void set_dei_regs(struct vpe_ctx *ctx)
791 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
792 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
793 unsigned int src_h = s_q_data->c_rect.height;
794 unsigned int src_w = s_q_data->c_rect.width;
795 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
796 bool deinterlace = true;
800 * according to TRM, we should set DEI in progressive bypass mode when
801 * the input content is progressive, however, DEI is bypassed correctly
802 * for both progressive and interlace content in interlace bypass mode.
803 * It has been recommended not to use progressive bypass mode.
805 if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
807 val = VPE_DEI_INTERLACE_BYPASS;
810 src_h = deinterlace ? src_h * 2 : src_h;
812 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
813 (src_w << VPE_DEI_WIDTH_SHIFT) |
818 ctx->load_mmrs = true;
821 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
823 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
824 u32 *dei_mmr = &mmr_adb->dei_regs[0];
825 const struct vpe_dei_regs *cur = &dei_regs;
827 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
828 dei_mmr[3] = cur->edi_config_reg;
829 dei_mmr[4] = cur->edi_lut_reg0;
830 dei_mmr[5] = cur->edi_lut_reg1;
831 dei_mmr[6] = cur->edi_lut_reg2;
832 dei_mmr[7] = cur->edi_lut_reg3;
834 ctx->load_mmrs = true;
837 static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
839 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
840 u32 *edi_config_reg = &mmr_adb->dei_regs[3];
843 write_field(edi_config_reg, 1, 1, 2); /* EDI_ENABLE_3D */
846 write_field(edi_config_reg, 1, 1, 3); /* EDI_CHROMA_3D */
848 write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
849 VPE_EDI_INP_MODE_SHIFT);
851 ctx->load_mmrs = true;
855 * Set the shadow registers whose values are modified when either the
856 * source or destination format is changed.
858 static int set_srcdst_params(struct vpe_ctx *ctx)
860 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
861 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
862 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
863 unsigned int src_w = s_q_data->c_rect.width;
864 unsigned int src_h = s_q_data->c_rect.height;
865 unsigned int dst_w = d_q_data->c_rect.width;
866 unsigned int dst_h = d_q_data->c_rect.height;
867 struct v4l2_pix_format_mplane *spix;
872 ctx->field = V4L2_FIELD_TOP;
873 spix = &s_q_data->format.fmt.pix_mp;
875 if ((s_q_data->flags & Q_IS_INTERLACED) &&
876 !(d_q_data->flags & Q_IS_INTERLACED)) {
878 const struct vpdma_data_format *mv =
879 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
882 * we make sure that the source image has a 16 byte aligned
883 * stride, we need to do the same for the motion vector buffer
884 * by aligning it's stride to the next 16 byte boundary. this
885 * extra space will not be used by the de-interlacer, but will
886 * ensure that vpdma operates correctly
888 bytes_per_line = ALIGN((spix->width * mv->depth) >> 3,
890 mv_buf_size = bytes_per_line * spix->height;
892 ctx->deinterlacing = true;
895 ctx->deinterlacing = false;
900 ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
902 ret = realloc_mv_buffers(ctx, mv_buf_size);
909 csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
910 &s_q_data->format, &d_q_data->format);
912 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
913 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
915 sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
916 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
917 src_w, src_h, dst_w, dst_h);
927 * job_ready() - check whether an instance is ready to be scheduled to run
929 static int job_ready(void *priv)
931 struct vpe_ctx *ctx = priv;
934 * This check is needed as this might be called directly from driver
935 * When called by m2m framework, this will always satisfy, but when
936 * called from vpe_irq, this might fail. (src stream with zero buffers)
938 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
939 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
945 static void job_abort(void *priv)
947 struct vpe_ctx *ctx = priv;
949 /* Will cancel the transaction in the next interrupt handler */
953 static void vpe_dump_regs(struct vpe_dev *dev)
955 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
957 vpe_dbg(dev, "VPE Registers:\n");
961 DUMPREG(INT0_STATUS0_RAW);
962 DUMPREG(INT0_STATUS0);
963 DUMPREG(INT0_ENABLE0);
964 DUMPREG(INT0_STATUS1_RAW);
965 DUMPREG(INT0_STATUS1);
966 DUMPREG(INT0_ENABLE1);
969 DUMPREG(CLK_FORMAT_SELECT);
970 DUMPREG(CLK_RANGE_MAP);
995 DUMPREG(DEI_FRAME_SIZE);
997 DUMPREG(MDT_SF_THRESHOLD);
999 DUMPREG(DEI_EDI_LUT_R0);
1000 DUMPREG(DEI_EDI_LUT_R1);
1001 DUMPREG(DEI_EDI_LUT_R2);
1002 DUMPREG(DEI_EDI_LUT_R3);
1003 DUMPREG(DEI_FMD_WINDOW_R0);
1004 DUMPREG(DEI_FMD_WINDOW_R1);
1005 DUMPREG(DEI_FMD_CONTROL_R0);
1006 DUMPREG(DEI_FMD_CONTROL_R1);
1007 DUMPREG(DEI_FMD_STATUS_R0);
1008 DUMPREG(DEI_FMD_STATUS_R1);
1009 DUMPREG(DEI_FMD_STATUS_R2);
1012 sc_dump_regs(dev->sc);
1013 csc_dump_regs(dev->csc);
1016 static void add_out_dtd(struct vpe_ctx *ctx, int port)
1018 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1019 const struct vpe_port_data *p_data = &port_data[port];
1020 struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1021 struct vpe_fmt *fmt = q_data->fmt;
1022 const struct vpdma_data_format *vpdma_fmt;
1023 int mv_buf_selector = !ctx->src_mv_buf_selector;
1024 struct v4l2_pix_format_mplane *pix;
1025 dma_addr_t dma_addr;
1030 if (port == VPE_PORT_MV_OUT) {
1031 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1032 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1033 q_data = &ctx->q_data[Q_DATA_SRC];
1034 pix = &q_data->format.fmt.pix_mp;
1035 stride = ALIGN((pix->width * vpdma_fmt->depth) >> 3,
1036 VPDMA_STRIDE_ALIGN);
1038 /* to incorporate interleaved formats */
1039 int plane = fmt->coplanar ? p_data->vb_part : 0;
1041 pix = &q_data->format.fmt.pix_mp;
1042 vpdma_fmt = fmt->vpdma_fmt[plane];
1044 * If we are using a single plane buffer and
1045 * we need to set a separate vpdma chroma channel.
1047 if (pix->num_planes == 1 && plane) {
1048 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1049 /* Compute required offset */
1050 offset = pix->plane_fmt[0].bytesperline * pix->height;
1052 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1053 /* Use address as is, no offset */
1058 "acquiring output buffer(%d) dma_addr failed\n",
1062 /* Apply the offset */
1064 stride = pix->plane_fmt[VPE_LUMA].bytesperline;
1067 if (q_data->flags & Q_DATA_FRAME_1D)
1068 flags |= VPDMA_DATA_FRAME_1D;
1069 if (q_data->flags & Q_DATA_MODE_TILED)
1070 flags |= VPDMA_DATA_MODE_TILED;
1072 vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1075 vpdma_add_out_dtd(&ctx->desc_list, pix->width,
1076 stride, &q_data->c_rect,
1077 vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1078 MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1081 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1083 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1084 const struct vpe_port_data *p_data = &port_data[port];
1085 struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1086 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1087 struct vpe_fmt *fmt = q_data->fmt;
1088 struct v4l2_pix_format_mplane *pix;
1089 const struct vpdma_data_format *vpdma_fmt;
1090 int mv_buf_selector = ctx->src_mv_buf_selector;
1091 int field = vbuf->field == V4L2_FIELD_BOTTOM;
1092 int frame_width, frame_height;
1093 dma_addr_t dma_addr;
1098 pix = &q_data->format.fmt.pix_mp;
1099 if (port == VPE_PORT_MV_IN) {
1100 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1101 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1102 stride = ALIGN((pix->width * vpdma_fmt->depth) >> 3,
1103 VPDMA_STRIDE_ALIGN);
1105 /* to incorporate interleaved formats */
1106 int plane = fmt->coplanar ? p_data->vb_part : 0;
1108 vpdma_fmt = fmt->vpdma_fmt[plane];
1110 * If we are using a single plane buffer and
1111 * we need to set a separate vpdma chroma channel.
1113 if (pix->num_planes == 1 && plane) {
1114 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1115 /* Compute required offset */
1116 offset = pix->plane_fmt[0].bytesperline * pix->height;
1118 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1119 /* Use address as is, no offset */
1124 "acquiring output buffer(%d) dma_addr failed\n",
1128 /* Apply the offset */
1130 stride = pix->plane_fmt[VPE_LUMA].bytesperline;
1133 * field used in VPDMA desc = 0 (top) / 1 (bottom)
1134 * Use top or bottom field from same vb alternately
1135 * For each de-interlacing operation, f,f-1,f-2 should be one
1138 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB ||
1139 q_data->flags & Q_DATA_INTERLACED_SEQ_BT) {
1140 /* Select initial value based on format */
1141 if (q_data->flags & Q_DATA_INTERLACED_SEQ_BT)
1146 /* Toggle for each vb_index and each operation */
1147 field = (field + p_data->vb_index + ctx->sequence) % 2;
1150 int height = pix->height / 2;
1153 if (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
1154 fmt->fourcc == V4L2_PIX_FMT_NV21)
1157 bpp = vpdma_fmt->depth >> 3;
1162 dma_addr += pix->width * height * bpp;
1167 if (q_data->flags & Q_DATA_FRAME_1D)
1168 flags |= VPDMA_DATA_FRAME_1D;
1169 if (q_data->flags & Q_DATA_MODE_TILED)
1170 flags |= VPDMA_DATA_MODE_TILED;
1172 frame_width = q_data->c_rect.width;
1173 frame_height = q_data->c_rect.height;
1175 if (p_data->vb_part && (fmt->fourcc == V4L2_PIX_FMT_NV12 ||
1176 fmt->fourcc == V4L2_PIX_FMT_NV21))
1179 vpdma_add_in_dtd(&ctx->desc_list, pix->width, stride,
1180 &q_data->c_rect, vpdma_fmt, dma_addr,
1181 p_data->channel, field, flags, frame_width,
1182 frame_height, 0, 0);
1186 * Enable the expected IRQ sources
1188 static void enable_irqs(struct vpe_ctx *ctx)
1190 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1191 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1192 VPE_DS1_UV_ERROR_INT);
1194 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1197 static void disable_irqs(struct vpe_ctx *ctx)
1199 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1200 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1202 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1205 /* device_run() - prepares and starts the device
1207 * This function is only called when both the source and destination
1208 * buffers are in place.
1210 static void device_run(void *priv)
1212 struct vpe_ctx *ctx = priv;
1213 struct sc_data *sc = ctx->dev->sc;
1214 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1215 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1216 const struct v4l2_format_info *d_finfo;
1218 d_finfo = v4l2_format_info(d_q_data->fmt->fourcc);
1220 if (ctx->deinterlacing && s_q_data->flags & Q_IS_SEQ_XX &&
1221 ctx->sequence % 2 == 0) {
1222 /* When using SEQ_XX type buffers, each buffer has two fields
1223 * each buffer has two fields (top & bottom)
1224 * Removing one buffer is actually getting two fields
1225 * Alternate between two operations:-
1226 * Even : consume one field but DO NOT REMOVE from queue
1227 * Odd : consume other field and REMOVE from queue
1229 ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1230 WARN_ON(ctx->src_vbs[0] == NULL);
1232 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1233 WARN_ON(ctx->src_vbs[0] == NULL);
1236 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1237 WARN_ON(ctx->dst_vb == NULL);
1239 if (ctx->deinterlacing) {
1241 if (ctx->src_vbs[2] == NULL) {
1242 ctx->src_vbs[2] = ctx->src_vbs[0];
1243 WARN_ON(ctx->src_vbs[2] == NULL);
1244 ctx->src_vbs[1] = ctx->src_vbs[0];
1245 WARN_ON(ctx->src_vbs[1] == NULL);
1249 * we have output the first 2 frames through line average, we
1250 * now switch to EDI de-interlacer
1252 if (ctx->sequence == 2)
1253 config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */
1256 /* config descriptors */
1257 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1258 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1259 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1261 set_line_modes(ctx);
1263 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1264 ctx->load_mmrs = false;
1267 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1269 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1270 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1271 &ctx->sc_coeff_h, 0);
1273 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1274 sc->load_coeff_h = false;
1277 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1279 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1280 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1281 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1283 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1284 sc->load_coeff_v = false;
1287 /* output data descriptors */
1288 if (ctx->deinterlacing)
1289 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1291 if (v4l2_is_format_rgb(d_finfo)) {
1292 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1294 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1295 if (d_q_data->fmt->coplanar)
1296 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1299 /* input data descriptors */
1300 if (ctx->deinterlacing) {
1301 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1302 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1304 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1305 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1308 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1309 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1311 if (ctx->deinterlacing)
1312 add_in_dtd(ctx, VPE_PORT_MV_IN);
1314 /* sync on channel control descriptors for input ports */
1315 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1316 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1318 if (ctx->deinterlacing) {
1319 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1321 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1322 VPE_CHAN_CHROMA2_IN);
1324 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1326 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1327 VPE_CHAN_CHROMA3_IN);
1329 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1332 /* sync on channel control descriptors for output ports */
1333 if (v4l2_is_format_rgb(d_finfo)) {
1334 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1337 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1339 if (d_q_data->fmt->coplanar)
1340 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1341 VPE_CHAN_CHROMA_OUT);
1344 if (ctx->deinterlacing)
1345 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1349 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1350 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1353 static void dei_error(struct vpe_ctx *ctx)
1355 dev_warn(ctx->dev->v4l2_dev.dev,
1356 "received DEI error interrupt\n");
1359 static void ds1_uv_error(struct vpe_ctx *ctx)
1361 dev_warn(ctx->dev->v4l2_dev.dev,
1362 "received downsampler error interrupt\n");
1365 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1367 struct vpe_dev *dev = (struct vpe_dev *)data;
1368 struct vpe_ctx *ctx;
1369 struct vpe_q_data *d_q_data;
1370 struct vb2_v4l2_buffer *s_vb, *d_vb;
1371 unsigned long flags;
1373 bool list_complete = false;
1375 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1377 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1378 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1381 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1383 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1384 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1387 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1389 vpe_err(dev, "instance released before end of transaction\n");
1394 if (irqst1 & VPE_DEI_ERROR_INT) {
1395 irqst1 &= ~VPE_DEI_ERROR_INT;
1398 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1399 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1405 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1406 vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1408 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1409 list_complete = true;
1412 if (irqst0 | irqst1) {
1413 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1418 * Setup next operation only when list complete IRQ occurs
1419 * otherwise, skip the following code
1426 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1427 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1428 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1429 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1431 vpdma_reset_desc_list(&ctx->desc_list);
1433 /* the previous dst mv buffer becomes the next src mv buffer */
1434 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1436 s_vb = ctx->src_vbs[0];
1439 d_vb->flags = s_vb->flags;
1440 d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1442 if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1443 d_vb->timecode = s_vb->timecode;
1445 d_vb->sequence = ctx->sequence;
1446 s_vb->sequence = ctx->sequence;
1448 d_q_data = &ctx->q_data[Q_DATA_DST];
1449 if (d_q_data->flags & Q_IS_INTERLACED) {
1450 d_vb->field = ctx->field;
1451 if (ctx->field == V4L2_FIELD_BOTTOM) {
1453 ctx->field = V4L2_FIELD_TOP;
1455 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1456 ctx->field = V4L2_FIELD_BOTTOM;
1459 d_vb->field = V4L2_FIELD_NONE;
1463 if (ctx->deinterlacing) {
1465 * Allow source buffer to be dequeued only if it won't be used
1466 * in the next iteration. All vbs are initialized to first
1467 * buffer and we are shifting buffers every iteration, for the
1468 * first two iterations, no buffer will be dequeued.
1469 * This ensures that driver will keep (n-2)th (n-1)th and (n)th
1470 * field when deinterlacing is enabled
1472 if (ctx->src_vbs[2] != ctx->src_vbs[1])
1473 s_vb = ctx->src_vbs[2];
1478 spin_lock_irqsave(&dev->lock, flags);
1481 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1483 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1485 spin_unlock_irqrestore(&dev->lock, flags);
1487 if (ctx->deinterlacing) {
1488 ctx->src_vbs[2] = ctx->src_vbs[1];
1489 ctx->src_vbs[1] = ctx->src_vbs[0];
1493 * Since the vb2_buf_done has already been called fir therse
1494 * buffer we can now NULL them out so that we won't try
1495 * to clean out stray pointer later on.
1497 ctx->src_vbs[0] = NULL;
1503 ctx->bufs_completed++;
1504 if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1510 vpe_dbg(ctx->dev, "finishing transaction\n");
1511 ctx->bufs_completed = 0;
1512 v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1520 static int vpe_querycap(struct file *file, void *priv,
1521 struct v4l2_capability *cap)
1523 strscpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver));
1524 strscpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card));
1525 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1530 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1533 struct vpe_fmt *fmt = NULL;
1536 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1537 if (vpe_formats[i].types & type) {
1538 if (index == f->index) {
1539 fmt = &vpe_formats[i];
1549 f->pixelformat = fmt->fourcc;
1553 static int vpe_enum_fmt(struct file *file, void *priv,
1554 struct v4l2_fmtdesc *f)
1556 if (V4L2_TYPE_IS_OUTPUT(f->type))
1557 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1559 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1562 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1564 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1565 struct vpe_ctx *ctx = file->private_data;
1566 struct vb2_queue *vq;
1567 struct vpe_q_data *q_data;
1569 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1573 q_data = get_q_data(ctx, f->type);
1577 *f = q_data->format;
1579 if (V4L2_TYPE_IS_CAPTURE(f->type)) {
1580 struct vpe_q_data *s_q_data;
1581 struct v4l2_pix_format_mplane *spix;
1583 /* get colorimetry from the source queue */
1584 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1585 spix = &s_q_data->format.fmt.pix_mp;
1587 pix->colorspace = spix->colorspace;
1588 pix->xfer_func = spix->xfer_func;
1589 pix->ycbcr_enc = spix->ycbcr_enc;
1590 pix->quantization = spix->quantization;
1596 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1597 struct vpe_fmt *fmt, int type)
1599 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1600 struct v4l2_plane_pix_format *plane_fmt;
1601 unsigned int w_align;
1602 int i, depth, depth_bytes, height;
1603 unsigned int stride = 0;
1604 const struct v4l2_format_info *finfo;
1606 if (!fmt || !(fmt->types & type)) {
1607 vpe_dbg(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1609 fmt = __find_format(V4L2_PIX_FMT_YUYV);
1612 if (pix->field != V4L2_FIELD_NONE &&
1613 pix->field != V4L2_FIELD_ALTERNATE &&
1614 pix->field != V4L2_FIELD_SEQ_TB &&
1615 pix->field != V4L2_FIELD_SEQ_BT)
1616 pix->field = V4L2_FIELD_NONE;
1618 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1621 * the line stride should 16 byte aligned for VPDMA to work, based on
1622 * the bytes per pixel, figure out how much the width should be aligned
1623 * to make sure line stride is 16 byte aligned
1625 depth_bytes = depth >> 3;
1627 if (depth_bytes == 3) {
1629 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1630 * really help in ensuring line stride is 16 byte aligned
1635 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1636 * can ensure a line stride alignment of 16 bytes. For example,
1637 * if bpp is 2, then the line stride can be 16 byte aligned if
1638 * the width is 8 byte aligned
1642 * HACK: using order_base_2() here causes lots of asm output
1643 * errors with smatch, on i386:
1644 * ./arch/x86/include/asm/bitops.h:457:22:
1645 * warning: asm output is not an lvalue
1646 * Perhaps some gcc optimization is doing the wrong thing
1648 * Let's get rid of them by doing the calculus on two steps
1650 w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes);
1651 w_align = ilog2(w_align);
1654 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1655 &pix->height, MIN_H, MAX_H, H_ALIGN,
1658 if (!pix->num_planes || pix->num_planes > 2)
1659 pix->num_planes = fmt->coplanar ? 2 : 1;
1660 else if (pix->num_planes > 1 && !fmt->coplanar)
1661 pix->num_planes = 1;
1663 pix->pixelformat = fmt->fourcc;
1664 finfo = v4l2_format_info(fmt->fourcc);
1667 * For the actual image parameters, we need to consider the field
1668 * height of the image for SEQ_XX buffers.
1670 if (pix->field == V4L2_FIELD_SEQ_TB || pix->field == V4L2_FIELD_SEQ_BT)
1671 height = pix->height / 2;
1673 height = pix->height;
1675 if (!pix->colorspace) {
1676 if (v4l2_is_format_rgb(finfo)) {
1677 pix->colorspace = V4L2_COLORSPACE_SRGB;
1679 if (height > 1280) /* HD */
1680 pix->colorspace = V4L2_COLORSPACE_REC709;
1682 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1686 memset(pix->reserved, 0, sizeof(pix->reserved));
1687 for (i = 0; i < pix->num_planes; i++) {
1688 plane_fmt = &pix->plane_fmt[i];
1689 depth = fmt->vpdma_fmt[i]->depth;
1691 stride = (pix->width * fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1692 if (stride > plane_fmt->bytesperline)
1693 plane_fmt->bytesperline = stride;
1695 plane_fmt->bytesperline = clamp_t(u32, plane_fmt->bytesperline,
1699 plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline,
1700 VPDMA_STRIDE_ALIGN);
1702 if (i == VPE_LUMA) {
1703 plane_fmt->sizeimage = pix->height *
1704 plane_fmt->bytesperline;
1706 if (pix->num_planes == 1 && fmt->coplanar)
1707 plane_fmt->sizeimage += pix->height *
1708 plane_fmt->bytesperline *
1709 fmt->vpdma_fmt[VPE_CHROMA]->depth >> 3;
1711 } else { /* i == VIP_CHROMA */
1712 plane_fmt->sizeimage = (pix->height *
1713 plane_fmt->bytesperline *
1716 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1722 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1724 struct vpe_ctx *ctx = file->private_data;
1725 struct vpe_fmt *fmt = find_format(f);
1727 if (V4L2_TYPE_IS_OUTPUT(f->type))
1728 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1730 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1733 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1735 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1736 struct v4l2_pix_format_mplane *qpix;
1737 struct vpe_q_data *q_data;
1738 struct vb2_queue *vq;
1740 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1744 if (vb2_is_busy(vq)) {
1745 vpe_err(ctx->dev, "queue busy\n");
1749 q_data = get_q_data(ctx, f->type);
1753 qpix = &q_data->format.fmt.pix_mp;
1754 q_data->fmt = find_format(f);
1755 q_data->format = *f;
1757 q_data->c_rect.left = 0;
1758 q_data->c_rect.top = 0;
1759 q_data->c_rect.width = pix->width;
1760 q_data->c_rect.height = pix->height;
1762 if (qpix->field == V4L2_FIELD_ALTERNATE)
1763 q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1764 else if (qpix->field == V4L2_FIELD_SEQ_TB)
1765 q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1766 else if (qpix->field == V4L2_FIELD_SEQ_BT)
1767 q_data->flags |= Q_DATA_INTERLACED_SEQ_BT;
1769 q_data->flags &= ~Q_IS_INTERLACED;
1771 /* the crop height is halved for the case of SEQ_XX buffers */
1772 if (q_data->flags & Q_IS_SEQ_XX)
1773 q_data->c_rect.height /= 2;
1775 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1776 f->type, pix->width, pix->height, pix->pixelformat,
1777 pix->plane_fmt[0].bytesperline);
1778 if (pix->num_planes == 2)
1779 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1780 pix->plane_fmt[1].bytesperline);
1785 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1788 struct vpe_ctx *ctx = file->private_data;
1790 ret = vpe_try_fmt(file, priv, f);
1794 ret = __vpe_s_fmt(ctx, f);
1798 if (V4L2_TYPE_IS_OUTPUT(f->type))
1799 set_src_registers(ctx);
1801 set_dst_registers(ctx);
1803 return set_srcdst_params(ctx);
1806 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1808 struct vpe_q_data *q_data;
1809 struct v4l2_pix_format_mplane *pix;
1812 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1813 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1816 q_data = get_q_data(ctx, s->type);
1820 pix = &q_data->format.fmt.pix_mp;
1822 switch (s->target) {
1823 case V4L2_SEL_TGT_COMPOSE:
1825 * COMPOSE target is only valid for capture buffer type, return
1826 * error for output buffer type
1828 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1831 case V4L2_SEL_TGT_CROP:
1833 * CROP target is only valid for output buffer type, return
1834 * error for capture buffer type
1836 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1840 * bound and default crop/compose targets are invalid targets to
1848 * For SEQ_XX buffers, crop height should be less than the height of
1849 * the field height, not the buffer height
1851 if (q_data->flags & Q_IS_SEQ_XX)
1852 height = pix->height / 2;
1854 height = pix->height;
1856 if (s->r.top < 0 || s->r.left < 0) {
1857 vpe_err(ctx->dev, "negative values for top and left\n");
1858 s->r.top = s->r.left = 0;
1861 v4l_bound_align_image(&s->r.width, MIN_W, pix->width, 1,
1862 &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1864 /* adjust left/top if cropping rectangle is out of bounds */
1865 if (s->r.left + s->r.width > pix->width)
1866 s->r.left = pix->width - s->r.width;
1867 if (s->r.top + s->r.height > pix->height)
1868 s->r.top = pix->height - s->r.height;
1873 static int vpe_g_selection(struct file *file, void *fh,
1874 struct v4l2_selection *s)
1876 struct vpe_ctx *ctx = file->private_data;
1877 struct vpe_q_data *q_data;
1878 struct v4l2_pix_format_mplane *pix;
1879 bool use_c_rect = false;
1881 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1882 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1885 q_data = get_q_data(ctx, s->type);
1889 pix = &q_data->format.fmt.pix_mp;
1891 switch (s->target) {
1892 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1893 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1894 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1897 case V4L2_SEL_TGT_CROP_BOUNDS:
1898 case V4L2_SEL_TGT_CROP_DEFAULT:
1899 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1902 case V4L2_SEL_TGT_COMPOSE:
1903 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1907 case V4L2_SEL_TGT_CROP:
1908 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1918 * for CROP/COMPOSE target type, return c_rect params from the
1919 * respective buffer type
1921 s->r = q_data->c_rect;
1924 * for DEFAULT/BOUNDS target type, return width and height from
1925 * S_FMT of the respective buffer type
1929 s->r.width = pix->width;
1930 s->r.height = pix->height;
1937 static int vpe_s_selection(struct file *file, void *fh,
1938 struct v4l2_selection *s)
1940 struct vpe_ctx *ctx = file->private_data;
1941 struct vpe_q_data *q_data;
1942 struct v4l2_selection sel = *s;
1945 ret = __vpe_try_selection(ctx, &sel);
1949 q_data = get_q_data(ctx, sel.type);
1953 if ((q_data->c_rect.left == sel.r.left) &&
1954 (q_data->c_rect.top == sel.r.top) &&
1955 (q_data->c_rect.width == sel.r.width) &&
1956 (q_data->c_rect.height == sel.r.height)) {
1958 "requested crop/compose values are already set\n");
1962 q_data->c_rect = sel.r;
1964 return set_srcdst_params(ctx);
1968 * defines number of buffers/frames a context can process with VPE before
1969 * switching to a different context. default value is 1 buffer per context
1971 #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1973 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1975 struct vpe_ctx *ctx =
1976 container_of(ctrl->handler, struct vpe_ctx, hdl);
1979 case V4L2_CID_VPE_BUFS_PER_JOB:
1980 ctx->bufs_per_job = ctrl->val;
1984 vpe_err(ctx->dev, "Invalid control\n");
1991 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1992 .s_ctrl = vpe_s_ctrl,
1995 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1996 .vidioc_querycap = vpe_querycap,
1998 .vidioc_enum_fmt_vid_cap = vpe_enum_fmt,
1999 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
2000 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
2001 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
2003 .vidioc_enum_fmt_vid_out = vpe_enum_fmt,
2004 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
2005 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
2006 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
2008 .vidioc_g_selection = vpe_g_selection,
2009 .vidioc_s_selection = vpe_s_selection,
2011 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
2012 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
2013 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
2014 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
2015 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
2016 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
2017 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
2019 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2020 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2026 static int vpe_queue_setup(struct vb2_queue *vq,
2027 unsigned int *nbuffers, unsigned int *nplanes,
2028 unsigned int sizes[], struct device *alloc_devs[])
2031 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
2032 struct vpe_q_data *q_data;
2033 struct v4l2_pix_format_mplane *pix;
2035 q_data = get_q_data(ctx, vq->type);
2039 pix = &q_data->format.fmt.pix_mp;
2040 *nplanes = pix->num_planes;
2042 for (i = 0; i < *nplanes; i++)
2043 sizes[i] = pix->plane_fmt[i].sizeimage;
2045 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
2048 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
2053 static int vpe_buf_prepare(struct vb2_buffer *vb)
2055 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2056 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2057 struct vpe_q_data *q_data;
2058 struct v4l2_pix_format_mplane *pix;
2061 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
2063 q_data = get_q_data(ctx, vb->vb2_queue->type);
2067 pix = &q_data->format.fmt.pix_mp;
2069 if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
2070 if (!(q_data->flags & Q_IS_INTERLACED)) {
2071 vbuf->field = V4L2_FIELD_NONE;
2073 if (vbuf->field != V4L2_FIELD_TOP &&
2074 vbuf->field != V4L2_FIELD_BOTTOM &&
2075 vbuf->field != V4L2_FIELD_SEQ_TB &&
2076 vbuf->field != V4L2_FIELD_SEQ_BT)
2081 for (i = 0; i < pix->num_planes; i++) {
2082 if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
2084 "data will not fit into plane (%lu < %lu)\n",
2085 vb2_plane_size(vb, i),
2086 (long)pix->plane_fmt[i].sizeimage);
2091 for (i = 0; i < pix->num_planes; i++)
2092 vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
2097 static void vpe_buf_queue(struct vb2_buffer *vb)
2099 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2100 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2102 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2105 static int check_srcdst_sizes(struct vpe_ctx *ctx)
2107 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
2108 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
2109 unsigned int src_w = s_q_data->c_rect.width;
2110 unsigned int src_h = s_q_data->c_rect.height;
2111 unsigned int dst_w = d_q_data->c_rect.width;
2112 unsigned int dst_h = d_q_data->c_rect.height;
2114 if (src_w == dst_w && src_h == dst_h)
2117 if (src_h <= SC_MAX_PIXEL_HEIGHT &&
2118 src_w <= SC_MAX_PIXEL_WIDTH &&
2119 dst_h <= SC_MAX_PIXEL_HEIGHT &&
2120 dst_w <= SC_MAX_PIXEL_WIDTH)
2126 static void vpe_return_all_buffers(struct vpe_ctx *ctx, struct vb2_queue *q,
2127 enum vb2_buffer_state state)
2129 struct vb2_v4l2_buffer *vb;
2130 unsigned long flags;
2133 if (V4L2_TYPE_IS_OUTPUT(q->type))
2134 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
2136 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2139 spin_lock_irqsave(&ctx->dev->lock, flags);
2140 v4l2_m2m_buf_done(vb, state);
2141 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2145 * Cleanup the in-transit vb2 buffers that have been
2146 * removed from their respective queue already but for
2147 * which procecessing has not been completed yet.
2149 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2150 spin_lock_irqsave(&ctx->dev->lock, flags);
2152 if (ctx->src_vbs[2])
2153 v4l2_m2m_buf_done(ctx->src_vbs[2], state);
2155 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
2156 v4l2_m2m_buf_done(ctx->src_vbs[1], state);
2158 if (ctx->src_vbs[0] &&
2159 (ctx->src_vbs[0] != ctx->src_vbs[1]) &&
2160 (ctx->src_vbs[0] != ctx->src_vbs[2]))
2161 v4l2_m2m_buf_done(ctx->src_vbs[0], state);
2163 ctx->src_vbs[2] = NULL;
2164 ctx->src_vbs[1] = NULL;
2165 ctx->src_vbs[0] = NULL;
2167 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2170 spin_lock_irqsave(&ctx->dev->lock, flags);
2172 v4l2_m2m_buf_done(ctx->dst_vb, state);
2174 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2179 static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2181 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2183 /* Check any of the size exceed maximum scaling sizes */
2184 if (check_srcdst_sizes(ctx)) {
2186 "Conversion setup failed, check source and destination parameters\n"
2188 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED);
2192 if (ctx->deinterlacing)
2193 config_edi_input_mode(ctx, 0x0);
2195 if (ctx->sequence != 0)
2196 set_srcdst_params(ctx);
2201 static void vpe_stop_streaming(struct vb2_queue *q)
2203 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2205 vpe_dump_regs(ctx->dev);
2206 vpdma_dump_regs(ctx->dev->vpdma);
2208 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR);
2211 static const struct vb2_ops vpe_qops = {
2212 .queue_setup = vpe_queue_setup,
2213 .buf_prepare = vpe_buf_prepare,
2214 .buf_queue = vpe_buf_queue,
2215 .wait_prepare = vb2_ops_wait_prepare,
2216 .wait_finish = vb2_ops_wait_finish,
2217 .start_streaming = vpe_start_streaming,
2218 .stop_streaming = vpe_stop_streaming,
2221 static int queue_init(void *priv, struct vb2_queue *src_vq,
2222 struct vb2_queue *dst_vq)
2224 struct vpe_ctx *ctx = priv;
2225 struct vpe_dev *dev = ctx->dev;
2228 memset(src_vq, 0, sizeof(*src_vq));
2229 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2230 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2231 src_vq->drv_priv = ctx;
2232 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2233 src_vq->ops = &vpe_qops;
2234 src_vq->mem_ops = &vb2_dma_contig_memops;
2235 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2236 src_vq->lock = &dev->dev_mutex;
2237 src_vq->dev = dev->v4l2_dev.dev;
2239 ret = vb2_queue_init(src_vq);
2243 memset(dst_vq, 0, sizeof(*dst_vq));
2244 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2245 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2246 dst_vq->drv_priv = ctx;
2247 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2248 dst_vq->ops = &vpe_qops;
2249 dst_vq->mem_ops = &vb2_dma_contig_memops;
2250 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2251 dst_vq->lock = &dev->dev_mutex;
2252 dst_vq->dev = dev->v4l2_dev.dev;
2254 return vb2_queue_init(dst_vq);
2257 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2258 .ops = &vpe_ctrl_ops,
2259 .id = V4L2_CID_VPE_BUFS_PER_JOB,
2260 .name = "Buffers Per Transaction",
2261 .type = V4L2_CTRL_TYPE_INTEGER,
2262 .def = VPE_DEF_BUFS_PER_JOB,
2264 .max = VIDEO_MAX_FRAME,
2271 static int vpe_open(struct file *file)
2273 struct vpe_dev *dev = video_drvdata(file);
2274 struct vpe_q_data *s_q_data;
2275 struct v4l2_ctrl_handler *hdl;
2276 struct vpe_ctx *ctx;
2277 struct v4l2_pix_format_mplane *pix;
2280 vpe_dbg(dev, "vpe_open\n");
2282 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2288 if (mutex_lock_interruptible(&dev->dev_mutex)) {
2293 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2294 VPDMA_LIST_TYPE_NORMAL);
2298 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2300 goto free_desc_list;
2302 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2306 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2312 v4l2_fh_init(&ctx->fh, video_devdata(file));
2313 file->private_data = ctx;
2316 v4l2_ctrl_handler_init(hdl, 1);
2317 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2322 ctx->fh.ctrl_handler = hdl;
2323 v4l2_ctrl_handler_setup(hdl);
2325 s_q_data = &ctx->q_data[Q_DATA_SRC];
2326 pix = &s_q_data->format.fmt.pix_mp;
2327 s_q_data->fmt = __find_format(V4L2_PIX_FMT_YUYV);
2328 pix->pixelformat = s_q_data->fmt->fourcc;
2329 s_q_data->format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2332 pix->num_planes = 1;
2333 pix->plane_fmt[VPE_LUMA].bytesperline = (pix->width *
2334 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2335 pix->plane_fmt[VPE_LUMA].sizeimage =
2336 pix->plane_fmt[VPE_LUMA].bytesperline *
2338 pix->colorspace = V4L2_COLORSPACE_REC709;
2339 pix->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2340 pix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2341 pix->quantization = V4L2_QUANTIZATION_DEFAULT;
2342 pix->field = V4L2_FIELD_NONE;
2343 s_q_data->c_rect.left = 0;
2344 s_q_data->c_rect.top = 0;
2345 s_q_data->c_rect.width = pix->width;
2346 s_q_data->c_rect.height = pix->height;
2347 s_q_data->flags = 0;
2349 ctx->q_data[Q_DATA_DST] = *s_q_data;
2350 ctx->q_data[Q_DATA_DST].format.type =
2351 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2353 set_dei_shadow_registers(ctx);
2354 set_src_registers(ctx);
2355 set_dst_registers(ctx);
2356 ret = set_srcdst_params(ctx);
2360 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2362 if (IS_ERR(ctx->fh.m2m_ctx)) {
2363 ret = PTR_ERR(ctx->fh.m2m_ctx);
2367 v4l2_fh_add(&ctx->fh);
2370 * for now, just report the creation of the first instance, we can later
2371 * optimize the driver to enable or disable clocks when the first
2372 * instance is created or the last instance released
2374 if (atomic_inc_return(&dev->num_instances) == 1)
2375 vpe_dbg(dev, "first instance created\n");
2377 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2379 ctx->load_mmrs = true;
2381 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2382 ctx, ctx->fh.m2m_ctx);
2384 mutex_unlock(&dev->dev_mutex);
2388 v4l2_ctrl_handler_free(hdl);
2389 v4l2_fh_exit(&ctx->fh);
2390 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2392 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2394 vpdma_free_desc_buf(&ctx->mmr_adb);
2396 vpdma_free_desc_list(&ctx->desc_list);
2398 mutex_unlock(&dev->dev_mutex);
2404 static int vpe_release(struct file *file)
2406 struct vpe_dev *dev = video_drvdata(file);
2407 struct vpe_ctx *ctx = file->private_data;
2409 vpe_dbg(dev, "releasing instance %p\n", ctx);
2411 mutex_lock(&dev->dev_mutex);
2412 free_mv_buffers(ctx);
2414 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
2415 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
2416 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
2417 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
2419 vpdma_free_desc_list(&ctx->desc_list);
2420 vpdma_free_desc_buf(&ctx->mmr_adb);
2422 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2423 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2425 v4l2_fh_del(&ctx->fh);
2426 v4l2_fh_exit(&ctx->fh);
2427 v4l2_ctrl_handler_free(&ctx->hdl);
2428 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2433 * for now, just report the release of the last instance, we can later
2434 * optimize the driver to enable or disable clocks when the first
2435 * instance is created or the last instance released
2437 if (atomic_dec_return(&dev->num_instances) == 0)
2438 vpe_dbg(dev, "last instance released\n");
2440 mutex_unlock(&dev->dev_mutex);
2445 static const struct v4l2_file_operations vpe_fops = {
2446 .owner = THIS_MODULE,
2448 .release = vpe_release,
2449 .poll = v4l2_m2m_fop_poll,
2450 .unlocked_ioctl = video_ioctl2,
2451 .mmap = v4l2_m2m_fop_mmap,
2454 static const struct video_device vpe_videodev = {
2455 .name = VPE_MODULE_NAME,
2457 .ioctl_ops = &vpe_ioctl_ops,
2459 .release = video_device_release_empty,
2460 .vfl_dir = VFL_DIR_M2M,
2461 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
2464 static const struct v4l2_m2m_ops m2m_ops = {
2465 .device_run = device_run,
2466 .job_ready = job_ready,
2467 .job_abort = job_abort,
2470 static int vpe_runtime_get(struct platform_device *pdev)
2474 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2476 r = pm_runtime_get_sync(&pdev->dev);
2479 pm_runtime_put_noidle(&pdev->dev);
2480 return r < 0 ? r : 0;
2483 static void vpe_runtime_put(struct platform_device *pdev)
2488 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2490 r = pm_runtime_put_sync(&pdev->dev);
2491 WARN_ON(r < 0 && r != -ENOSYS);
2494 static void vpe_fw_cb(struct platform_device *pdev)
2496 struct vpe_dev *dev = platform_get_drvdata(pdev);
2497 struct video_device *vfd;
2501 *vfd = vpe_videodev;
2502 vfd->lock = &dev->dev_mutex;
2503 vfd->v4l2_dev = &dev->v4l2_dev;
2505 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
2507 vpe_err(dev, "Failed to register video device\n");
2509 vpe_set_clock_enable(dev, 0);
2510 vpe_runtime_put(pdev);
2511 pm_runtime_disable(&pdev->dev);
2512 v4l2_m2m_release(dev->m2m_dev);
2513 v4l2_device_unregister(&dev->v4l2_dev);
2518 video_set_drvdata(vfd, dev);
2519 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2523 static int vpe_probe(struct platform_device *pdev)
2525 struct vpe_dev *dev;
2528 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2531 "32-bit consistent DMA enable failed\n");
2535 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2539 spin_lock_init(&dev->lock);
2541 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2545 atomic_set(&dev->num_instances, 0);
2546 mutex_init(&dev->dev_mutex);
2548 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2551 dev_err(&pdev->dev, "missing 'vpe_top' resources data\n");
2556 * HACK: we get resource info from device tree in the form of a list of
2557 * VPE sub blocks, the driver currently uses only the base of vpe_top
2558 * for register access, the driver should be changed later to access
2559 * registers based on the sub block base addresses
2561 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2564 goto v4l2_dev_unreg;
2567 irq = platform_get_irq(pdev, 0);
2568 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2571 goto v4l2_dev_unreg;
2573 platform_set_drvdata(pdev, dev);
2575 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2576 if (IS_ERR(dev->m2m_dev)) {
2577 vpe_err(dev, "Failed to init mem2mem device\n");
2578 ret = PTR_ERR(dev->m2m_dev);
2579 goto v4l2_dev_unreg;
2582 pm_runtime_enable(&pdev->dev);
2584 ret = vpe_runtime_get(pdev);
2588 /* Perform clk enable followed by reset */
2589 vpe_set_clock_enable(dev, 1);
2593 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2594 VPE_PID_FUNC_SHIFT);
2595 vpe_dbg(dev, "VPE PID function %x\n", func);
2597 vpe_top_vpdma_reset(dev);
2599 dev->sc = sc_create(pdev, "sc");
2600 if (IS_ERR(dev->sc)) {
2601 ret = PTR_ERR(dev->sc);
2605 dev->csc = csc_create(pdev, "csc");
2606 if (IS_ERR(dev->csc)) {
2607 ret = PTR_ERR(dev->csc);
2611 dev->vpdma = &dev->vpdma_data;
2612 ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb);
2619 vpe_runtime_put(pdev);
2621 pm_runtime_disable(&pdev->dev);
2622 v4l2_m2m_release(dev->m2m_dev);
2624 v4l2_device_unregister(&dev->v4l2_dev);
2629 static int vpe_remove(struct platform_device *pdev)
2631 struct vpe_dev *dev = platform_get_drvdata(pdev);
2633 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2635 v4l2_m2m_release(dev->m2m_dev);
2636 video_unregister_device(&dev->vfd);
2637 v4l2_device_unregister(&dev->v4l2_dev);
2639 vpe_set_clock_enable(dev, 0);
2640 vpe_runtime_put(pdev);
2641 pm_runtime_disable(&pdev->dev);
2646 #if defined(CONFIG_OF)
2647 static const struct of_device_id vpe_of_match[] = {
2649 .compatible = "ti,dra7-vpe",
2653 MODULE_DEVICE_TABLE(of, vpe_of_match);
2656 static struct platform_driver vpe_pdrv = {
2658 .remove = vpe_remove,
2660 .name = VPE_MODULE_NAME,
2661 .of_match_table = of_match_ptr(vpe_of_match),
2665 module_platform_driver(vpe_pdrv);
2667 MODULE_DESCRIPTION("TI VPE driver");
2668 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2669 MODULE_LICENSE("GPL");