1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
10 #ifndef _TI_VPDMA_PRIV_H_
11 #define _TI_VPDMA_PRIV_H_
14 * VPDMA Register offsets
18 #define VPDMA_PID 0x00
19 #define VPDMA_LIST_ADDR 0x04
20 #define VPDMA_LIST_ATTR 0x08
21 #define VPDMA_LIST_STAT_SYNC 0x0c
22 #define VPDMA_BG_RGB 0x18
23 #define VPDMA_BG_YUV 0x1c
24 #define VPDMA_SETUP 0x30
25 #define VPDMA_MAX_SIZE1 0x34
26 #define VPDMA_MAX_SIZE2 0x38
27 #define VPDMA_MAX_SIZE3 0x3c
28 #define VPDMA_MAX_SIZE_WIDTH_MASK 0xffff
29 #define VPDMA_MAX_SIZE_WIDTH_SHFT 16
30 #define VPDMA_MAX_SIZE_HEIGHT_MASK 0xffff
31 #define VPDMA_MAX_SIZE_HEIGHT_SHFT 0
34 #define VPDMA_INT_CHAN_STAT(grp) (0x40 + grp * 8)
35 #define VPDMA_INT_CHAN_MASK(grp) (VPDMA_INT_CHAN_STAT(grp) + 4)
36 #define VPDMA_INT_CLIENT0_STAT 0x78
37 #define VPDMA_INT_CLIENT0_MASK 0x7c
38 #define VPDMA_INT_CLIENT1_STAT 0x80
39 #define VPDMA_INT_CLIENT1_MASK 0x84
40 #define VPDMA_INT_LIST0_STAT 0x88
41 #define VPDMA_INT_LIST0_MASK 0x8c
43 #define VPDMA_INTX_OFFSET 0x50
45 #define VPDMA_PERFMON(i) (0x200 + i * 4)
47 /* VIP/VPE client registers */
48 #define VPDMA_DEI_CHROMA1_CSTAT 0x0300
49 #define VPDMA_DEI_LUMA1_CSTAT 0x0304
50 #define VPDMA_DEI_LUMA2_CSTAT 0x0308
51 #define VPDMA_DEI_CHROMA2_CSTAT 0x030c
52 #define VPDMA_DEI_LUMA3_CSTAT 0x0310
53 #define VPDMA_DEI_CHROMA3_CSTAT 0x0314
54 #define VPDMA_DEI_MV_IN_CSTAT 0x0330
55 #define VPDMA_DEI_MV_OUT_CSTAT 0x033c
56 #define VPDMA_VIP_LO_Y_CSTAT 0x0388
57 #define VPDMA_VIP_LO_UV_CSTAT 0x038c
58 #define VPDMA_VIP_UP_Y_CSTAT 0x0390
59 #define VPDMA_VIP_UP_UV_CSTAT 0x0394
60 #define VPDMA_VPI_CTL_CSTAT 0x03d0
62 /* Reg field info for VPDMA_CLIENT_CSTAT registers */
63 #define VPDMA_CSTAT_LINE_MODE_MASK 0x03
64 #define VPDMA_CSTAT_LINE_MODE_SHIFT 8
65 #define VPDMA_CSTAT_FRAME_START_MASK 0xf
66 #define VPDMA_CSTAT_FRAME_START_SHIFT 10
68 #define VPDMA_LIST_NUM_MASK 0x07
69 #define VPDMA_LIST_NUM_SHFT 24
70 #define VPDMA_LIST_STOP_SHFT 20
71 #define VPDMA_LIST_RDY_MASK 0x01
72 #define VPDMA_LIST_RDY_SHFT 19
73 #define VPDMA_LIST_TYPE_MASK 0x03
74 #define VPDMA_LIST_TYPE_SHFT 16
75 #define VPDMA_LIST_SIZE_MASK 0xffff
78 * The YUV data type definition below are taken from
79 * both the TRM and i839 Errata information.
80 * Use the correct data type considering byte
81 * reordering of components.
83 * Also since the single use of "C" in the 422 case
84 * to mean "Cr" (i.e. V component). It was decided
85 * to explicitly label them CR to remove any confusion.
86 * Bear in mind that the type label refer to the memory
87 * packed order (LSB - MSB).
89 #define DATA_TYPE_Y444 0x0
90 #define DATA_TYPE_Y422 0x1
91 #define DATA_TYPE_Y420 0x2
92 #define DATA_TYPE_C444 0x4
93 #define DATA_TYPE_C422 0x5
94 #define DATA_TYPE_C420 0x6
95 #define DATA_TYPE_CB420 0x16
96 #define DATA_TYPE_YC444 0x8
97 #define DATA_TYPE_YCB422 0x7
98 #define DATA_TYPE_YCR422 0x17
99 #define DATA_TYPE_CBY422 0x27
100 #define DATA_TYPE_CRY422 0x37
103 * The RGB data type definition below are defined
104 * to follow Errata i819.
105 * The initial values were taken from:
106 * VPDMA_data_type_mapping_v0.2vayu_c.pdf
107 * But some of the ARGB definition appeared to be wrong
108 * in the document also. As they would yield RGBA instead.
109 * They have been corrected based on experimentation.
111 #define DATA_TYPE_RGB16_565 0x10
112 #define DATA_TYPE_ARGB_1555 0x13
113 #define DATA_TYPE_ARGB_4444 0x14
114 #define DATA_TYPE_RGBA_5551 0x11
115 #define DATA_TYPE_RGBA_4444 0x12
116 #define DATA_TYPE_ARGB24_6666 0x18
117 #define DATA_TYPE_RGB24_888 0x16
118 #define DATA_TYPE_ARGB32_8888 0x17
119 #define DATA_TYPE_RGBA24_6666 0x15
120 #define DATA_TYPE_RGBA32_8888 0x19
121 #define DATA_TYPE_BGR16_565 0x0
122 #define DATA_TYPE_ABGR_1555 0x3
123 #define DATA_TYPE_ABGR_4444 0x4
124 #define DATA_TYPE_BGRA_5551 0x1
125 #define DATA_TYPE_BGRA_4444 0x2
126 #define DATA_TYPE_ABGR24_6666 0x8
127 #define DATA_TYPE_BGR24_888 0x6
128 #define DATA_TYPE_ABGR32_8888 0x7
129 #define DATA_TYPE_BGRA24_6666 0x5
130 #define DATA_TYPE_BGRA32_8888 0x9
132 #define DATA_TYPE_MV 0x3
134 /* VPDMA channel numbers, some are common between VIP/VPE and appear twice */
135 #define VPE_CHAN_NUM_LUMA1_IN 0
136 #define VPE_CHAN_NUM_CHROMA1_IN 1
137 #define VPE_CHAN_NUM_LUMA2_IN 2
138 #define VPE_CHAN_NUM_CHROMA2_IN 3
139 #define VPE_CHAN_NUM_LUMA3_IN 4
140 #define VPE_CHAN_NUM_CHROMA3_IN 5
141 #define VPE_CHAN_NUM_MV_IN 12
142 #define VPE_CHAN_NUM_MV_OUT 15
143 #define VIP1_CHAN_NUM_MULT_PORT_A_SRC0 38
144 #define VIP1_CHAN_NUM_MULT_ANC_A_SRC0 70
145 #define VPE_CHAN_NUM_LUMA_OUT 102
146 #define VPE_CHAN_NUM_CHROMA_OUT 103
147 #define VIP1_CHAN_NUM_PORT_A_LUMA 102
148 #define VIP1_CHAN_NUM_PORT_A_CHROMA 103
149 #define VPE_CHAN_NUM_RGB_OUT 106
150 #define VIP1_CHAN_NUM_PORT_A_RGB 106
151 #define VIP1_CHAN_NUM_PORT_B_RGB 107
153 * a VPDMA address data block payload for a configuration descriptor needs to
154 * have each sub block length as a multiple of 16 bytes. Therefore, the overall
155 * size of the payload also needs to be a multiple of 16 bytes. The sub block
156 * lengths should be ensured to be aligned by the VPDMA user.
158 #define VPDMA_ADB_SIZE_ALIGN 0x0f
161 * data transfer descriptor
166 u32 xfer_length_height;
172 u32 frame_width_height; /* inbound */
173 u32 desc_write_addr; /* outbound */
176 u32 start_h_v; /* inbound */
177 u32 max_width_height; /* outbound */
183 /* Data Transfer Descriptor specifics */
184 #define DTD_NO_NOTIFY 0
187 #define DTD_PKT_TYPE 0xa
189 #define DTD_DIR_OUT 1
191 /* type_ctl_stride */
192 #define DTD_DATA_TYPE_MASK 0x3f
193 #define DTD_DATA_TYPE_SHFT 26
194 #define DTD_NOTIFY_MASK 0x01
195 #define DTD_NOTIFY_SHFT 25
196 #define DTD_FIELD_MASK 0x01
197 #define DTD_FIELD_SHFT 24
198 #define DTD_1D_MASK 0x01
199 #define DTD_1D_SHFT 23
200 #define DTD_EVEN_LINE_SKIP_MASK 0x01
201 #define DTD_EVEN_LINE_SKIP_SHFT 20
202 #define DTD_ODD_LINE_SKIP_MASK 0x01
203 #define DTD_ODD_LINE_SKIP_SHFT 16
204 #define DTD_LINE_STRIDE_MASK 0xffff
205 #define DTD_LINE_STRIDE_SHFT 0
207 /* xfer_length_height */
208 #define DTD_LINE_LENGTH_MASK 0xffff
209 #define DTD_LINE_LENGTH_SHFT 16
210 #define DTD_XFER_HEIGHT_MASK 0xffff
211 #define DTD_XFER_HEIGHT_SHFT 0
214 #define DTD_PKT_TYPE_MASK 0x1f
215 #define DTD_PKT_TYPE_SHFT 27
216 #define DTD_MODE_MASK 0x01
217 #define DTD_MODE_SHFT 26
218 #define DTD_DIR_MASK 0x01
219 #define DTD_DIR_SHFT 25
220 #define DTD_CHAN_MASK 0x01ff
221 #define DTD_CHAN_SHFT 16
222 #define DTD_PRI_MASK 0x0f
223 #define DTD_PRI_SHFT 9
224 #define DTD_NEXT_CHAN_MASK 0x01ff
225 #define DTD_NEXT_CHAN_SHFT 0
227 /* frame_width_height */
228 #define DTD_FRAME_WIDTH_MASK 0xffff
229 #define DTD_FRAME_WIDTH_SHFT 16
230 #define DTD_FRAME_HEIGHT_MASK 0xffff
231 #define DTD_FRAME_HEIGHT_SHFT 0
234 #define DTD_H_START_MASK 0xffff
235 #define DTD_H_START_SHFT 16
236 #define DTD_V_START_MASK 0xffff
237 #define DTD_V_START_SHFT 0
239 #define DTD_DESC_START_MASK 0xffffffe0
240 #define DTD_DESC_START_SHIFT 5
241 #define DTD_WRITE_DESC_MASK 0x01
242 #define DTD_WRITE_DESC_SHIFT 2
243 #define DTD_DROP_DATA_MASK 0x01
244 #define DTD_DROP_DATA_SHIFT 1
245 #define DTD_USE_DESC_MASK 0x01
246 #define DTD_USE_DESC_SHIFT 0
248 /* max_width_height */
249 #define DTD_MAX_WIDTH_MASK 0x07
250 #define DTD_MAX_WIDTH_SHFT 4
251 #define DTD_MAX_HEIGHT_MASK 0x07
252 #define DTD_MAX_HEIGHT_SHFT 0
254 static inline u32 dtd_type_ctl_stride(int type, bool notify, int field,
255 bool one_d, bool even_line_skip, bool odd_line_skip,
258 return (type << DTD_DATA_TYPE_SHFT) | (notify << DTD_NOTIFY_SHFT) |
259 (field << DTD_FIELD_SHFT) | (one_d << DTD_1D_SHFT) |
260 (even_line_skip << DTD_EVEN_LINE_SKIP_SHFT) |
261 (odd_line_skip << DTD_ODD_LINE_SKIP_SHFT) |
265 static inline u32 dtd_xfer_length_height(int line_length, int xfer_height)
267 return (line_length << DTD_LINE_LENGTH_SHFT) | xfer_height;
270 static inline u32 dtd_pkt_ctl(bool mode, bool dir, int chan, int pri,
273 return (DTD_PKT_TYPE << DTD_PKT_TYPE_SHFT) | (mode << DTD_MODE_SHFT) |
274 (dir << DTD_DIR_SHFT) | (chan << DTD_CHAN_SHFT) |
275 (pri << DTD_PRI_SHFT) | next_chan;
278 static inline u32 dtd_frame_width_height(int width, int height)
280 return (width << DTD_FRAME_WIDTH_SHFT) | height;
283 static inline u32 dtd_desc_write_addr(unsigned int addr, bool write_desc,
284 bool drop_data, bool use_desc)
286 return (addr & DTD_DESC_START_MASK) |
287 (write_desc << DTD_WRITE_DESC_SHIFT) |
288 (drop_data << DTD_DROP_DATA_SHIFT) |
292 static inline u32 dtd_start_h_v(int h_start, int v_start)
294 return (h_start << DTD_H_START_SHFT) | v_start;
297 static inline u32 dtd_max_width_height(int max_width, int max_height)
299 return (max_width << DTD_MAX_WIDTH_SHFT) | max_height;
302 static inline int dtd_get_data_type(struct vpdma_dtd *dtd)
304 return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT;
307 static inline bool dtd_get_notify(struct vpdma_dtd *dtd)
309 return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK;
312 static inline int dtd_get_field(struct vpdma_dtd *dtd)
314 return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK;
317 static inline bool dtd_get_1d(struct vpdma_dtd *dtd)
319 return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK;
322 static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd)
324 return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT)
325 & DTD_EVEN_LINE_SKIP_MASK;
328 static inline bool dtd_get_odd_line_skip(struct vpdma_dtd *dtd)
330 return (dtd->type_ctl_stride >> DTD_ODD_LINE_SKIP_SHFT)
331 & DTD_ODD_LINE_SKIP_MASK;
334 static inline int dtd_get_line_stride(struct vpdma_dtd *dtd)
336 return dtd->type_ctl_stride & DTD_LINE_STRIDE_MASK;
339 static inline int dtd_get_line_length(struct vpdma_dtd *dtd)
341 return dtd->xfer_length_height >> DTD_LINE_LENGTH_SHFT;
344 static inline int dtd_get_xfer_height(struct vpdma_dtd *dtd)
346 return dtd->xfer_length_height & DTD_XFER_HEIGHT_MASK;
349 static inline int dtd_get_pkt_type(struct vpdma_dtd *dtd)
351 return dtd->pkt_ctl >> DTD_PKT_TYPE_SHFT;
354 static inline bool dtd_get_mode(struct vpdma_dtd *dtd)
356 return (dtd->pkt_ctl >> DTD_MODE_SHFT) & DTD_MODE_MASK;
359 static inline bool dtd_get_dir(struct vpdma_dtd *dtd)
361 return (dtd->pkt_ctl >> DTD_DIR_SHFT) & DTD_DIR_MASK;
364 static inline int dtd_get_chan(struct vpdma_dtd *dtd)
366 return (dtd->pkt_ctl >> DTD_CHAN_SHFT) & DTD_CHAN_MASK;
369 static inline int dtd_get_priority(struct vpdma_dtd *dtd)
371 return (dtd->pkt_ctl >> DTD_PRI_SHFT) & DTD_PRI_MASK;
374 static inline int dtd_get_next_chan(struct vpdma_dtd *dtd)
376 return (dtd->pkt_ctl >> DTD_NEXT_CHAN_SHFT) & DTD_NEXT_CHAN_MASK;
379 static inline int dtd_get_frame_width(struct vpdma_dtd *dtd)
381 return dtd->frame_width_height >> DTD_FRAME_WIDTH_SHFT;
384 static inline int dtd_get_frame_height(struct vpdma_dtd *dtd)
386 return dtd->frame_width_height & DTD_FRAME_HEIGHT_MASK;
389 static inline int dtd_get_desc_write_addr(struct vpdma_dtd *dtd)
391 return dtd->desc_write_addr & DTD_DESC_START_MASK;
394 static inline bool dtd_get_write_desc(struct vpdma_dtd *dtd)
396 return (dtd->desc_write_addr >> DTD_WRITE_DESC_SHIFT) &
400 static inline bool dtd_get_drop_data(struct vpdma_dtd *dtd)
402 return (dtd->desc_write_addr >> DTD_DROP_DATA_SHIFT) &
406 static inline bool dtd_get_use_desc(struct vpdma_dtd *dtd)
408 return dtd->desc_write_addr & DTD_USE_DESC_MASK;
411 static inline int dtd_get_h_start(struct vpdma_dtd *dtd)
413 return dtd->start_h_v >> DTD_H_START_SHFT;
416 static inline int dtd_get_v_start(struct vpdma_dtd *dtd)
418 return dtd->start_h_v & DTD_V_START_MASK;
421 static inline int dtd_get_max_width(struct vpdma_dtd *dtd)
423 return (dtd->max_width_height >> DTD_MAX_WIDTH_SHFT) &
427 static inline int dtd_get_max_height(struct vpdma_dtd *dtd)
429 return (dtd->max_width_height >> DTD_MAX_HEIGHT_SHFT) &
434 * configuration descriptor
438 u32 dest_addr_offset;
442 u32 block_len; /* in words */
446 u32 ctl_payload_len; /* in words */
449 /* Configuration descriptor specifics */
451 #define CFD_PKT_TYPE 0xb
454 #define CFD_INDIRECT 0
455 #define CFD_CLS_ADB 0
456 #define CFD_CLS_BLOCK 1
459 #define CFD__BLOCK_LEN_MASK 0xffff
460 #define CFD__BLOCK_LEN_SHFT 0
462 /* ctl_payload_len */
463 #define CFD_PKT_TYPE_MASK 0x1f
464 #define CFD_PKT_TYPE_SHFT 27
465 #define CFD_DIRECT_MASK 0x01
466 #define CFD_DIRECT_SHFT 26
467 #define CFD_CLASS_MASK 0x03
468 #define CFD_CLASS_SHFT 24
469 #define CFD_DEST_MASK 0xff
470 #define CFD_DEST_SHFT 16
471 #define CFD_PAYLOAD_LEN_MASK 0xffff
472 #define CFD_PAYLOAD_LEN_SHFT 0
474 static inline u32 cfd_pkt_payload_len(bool direct, int cls, int dest,
477 return (CFD_PKT_TYPE << CFD_PKT_TYPE_SHFT) |
478 (direct << CFD_DIRECT_SHFT) |
479 (cls << CFD_CLASS_SHFT) |
480 (dest << CFD_DEST_SHFT) |
484 static inline int cfd_get_pkt_type(struct vpdma_cfd *cfd)
486 return cfd->ctl_payload_len >> CFD_PKT_TYPE_SHFT;
489 static inline bool cfd_get_direct(struct vpdma_cfd *cfd)
491 return (cfd->ctl_payload_len >> CFD_DIRECT_SHFT) & CFD_DIRECT_MASK;
494 static inline bool cfd_get_class(struct vpdma_cfd *cfd)
496 return (cfd->ctl_payload_len >> CFD_CLASS_SHFT) & CFD_CLASS_MASK;
499 static inline int cfd_get_dest(struct vpdma_cfd *cfd)
501 return (cfd->ctl_payload_len >> CFD_DEST_SHFT) & CFD_DEST_MASK;
504 static inline int cfd_get_payload_len(struct vpdma_cfd *cfd)
506 return cfd->ctl_payload_len & CFD_PAYLOAD_LEN_MASK;
519 u32 pixel_line_count;
531 /* control descriptor types */
532 #define CTD_TYPE_SYNC_ON_CLIENT 0
533 #define CTD_TYPE_SYNC_ON_LIST 1
534 #define CTD_TYPE_SYNC_ON_EXT 2
535 #define CTD_TYPE_SYNC_ON_LM_TIMER 3
536 #define CTD_TYPE_SYNC_ON_CHANNEL 4
537 #define CTD_TYPE_CHNG_CLIENT_IRQ 5
538 #define CTD_TYPE_SEND_IRQ 6
539 #define CTD_TYPE_RELOAD_LIST 7
540 #define CTD_TYPE_ABORT_CHANNEL 8
542 #define CTD_PKT_TYPE 0xc
545 #define CTD_TIMER_VALUE_MASK 0xffff
546 #define CTD_TIMER_VALUE_SHFT 0
548 /* pixel_line_count */
549 #define CTD_PIXEL_COUNT_MASK 0xffff
550 #define CTD_PIXEL_COUNT_SHFT 16
551 #define CTD_LINE_COUNT_MASK 0xffff
552 #define CTD_LINE_COUNT_SHFT 0
555 #define CTD_LIST_SIZE_MASK 0xffff
556 #define CTD_LIST_SIZE_SHFT 0
559 #define CTD_EVENT_MASK 0x0f
560 #define CTD_EVENT_SHFT 0
563 #define CTD_FID2_MASK 0x03
564 #define CTD_FID2_SHFT 4
565 #define CTD_FID1_MASK 0x03
566 #define CTD_FID1_SHFT 2
567 #define CTD_FID0_MASK 0x03
568 #define CTD_FID0_SHFT 0
570 /* type_source_ctl */
571 #define CTD_PKT_TYPE_MASK 0x1f
572 #define CTD_PKT_TYPE_SHFT 27
573 #define CTD_SOURCE_MASK 0xff
574 #define CTD_SOURCE_SHFT 16
575 #define CTD_CONTROL_MASK 0x0f
576 #define CTD_CONTROL_SHFT 0
578 static inline u32 ctd_pixel_line_count(int pixel_count, int line_count)
580 return (pixel_count << CTD_PIXEL_COUNT_SHFT) | line_count;
583 static inline u32 ctd_set_fid_ctl(int fid0, int fid1, int fid2)
585 return (fid2 << CTD_FID2_SHFT) | (fid1 << CTD_FID1_SHFT) | fid0;
588 static inline u32 ctd_type_source_ctl(int source, int control)
590 return (CTD_PKT_TYPE << CTD_PKT_TYPE_SHFT) |
591 (source << CTD_SOURCE_SHFT) | control;
594 static inline u32 ctd_get_pixel_count(struct vpdma_ctd *ctd)
596 return ctd->pixel_line_count >> CTD_PIXEL_COUNT_SHFT;
599 static inline int ctd_get_line_count(struct vpdma_ctd *ctd)
601 return ctd->pixel_line_count & CTD_LINE_COUNT_MASK;
604 static inline int ctd_get_event(struct vpdma_ctd *ctd)
606 return ctd->event & CTD_EVENT_MASK;
609 static inline int ctd_get_fid2_ctl(struct vpdma_ctd *ctd)
611 return (ctd->fid_ctl >> CTD_FID2_SHFT) & CTD_FID2_MASK;
614 static inline int ctd_get_fid1_ctl(struct vpdma_ctd *ctd)
616 return (ctd->fid_ctl >> CTD_FID1_SHFT) & CTD_FID1_MASK;
619 static inline int ctd_get_fid0_ctl(struct vpdma_ctd *ctd)
621 return ctd->fid_ctl & CTD_FID2_MASK;
624 static inline int ctd_get_pkt_type(struct vpdma_ctd *ctd)
626 return ctd->type_source_ctl >> CTD_PKT_TYPE_SHFT;
629 static inline int ctd_get_source(struct vpdma_ctd *ctd)
631 return (ctd->type_source_ctl >> CTD_SOURCE_SHFT) & CTD_SOURCE_MASK;
634 static inline int ctd_get_ctl(struct vpdma_ctd *ctd)
636 return ctd->type_source_ctl & CTD_CONTROL_MASK;