1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TI CAL camera interface driver
5 * Copyright (c) 2015 Texas Instruments Inc.
7 * Benoit Parrot, <bparrot@ti.com>
10 #ifndef __TI_CAL_REGS_H
11 #define __TI_CAL_REGS_H
14 * struct cal_dev.flags possibilities
16 * DRA72_CAL_PRE_ES2_LDO_DISABLE:
17 * Errata i913: CSI2 LDO Needs to be disabled when module is powered on
19 * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
20 * LDOs on the device are disabled if CSI-2 module is powered on
21 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
22 * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
23 * current draw on the module supply in active mode.
25 * Errata does not apply when CSI-2 module is powered off
26 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
29 * Set the following register bits to disable the LDO,
30 * which is essentially CSI2 REG10 bit 6:
32 * Core 0: 0x4845 B828 = 0x0000 0040
33 * Core 1: 0x4845 B928 = 0x0000 0040
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
37 /* CAL register offsets */
39 #define CAL_HL_REVISION 0x0000
40 #define CAL_HL_HWINFO 0x0004
41 #define CAL_HL_SYSCONFIG 0x0010
42 #define CAL_HL_IRQ_EOI 0x001c
43 #define CAL_HL_IRQSTATUS_RAW(m) (0x20U + (m) * 0x10U)
44 #define CAL_HL_IRQSTATUS(m) (0x24U + (m) * 0x10U)
45 #define CAL_HL_IRQENABLE_SET(m) (0x28U + (m) * 0x10U)
46 #define CAL_HL_IRQENABLE_CLR(m) (0x2cU + (m) * 0x10U)
47 #define CAL_PIX_PROC(m) (0xc0U + (m) * 0x4U)
48 #define CAL_CTRL 0x100
49 #define CAL_CTRL1 0x104
50 #define CAL_LINE_NUMBER_EVT 0x108
51 #define CAL_VPORT_CTRL1 0x120
52 #define CAL_VPORT_CTRL2 0x124
53 #define CAL_BYS_CTRL1 0x130
54 #define CAL_BYS_CTRL2 0x134
55 #define CAL_RD_DMA_CTRL 0x140
56 #define CAL_RD_DMA_PIX_ADDR 0x144
57 #define CAL_RD_DMA_PIX_OFST 0x148
58 #define CAL_RD_DMA_XSIZE 0x14c
59 #define CAL_RD_DMA_YSIZE 0x150
60 #define CAL_RD_DMA_INIT_ADDR 0x154
61 #define CAL_RD_DMA_INIT_OFST 0x168
62 #define CAL_RD_DMA_CTRL2 0x16c
63 #define CAL_WR_DMA_CTRL(m) (0x200U + (m) * 0x10U)
64 #define CAL_WR_DMA_ADDR(m) (0x204U + (m) * 0x10U)
65 #define CAL_WR_DMA_OFST(m) (0x208U + (m) * 0x10U)
66 #define CAL_WR_DMA_XSIZE(m) (0x20cU + (m) * 0x10U)
67 #define CAL_CSI2_PPI_CTRL(m) (0x300U + (m) * 0x80U)
68 #define CAL_CSI2_COMPLEXIO_CFG(m) (0x304U + (m) * 0x80U)
69 #define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) (0x308U + (m) * 0x80U)
70 #define CAL_CSI2_SHORT_PACKET(m) (0x30cU + (m) * 0x80U)
71 #define CAL_CSI2_COMPLEXIO_IRQENABLE(m) (0x310U + (m) * 0x80U)
72 #define CAL_CSI2_TIMING(m) (0x314U + (m) * 0x80U)
73 #define CAL_CSI2_VC_IRQENABLE(m) (0x318U + (m) * 0x80U)
74 #define CAL_CSI2_VC_IRQSTATUS(m) (0x328U + (m) * 0x80U)
75 #define CAL_CSI2_CTX0(m) (0x330U + (m) * 0x80U)
76 #define CAL_CSI2_CTX1(m) (0x334U + (m) * 0x80U)
77 #define CAL_CSI2_CTX2(m) (0x338U + (m) * 0x80U)
78 #define CAL_CSI2_CTX3(m) (0x33cU + (m) * 0x80U)
79 #define CAL_CSI2_CTX4(m) (0x340U + (m) * 0x80U)
80 #define CAL_CSI2_CTX5(m) (0x344U + (m) * 0x80U)
81 #define CAL_CSI2_CTX6(m) (0x348U + (m) * 0x80U)
82 #define CAL_CSI2_CTX7(m) (0x34cU + (m) * 0x80U)
83 #define CAL_CSI2_STATUS0(m) (0x350U + (m) * 0x80U)
84 #define CAL_CSI2_STATUS1(m) (0x354U + (m) * 0x80U)
85 #define CAL_CSI2_STATUS2(m) (0x358U + (m) * 0x80U)
86 #define CAL_CSI2_STATUS3(m) (0x35cU + (m) * 0x80U)
87 #define CAL_CSI2_STATUS4(m) (0x360U + (m) * 0x80U)
88 #define CAL_CSI2_STATUS5(m) (0x364U + (m) * 0x80U)
89 #define CAL_CSI2_STATUS6(m) (0x368U + (m) * 0x80U)
90 #define CAL_CSI2_STATUS7(m) (0x36cU + (m) * 0x80U)
92 /* CAL CSI2 PHY register offsets */
93 #define CAL_CSI2_PHY_REG0 0x000
94 #define CAL_CSI2_PHY_REG1 0x004
95 #define CAL_CSI2_PHY_REG2 0x008
96 #define CAL_CSI2_PHY_REG10 0x028
98 /* CAL Control Module Core Camerrx Control register offsets */
99 #define CM_CTRL_CORE_CAMERRX_CONTROL 0x000
101 /*********************************************************************
102 * Field Definition Macros
103 *********************************************************************/
105 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
106 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
107 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
108 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
109 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
110 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
111 #define CAL_HL_REVISION_SCHEME_H08 1
112 #define CAL_HL_REVISION_SCHEME_LEGACY 0
114 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
115 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
116 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
117 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
118 #define CAL_HL_HWINFO_VFIFO_MASK GENMASK(22, 19)
119 #define CAL_HL_HWINFO_NCPORT_MASK GENMASK(27, 23)
120 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
121 #define CAL_HL_HWINFO_NPPI_CTXS1_MASK GENMASK(31, 30)
122 #define CAL_HL_HWINFO_NPPI_CONTEXTS_ZERO 0
123 #define CAL_HL_HWINFO_NPPI_CONTEXTS_FOUR 1
124 #define CAL_HL_HWINFO_NPPI_CONTEXTS_EIGHT 2
125 #define CAL_HL_HWINFO_NPPI_CONTEXTS_RESERVED 3
127 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
128 #define CAL_HL_SYSCONFIG_SOFTRESET_DONE 0x0
129 #define CAL_HL_SYSCONFIG_SOFTRESET_PENDING 0x1
130 #define CAL_HL_SYSCONFIG_SOFTRESET_NOACTION 0x0
131 #define CAL_HL_SYSCONFIG_SOFTRESET_RESET 0x1
132 #define CAL_HL_SYSCONFIG_IDLE_MASK GENMASK(3, 2)
133 #define CAL_HL_SYSCONFIG_IDLEMODE_FORCE 0
134 #define CAL_HL_SYSCONFIG_IDLEMODE_NO 1
135 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART1 2
136 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART2 3
138 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
139 #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0 0
140 #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0 0
142 #define CAL_HL_IRQ_MASK(m) BIT(m)
144 #define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6)
146 #define CAL_HL_IRQ_CIO_MASK(i) BIT(16 + (i) * 8)
147 #define CAL_HL_IRQ_VC_MASK(i) BIT(17 + (i) * 8)
149 #define CAL_PIX_PROC_EN_MASK BIT(0)
150 #define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1)
151 #define CAL_PIX_PROC_EXTRACT_B6 0x0
152 #define CAL_PIX_PROC_EXTRACT_B7 0x1
153 #define CAL_PIX_PROC_EXTRACT_B8 0x2
154 #define CAL_PIX_PROC_EXTRACT_B10 0x3
155 #define CAL_PIX_PROC_EXTRACT_B10_MIPI 0x4
156 #define CAL_PIX_PROC_EXTRACT_B12 0x5
157 #define CAL_PIX_PROC_EXTRACT_B12_MIPI 0x6
158 #define CAL_PIX_PROC_EXTRACT_B14 0x7
159 #define CAL_PIX_PROC_EXTRACT_B14_MIPI 0x8
160 #define CAL_PIX_PROC_EXTRACT_B16_BE 0x9
161 #define CAL_PIX_PROC_EXTRACT_B16_LE 0xa
162 #define CAL_PIX_PROC_DPCMD_MASK GENMASK(9, 5)
163 #define CAL_PIX_PROC_DPCMD_BYPASS 0x0
164 #define CAL_PIX_PROC_DPCMD_DPCM_10_8_1 0x2
165 #define CAL_PIX_PROC_DPCMD_DPCM_12_8_1 0x8
166 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_1 0x4
167 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_2 0x5
168 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_1 0x6
169 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_2 0x7
170 #define CAL_PIX_PROC_DPCMD_DPCM_12_7_1 0xa
171 #define CAL_PIX_PROC_DPCMD_DPCM_12_6_1 0xc
172 #define CAL_PIX_PROC_DPCMD_DPCM_14_10 0xe
173 #define CAL_PIX_PROC_DPCMD_DPCM_14_8_1 0x10
174 #define CAL_PIX_PROC_DPCMD_DPCM_16_12_1 0x12
175 #define CAL_PIX_PROC_DPCMD_DPCM_16_10_1 0x14
176 #define CAL_PIX_PROC_DPCMD_DPCM_16_8_1 0x16
177 #define CAL_PIX_PROC_DPCME_MASK GENMASK(15, 11)
178 #define CAL_PIX_PROC_DPCME_BYPASS 0x0
179 #define CAL_PIX_PROC_DPCME_DPCM_10_8_1 0x2
180 #define CAL_PIX_PROC_DPCME_DPCM_12_8_1 0x8
181 #define CAL_PIX_PROC_DPCME_DPCM_14_10 0xe
182 #define CAL_PIX_PROC_DPCME_DPCM_14_8_1 0x10
183 #define CAL_PIX_PROC_DPCME_DPCM_16_12_1 0x12
184 #define CAL_PIX_PROC_DPCME_DPCM_16_10_1 0x14
185 #define CAL_PIX_PROC_DPCME_DPCM_16_8_1 0x16
186 #define CAL_PIX_PROC_PACK_MASK GENMASK(18, 16)
187 #define CAL_PIX_PROC_PACK_B8 0x0
188 #define CAL_PIX_PROC_PACK_B10_MIPI 0x2
189 #define CAL_PIX_PROC_PACK_B12 0x3
190 #define CAL_PIX_PROC_PACK_B12_MIPI 0x4
191 #define CAL_PIX_PROC_PACK_B16 0x5
192 #define CAL_PIX_PROC_PACK_ARGB 0x6
193 #define CAL_PIX_PROC_CPORT_MASK GENMASK(23, 19)
195 #define CAL_CTRL_POSTED_WRITES_MASK BIT(0)
196 #define CAL_CTRL_POSTED_WRITES_NONPOSTED 0
197 #define CAL_CTRL_POSTED_WRITES 1
198 #define CAL_CTRL_TAGCNT_MASK GENMASK(4, 1)
199 #define CAL_CTRL_BURSTSIZE_MASK GENMASK(6, 5)
200 #define CAL_CTRL_BURSTSIZE_BURST16 0x0
201 #define CAL_CTRL_BURSTSIZE_BURST32 0x1
202 #define CAL_CTRL_BURSTSIZE_BURST64 0x2
203 #define CAL_CTRL_BURSTSIZE_BURST128 0x3
204 #define CAL_CTRL_LL_FORCE_STATE_MASK GENMASK(12, 7)
205 #define CAL_CTRL_MFLAGL_MASK GENMASK(20, 13)
206 #define CAL_CTRL_PWRSCPCLK_MASK BIT(21)
207 #define CAL_CTRL_PWRSCPCLK_AUTO 0
208 #define CAL_CTRL_PWRSCPCLK_FORCE 1
209 #define CAL_CTRL_RD_DMA_STALL_MASK BIT(22)
210 #define CAL_CTRL_MFLAGH_MASK GENMASK(31, 24)
212 #define CAL_CTRL1_PPI_GROUPING_MASK GENMASK(1, 0)
213 #define CAL_CTRL1_PPI_GROUPING_DISABLED 0
214 #define CAL_CTRL1_PPI_GROUPING_RESERVED 1
215 #define CAL_CTRL1_PPI_GROUPING_0 2
216 #define CAL_CTRL1_PPI_GROUPING_1 3
217 #define CAL_CTRL1_INTERLEAVE01_MASK GENMASK(3, 2)
218 #define CAL_CTRL1_INTERLEAVE01_DISABLED 0
219 #define CAL_CTRL1_INTERLEAVE01_PIX1 1
220 #define CAL_CTRL1_INTERLEAVE01_PIX4 2
221 #define CAL_CTRL1_INTERLEAVE01_RESERVED 3
222 #define CAL_CTRL1_INTERLEAVE23_MASK GENMASK(5, 4)
223 #define CAL_CTRL1_INTERLEAVE23_DISABLED 0
224 #define CAL_CTRL1_INTERLEAVE23_PIX1 1
225 #define CAL_CTRL1_INTERLEAVE23_PIX4 2
226 #define CAL_CTRL1_INTERLEAVE23_RESERVED 3
228 #define CAL_LINE_NUMBER_EVT_CPORT_MASK GENMASK(4, 0)
229 #define CAL_LINE_NUMBER_EVT_MASK GENMASK(29, 16)
231 #define CAL_VPORT_CTRL1_PCLK_MASK GENMASK(16, 0)
232 #define CAL_VPORT_CTRL1_XBLK_MASK GENMASK(24, 17)
233 #define CAL_VPORT_CTRL1_YBLK_MASK GENMASK(30, 25)
234 #define CAL_VPORT_CTRL1_WIDTH_MASK BIT(31)
235 #define CAL_VPORT_CTRL1_WIDTH_ONE 0
236 #define CAL_VPORT_CTRL1_WIDTH_TWO 1
238 #define CAL_VPORT_CTRL2_CPORT_MASK GENMASK(4, 0)
239 #define CAL_VPORT_CTRL2_FREERUNNING_MASK BIT(15)
240 #define CAL_VPORT_CTRL2_FREERUNNING_GATED 0
241 #define CAL_VPORT_CTRL2_FREERUNNING_FREE 1
242 #define CAL_VPORT_CTRL2_FS_RESETS_MASK BIT(16)
243 #define CAL_VPORT_CTRL2_FS_RESETS_NO 0
244 #define CAL_VPORT_CTRL2_FS_RESETS_YES 1
245 #define CAL_VPORT_CTRL2_FSM_RESET_MASK BIT(17)
246 #define CAL_VPORT_CTRL2_FSM_RESET_NOEFFECT 0
247 #define CAL_VPORT_CTRL2_FSM_RESET 1
248 #define CAL_VPORT_CTRL2_RDY_THR_MASK GENMASK(31, 18)
250 #define CAL_BYS_CTRL1_PCLK_MASK GENMASK(16, 0)
251 #define CAL_BYS_CTRL1_XBLK_MASK GENMASK(24, 17)
252 #define CAL_BYS_CTRL1_YBLK_MASK GENMASK(30, 25)
253 #define CAL_BYS_CTRL1_BYSINEN_MASK BIT(31)
255 #define CAL_BYS_CTRL2_CPORTIN_MASK GENMASK(4, 0)
256 #define CAL_BYS_CTRL2_CPORTOUT_MASK GENMASK(9, 5)
257 #define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK BIT(10)
258 #define CAL_BYS_CTRL2_DUPLICATEDDATA_NO 0
259 #define CAL_BYS_CTRL2_DUPLICATEDDATA_YES 1
260 #define CAL_BYS_CTRL2_FREERUNNING_MASK BIT(11)
261 #define CAL_BYS_CTRL2_FREERUNNING_NO 0
262 #define CAL_BYS_CTRL2_FREERUNNING_YES 1
264 #define CAL_RD_DMA_CTRL_GO_MASK BIT(0)
265 #define CAL_RD_DMA_CTRL_GO_DIS 0
266 #define CAL_RD_DMA_CTRL_GO_EN 1
267 #define CAL_RD_DMA_CTRL_GO_IDLE 0
268 #define CAL_RD_DMA_CTRL_GO_BUSY 1
269 #define CAL_RD_DMA_CTRL_INIT_MASK BIT(1)
270 #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK GENMASK(10, 2)
271 #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK GENMASK(14, 11)
272 #define CAL_RD_DMA_CTRL_PCLK_MASK GENMASK(31, 15)
274 #define CAL_RD_DMA_PIX_ADDR_MASK GENMASK(31, 3)
276 #define CAL_RD_DMA_PIX_OFST_MASK GENMASK(31, 4)
278 #define CAL_RD_DMA_XSIZE_MASK GENMASK(31, 19)
280 #define CAL_RD_DMA_YSIZE_MASK GENMASK(29, 16)
282 #define CAL_RD_DMA_INIT_ADDR_MASK GENMASK(31, 3)
284 #define CAL_RD_DMA_INIT_OFST_MASK GENMASK(31, 3)
286 #define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK GENMASK(2, 0)
287 #define CAL_RD_DMA_CTRL2_CIRC_MODE_DIS 0
288 #define CAL_RD_DMA_CTRL2_CIRC_MODE_ONE 1
289 #define CAL_RD_DMA_CTRL2_CIRC_MODE_FOUR 2
290 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTEEN 3
291 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTYFOUR 4
292 #define CAL_RD_DMA_CTRL2_CIRC_MODE_RESERVED 5
293 #define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK BIT(3)
294 #define CAL_RD_DMA_CTRL2_PATTERN_MASK GENMASK(5, 4)
295 #define CAL_RD_DMA_CTRL2_PATTERN_LINEAR 0
296 #define CAL_RD_DMA_CTRL2_PATTERN_YUV420 1
297 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP2 2
298 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP4 3
299 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK BIT(6)
300 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_FREERUNNING 0
301 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_WAITFORBYSOUT 1
302 #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK GENMASK(29, 16)
304 #define CAL_WR_DMA_CTRL_MODE_MASK GENMASK(2, 0)
305 #define CAL_WR_DMA_CTRL_MODE_DIS 0
306 #define CAL_WR_DMA_CTRL_MODE_SHD 1
307 #define CAL_WR_DMA_CTRL_MODE_CNT 2
308 #define CAL_WR_DMA_CTRL_MODE_CNT_INIT 3
309 #define CAL_WR_DMA_CTRL_MODE_CONST 4
310 #define CAL_WR_DMA_CTRL_MODE_RESERVED 5
311 #define CAL_WR_DMA_CTRL_PATTERN_MASK GENMASK(4, 3)
312 #define CAL_WR_DMA_CTRL_PATTERN_LINEAR 0
313 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP2 2
314 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP4 3
315 #define CAL_WR_DMA_CTRL_PATTERN_RESERVED 1
316 #define CAL_WR_DMA_CTRL_ICM_PSTART_MASK BIT(5)
317 #define CAL_WR_DMA_CTRL_DTAG_MASK GENMASK(8, 6)
318 #define CAL_WR_DMA_CTRL_DTAG_ATT_HDR 0
319 #define CAL_WR_DMA_CTRL_DTAG_ATT_DAT 1
320 #define CAL_WR_DMA_CTRL_DTAG 2
321 #define CAL_WR_DMA_CTRL_DTAG_PIX_HDR 3
322 #define CAL_WR_DMA_CTRL_DTAG_PIX_DAT 4
323 #define CAL_WR_DMA_CTRL_DTAG_D5 5
324 #define CAL_WR_DMA_CTRL_DTAG_D6 6
325 #define CAL_WR_DMA_CTRL_DTAG_D7 7
326 #define CAL_WR_DMA_CTRL_CPORT_MASK GENMASK(13, 9)
327 #define CAL_WR_DMA_CTRL_STALL_RD_MASK BIT(14)
328 #define CAL_WR_DMA_CTRL_YSIZE_MASK GENMASK(31, 18)
330 #define CAL_WR_DMA_ADDR_MASK GENMASK(31, 4)
332 #define CAL_WR_DMA_OFST_MASK GENMASK(18, 4)
333 #define CAL_WR_DMA_OFST_CIRC_MODE_MASK GENMASK(23, 22)
334 #define CAL_WR_DMA_OFST_CIRC_MODE_ONE 1
335 #define CAL_WR_DMA_OFST_CIRC_MODE_FOUR 2
336 #define CAL_WR_DMA_OFST_CIRC_MODE_SIXTYFOUR 3
337 #define CAL_WR_DMA_OFST_CIRC_MODE_DISABLED 0
338 #define CAL_WR_DMA_OFST_CIRC_SIZE_MASK GENMASK(31, 24)
340 #define CAL_WR_DMA_XSIZE_XSKIP_MASK GENMASK(15, 3)
341 #define CAL_WR_DMA_XSIZE_MASK GENMASK(31, 19)
343 #define CAL_CSI2_PPI_CTRL_IF_EN_MASK BIT(0)
344 #define CAL_CSI2_PPI_CTRL_ECC_EN_MASK BIT(2)
345 #define CAL_CSI2_PPI_CTRL_FRAME_MASK BIT(3)
346 #define CAL_CSI2_PPI_CTRL_FRAME_IMMEDIATE 0
347 #define CAL_CSI2_PPI_CTRL_FRAME 1
349 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK GENMASK(2, 0)
350 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_5 5
351 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_4 4
352 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_3 3
353 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_2 2
354 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_1 1
355 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_NOT_USED 0
356 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK BIT(3)
357 #define CAL_CSI2_COMPLEXIO_CFG_POL_PLUSMINUS 0
358 #define CAL_CSI2_COMPLEXIO_CFG_POL_MINUSPLUS 1
359 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK GENMASK(6, 4)
360 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK BIT(7)
361 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK GENMASK(10, 8)
362 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK BIT(11)
363 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK GENMASK(14, 12)
364 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK BIT(15)
365 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK GENMASK(18, 16)
366 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK BIT(19)
367 #define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK BIT(24)
368 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK GENMASK(26, 25)
369 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF 0
370 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON 1
371 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ULP 2
372 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK GENMASK(28, 27)
373 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF 0
374 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON 1
375 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ULP 2
376 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK BIT(29)
377 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED 1
378 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING 0
379 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK BIT(30)
380 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL 0
381 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL 1
383 #define CAL_CSI2_SHORT_PACKET_MASK GENMASK(23, 0)
385 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK BIT(0)
386 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK BIT(1)
387 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK BIT(2)
388 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK BIT(3)
389 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK BIT(4)
390 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK BIT(5)
391 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK BIT(6)
392 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK BIT(7)
393 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK BIT(8)
394 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK BIT(9)
395 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK BIT(10)
396 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK BIT(11)
397 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK BIT(12)
398 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK BIT(13)
399 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK BIT(14)
400 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK BIT(15)
401 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK BIT(16)
402 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK BIT(17)
403 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK BIT(18)
404 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK BIT(19)
405 #define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK GENMASK(19, 0)
406 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK BIT(20)
407 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK BIT(21)
408 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK BIT(22)
409 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK BIT(23)
410 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK BIT(24)
411 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK BIT(25)
412 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK BIT(26)
413 #define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK BIT(27)
414 #define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK BIT(28)
415 #define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK BIT(30)
417 #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK GENMASK(12, 0)
418 #define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK BIT(13)
419 #define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK BIT(14)
420 #define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK BIT(15)
422 #define CAL_CSI2_VC_IRQ_FS_IRQ_0_MASK BIT(0)
423 #define CAL_CSI2_VC_IRQ_FE_IRQ_0_MASK BIT(1)
424 #define CAL_CSI2_VC_IRQ_LS_IRQ_0_MASK BIT(2)
425 #define CAL_CSI2_VC_IRQ_LE_IRQ_0_MASK BIT(3)
426 #define CAL_CSI2_VC_IRQ_CS_IRQ_0_MASK BIT(4)
427 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_0_MASK BIT(5)
428 #define CAL_CSI2_VC_IRQ_FS_IRQ_1_MASK BIT(8)
429 #define CAL_CSI2_VC_IRQ_FE_IRQ_1_MASK BIT(9)
430 #define CAL_CSI2_VC_IRQ_LS_IRQ_1_MASK BIT(10)
431 #define CAL_CSI2_VC_IRQ_LE_IRQ_1_MASK BIT(11)
432 #define CAL_CSI2_VC_IRQ_CS_IRQ_1_MASK BIT(12)
433 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_1_MASK BIT(13)
434 #define CAL_CSI2_VC_IRQ_FS_IRQ_2_MASK BIT(16)
435 #define CAL_CSI2_VC_IRQ_FE_IRQ_2_MASK BIT(17)
436 #define CAL_CSI2_VC_IRQ_LS_IRQ_2_MASK BIT(18)
437 #define CAL_CSI2_VC_IRQ_LE_IRQ_2_MASK BIT(19)
438 #define CAL_CSI2_VC_IRQ_CS_IRQ_2_MASK BIT(20)
439 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_2_MASK BIT(21)
440 #define CAL_CSI2_VC_IRQ_FS_IRQ_3_MASK BIT(24)
441 #define CAL_CSI2_VC_IRQ_FE_IRQ_3_MASK BIT(25)
442 #define CAL_CSI2_VC_IRQ_LS_IRQ_3_MASK BIT(26)
443 #define CAL_CSI2_VC_IRQ_LE_IRQ_3_MASK BIT(27)
444 #define CAL_CSI2_VC_IRQ_CS_IRQ_3_MASK BIT(28)
445 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_3_MASK BIT(29)
447 #define CAL_CSI2_CTX_DT_MASK GENMASK(5, 0)
448 #define CAL_CSI2_CTX_VC_MASK GENMASK(7, 6)
449 #define CAL_CSI2_CTX_CPORT_MASK GENMASK(12, 8)
450 #define CAL_CSI2_CTX_ATT_MASK BIT(13)
451 #define CAL_CSI2_CTX_ATT_PIX 0
452 #define CAL_CSI2_CTX_ATT 1
453 #define CAL_CSI2_CTX_PACK_MODE_MASK BIT(14)
454 #define CAL_CSI2_CTX_PACK_MODE_LINE 0
455 #define CAL_CSI2_CTX_PACK_MODE_FRAME 1
456 #define CAL_CSI2_CTX_LINES_MASK GENMASK(29, 16)
458 #define CAL_CSI2_STATUS_FRAME_MASK GENMASK(15, 0)
460 #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK GENMASK(7, 0)
461 #define CAL_CSI2_PHY_REG0_THS_TERM_MASK GENMASK(15, 8)
462 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK BIT(24)
463 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE 1
464 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_ENABLE 0
466 #define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK GENMASK(7, 0)
467 #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK GENMASK(9, 8)
468 #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK GENMASK(17, 10)
469 #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK GENMASK(24, 18)
470 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK BIT(25)
471 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_ERROR 1
472 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS 0
473 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK GENMASK(29, 28)
475 #define CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK BIT(6)
477 #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK GENMASK(23, 0)
478 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK GENMASK(25, 24)
479 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK GENMASK(27, 26)
480 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK GENMASK(29, 28)
481 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK GENMASK(31, 30)
483 #define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK BIT(0)
484 #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK GENMASK(2, 1)
485 #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK GENMASK(4, 3)
486 #define CM_CAMERRX_CTRL_CSI1_MODE_MASK BIT(5)
487 #define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK BIT(10)
488 #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK GENMASK(12, 11)
489 #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK GENMASK(16, 13)
490 #define CM_CAMERRX_CTRL_CSI0_MODE_MASK BIT(17)