1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Camera Access Layer (CAL) - Driver
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
8 * Benoit Parrot <bparrot@ti.com>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
23 #include <media/media-device.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-common.h>
26 #include <media/v4l2-device.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
33 MODULE_DESCRIPTION("TI CAL driver");
34 MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>");
35 MODULE_LICENSE("GPL v2");
36 MODULE_VERSION("0.1.0");
38 int cal_video_nr = -1;
39 module_param_named(video_nr, cal_video_nr, uint, 0644);
40 MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect");
42 unsigned int cal_debug;
43 module_param_named(debug, cal_debug, uint, 0644);
44 MODULE_PARM_DESC(debug, "activates debug info");
46 /* ------------------------------------------------------------------
48 * ------------------------------------------------------------------
51 static const struct cal_camerarx_data dra72x_cal_camerarx[] = {
54 [F_CTRLCLKEN] = { 10, 10 },
55 [F_CAMMODE] = { 11, 12 },
56 [F_LANEENABLE] = { 13, 16 },
57 [F_CSI_MODE] = { 17, 17 },
63 [F_CTRLCLKEN] = { 0, 0 },
64 [F_CAMMODE] = { 1, 2 },
65 [F_LANEENABLE] = { 3, 4 },
66 [F_CSI_MODE] = { 5, 5 },
72 static const struct cal_data dra72x_cal_data = {
73 .camerarx = dra72x_cal_camerarx,
74 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
77 static const struct cal_data dra72x_es1_cal_data = {
78 .camerarx = dra72x_cal_camerarx,
79 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
80 .flags = DRA72_CAL_PRE_ES2_LDO_DISABLE,
83 static const struct cal_camerarx_data dra76x_cal_csi_phy[] = {
86 [F_CTRLCLKEN] = { 8, 8 },
87 [F_CAMMODE] = { 9, 10 },
88 [F_CSI_MODE] = { 11, 11 },
89 [F_LANEENABLE] = { 27, 31 },
95 [F_CTRLCLKEN] = { 0, 0 },
96 [F_CAMMODE] = { 1, 2 },
97 [F_CSI_MODE] = { 3, 3 },
98 [F_LANEENABLE] = { 24, 26 },
104 static const struct cal_data dra76x_cal_data = {
105 .camerarx = dra76x_cal_csi_phy,
106 .num_csi2_phy = ARRAY_SIZE(dra76x_cal_csi_phy),
109 static const struct cal_camerarx_data am654_cal_csi_phy[] = {
112 [F_CTRLCLKEN] = { 15, 15 },
113 [F_CAMMODE] = { 24, 25 },
114 [F_LANEENABLE] = { 0, 4 },
120 static const struct cal_data am654_cal_data = {
121 .camerarx = am654_cal_csi_phy,
122 .num_csi2_phy = ARRAY_SIZE(am654_cal_csi_phy),
125 /* ------------------------------------------------------------------
126 * I/O Register Accessors
127 * ------------------------------------------------------------------
130 void cal_quickdump_regs(struct cal_dev *cal)
134 cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start);
135 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
136 (__force const void *)cal->base,
137 resource_size(cal->res), false);
139 for (i = 0; i < ARRAY_SIZE(cal->phy); ++i) {
140 struct cal_camerarx *phy = cal->phy[i];
145 cal_info(cal, "CSI2 Core %u Registers @ %pa:\n", i,
147 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
148 (__force const void *)phy->base,
149 resource_size(phy->res),
154 /* ------------------------------------------------------------------
156 * ------------------------------------------------------------------
159 void cal_ctx_csi2_config(struct cal_ctx *ctx)
163 val = cal_read(ctx->cal, CAL_CSI2_CTX0(ctx->index));
164 cal_set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK);
166 * DT type: MIPI CSI-2 Specs
167 * 0x1: All - DT filter is disabled
168 * 0x24: RGB888 1 pixel = 3 bytes
169 * 0x2B: RAW10 4 pixels = 5 bytes
170 * 0x2A: RAW8 1 pixel = 1 byte
171 * 0x1E: YUV422 2 pixels = 4 bytes
173 cal_set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK);
174 cal_set_field(&val, 0, CAL_CSI2_CTX_VC_MASK);
175 cal_set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK);
176 cal_set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
177 cal_set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
178 CAL_CSI2_CTX_PACK_MODE_MASK);
179 cal_write(ctx->cal, CAL_CSI2_CTX0(ctx->index), val);
180 ctx_dbg(3, ctx, "CAL_CSI2_CTX0(%d) = 0x%08x\n", ctx->index,
181 cal_read(ctx->cal, CAL_CSI2_CTX0(ctx->index)));
184 void cal_ctx_pix_proc_config(struct cal_ctx *ctx)
186 u32 val, extract, pack;
188 switch (ctx->fmt->bpp) {
190 extract = CAL_PIX_PROC_EXTRACT_B8;
191 pack = CAL_PIX_PROC_PACK_B8;
194 extract = CAL_PIX_PROC_EXTRACT_B10_MIPI;
195 pack = CAL_PIX_PROC_PACK_B16;
198 extract = CAL_PIX_PROC_EXTRACT_B12_MIPI;
199 pack = CAL_PIX_PROC_PACK_B16;
202 extract = CAL_PIX_PROC_EXTRACT_B16_LE;
203 pack = CAL_PIX_PROC_PACK_B16;
207 * If you see this warning then it means that you added
208 * some new entry in the cal_formats[] array with a different
209 * bit per pixel values then the one supported below.
210 * Either add support for the new bpp value below or adjust
211 * the new entry to use one of the value below.
213 * Instead of failing here just use 8 bpp as a default.
215 dev_warn_once(ctx->cal->dev,
216 "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n",
217 __FILE__, __LINE__, __func__, ctx->fmt->bpp);
218 extract = CAL_PIX_PROC_EXTRACT_B8;
219 pack = CAL_PIX_PROC_PACK_B8;
223 val = cal_read(ctx->cal, CAL_PIX_PROC(ctx->index));
224 cal_set_field(&val, extract, CAL_PIX_PROC_EXTRACT_MASK);
225 cal_set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);
226 cal_set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
227 cal_set_field(&val, pack, CAL_PIX_PROC_PACK_MASK);
228 cal_set_field(&val, ctx->cport, CAL_PIX_PROC_CPORT_MASK);
229 cal_set_field(&val, 1, CAL_PIX_PROC_EN_MASK);
230 cal_write(ctx->cal, CAL_PIX_PROC(ctx->index), val);
231 ctx_dbg(3, ctx, "CAL_PIX_PROC(%d) = 0x%08x\n", ctx->index,
232 cal_read(ctx->cal, CAL_PIX_PROC(ctx->index)));
235 void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width,
240 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index));
241 cal_set_field(&val, ctx->cport, CAL_WR_DMA_CTRL_CPORT_MASK);
242 cal_set_field(&val, height, CAL_WR_DMA_CTRL_YSIZE_MASK);
243 cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
244 CAL_WR_DMA_CTRL_DTAG_MASK);
245 cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
246 CAL_WR_DMA_CTRL_MODE_MASK);
247 cal_set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
248 CAL_WR_DMA_CTRL_PATTERN_MASK);
249 cal_set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK);
250 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->index), val);
251 ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->index,
252 cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index)));
255 * width/16 not sure but giving it a whirl.
256 * zero does not work right
258 cal_write_field(ctx->cal,
259 CAL_WR_DMA_OFST(ctx->index),
261 CAL_WR_DMA_OFST_MASK);
262 ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->index,
263 cal_read(ctx->cal, CAL_WR_DMA_OFST(ctx->index)));
265 val = cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index));
266 /* 64 bit word means no skipping */
267 cal_set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);
269 * (width*8)/64 this should be size of an entire line
270 * in 64bit word but 0 means all data until the end
271 * is detected automagically
273 cal_set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK);
274 cal_write(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index), val);
275 ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->index,
276 cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index)));
278 val = cal_read(ctx->cal, CAL_CTRL);
279 cal_set_field(&val, CAL_CTRL_BURSTSIZE_BURST128,
280 CAL_CTRL_BURSTSIZE_MASK);
281 cal_set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK);
282 cal_set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,
283 CAL_CTRL_POSTED_WRITES_MASK);
284 cal_set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK);
285 cal_set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK);
286 cal_write(ctx->cal, CAL_CTRL, val);
287 ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", cal_read(ctx->cal, CAL_CTRL));
290 void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
292 cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->index), dmaaddr);
295 /* ------------------------------------------------------------------
297 * ------------------------------------------------------------------
300 static inline void cal_schedule_next_buffer(struct cal_ctx *ctx)
302 struct cal_dmaqueue *dma_q = &ctx->vidq;
303 struct cal_buffer *buf;
306 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
308 list_del(&buf->list);
310 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
311 cal_ctx_wr_dma_addr(ctx, addr);
314 static inline void cal_process_buffer_complete(struct cal_ctx *ctx)
316 ctx->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
317 ctx->cur_frm->vb.field = ctx->m_fmt.field;
318 ctx->cur_frm->vb.sequence = ctx->sequence++;
320 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
321 ctx->cur_frm = ctx->next_frm;
324 static irqreturn_t cal_irq(int irq_cal, void *data)
326 struct cal_dev *cal = data;
328 struct cal_dmaqueue *dma_q;
331 status = cal_read(cal, CAL_HL_IRQSTATUS(0));
335 cal_write(cal, CAL_HL_IRQSTATUS(0), status);
337 if (status & CAL_HL_IRQ_OCPO_ERR_MASK)
338 dev_err_ratelimited(cal->dev, "OCPO ERROR\n");
340 for (i = 0; i < CAL_NUM_CSI2_PORTS; ++i) {
341 if (status & CAL_HL_IRQ_CIO_MASK(i)) {
342 u32 cio_stat = cal_read(cal,
343 CAL_CSI2_COMPLEXIO_IRQSTATUS(i));
345 dev_err_ratelimited(cal->dev,
346 "CIO%u error: %#08x\n", i, cio_stat);
348 cal_write(cal, CAL_CSI2_COMPLEXIO_IRQSTATUS(i),
354 /* Check which DMA just finished */
355 status = cal_read(cal, CAL_HL_IRQSTATUS(1));
359 /* Clear Interrupt status */
360 cal_write(cal, CAL_HL_IRQSTATUS(1), status);
362 for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
363 if (status & CAL_HL_IRQ_MASK(i)) {
366 spin_lock(&ctx->slock);
367 ctx->dma_act = false;
369 if (ctx->cur_frm != ctx->next_frm)
370 cal_process_buffer_complete(ctx);
372 spin_unlock(&ctx->slock);
377 /* Check which DMA just started */
378 status = cal_read(cal, CAL_HL_IRQSTATUS(2));
382 /* Clear Interrupt status */
383 cal_write(cal, CAL_HL_IRQSTATUS(2), status);
385 for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
386 if (status & CAL_HL_IRQ_MASK(i)) {
390 spin_lock(&ctx->slock);
392 if (!list_empty(&dma_q->active) &&
393 ctx->cur_frm == ctx->next_frm)
394 cal_schedule_next_buffer(ctx);
395 spin_unlock(&ctx->slock);
403 /* ------------------------------------------------------------------
404 * Asynchronous V4L2 subdev binding
405 * ------------------------------------------------------------------
408 struct cal_v4l2_async_subdev {
409 struct v4l2_async_subdev asd; /* Must be first */
410 struct cal_camerarx *phy;
413 static inline struct cal_v4l2_async_subdev *
414 to_cal_asd(struct v4l2_async_subdev *asd)
416 return container_of(asd, struct cal_v4l2_async_subdev, asd);
419 static int cal_async_notifier_bound(struct v4l2_async_notifier *notifier,
420 struct v4l2_subdev *subdev,
421 struct v4l2_async_subdev *asd)
423 struct cal_camerarx *phy = to_cal_asd(asd)->phy;
426 phy_info(phy, "Rejecting subdev %s (Already set!!)",
431 phy->sensor = subdev;
432 phy_dbg(1, phy, "Using sensor %s for capture\n", subdev->name);
437 static int cal_async_notifier_complete(struct v4l2_async_notifier *notifier)
439 struct cal_dev *cal = container_of(notifier, struct cal_dev, notifier);
442 for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
444 cal_ctx_v4l2_register(cal->ctx[i]);
450 static const struct v4l2_async_notifier_operations cal_async_notifier_ops = {
451 .bound = cal_async_notifier_bound,
452 .complete = cal_async_notifier_complete,
455 static int cal_async_notifier_register(struct cal_dev *cal)
460 v4l2_async_notifier_init(&cal->notifier);
461 cal->notifier.ops = &cal_async_notifier_ops;
463 for (i = 0; i < ARRAY_SIZE(cal->phy); ++i) {
464 struct cal_camerarx *phy = cal->phy[i];
465 struct cal_v4l2_async_subdev *casd;
466 struct v4l2_async_subdev *asd;
467 struct fwnode_handle *fwnode;
469 if (!phy || !phy->sensor_node)
472 fwnode = of_fwnode_handle(phy->sensor_node);
473 asd = v4l2_async_notifier_add_fwnode_subdev(&cal->notifier,
477 phy_err(phy, "Failed to add subdev to notifier\n");
482 casd = to_cal_asd(asd);
486 ret = v4l2_async_notifier_register(&cal->v4l2_dev, &cal->notifier);
488 cal_err(cal, "Error registering async notifier\n");
495 v4l2_async_notifier_cleanup(&cal->notifier);
499 static void cal_async_notifier_unregister(struct cal_dev *cal)
501 v4l2_async_notifier_unregister(&cal->notifier);
502 v4l2_async_notifier_cleanup(&cal->notifier);
505 /* ------------------------------------------------------------------
506 * Media and V4L2 device handling
507 * ------------------------------------------------------------------
511 * Register user-facing devices. To be called at the end of the probe function
512 * when all resources are initialized and ready.
514 static int cal_media_register(struct cal_dev *cal)
518 ret = media_device_register(&cal->mdev);
520 cal_err(cal, "Failed to register media device\n");
525 * Register the async notifier. This may trigger registration of the
526 * V4L2 video devices if all subdevs are ready.
528 ret = cal_async_notifier_register(cal);
530 media_device_unregister(&cal->mdev);
538 * Unregister the user-facing devices, but don't free memory yet. To be called
539 * at the beginning of the remove function, to disallow access from userspace.
541 static void cal_media_unregister(struct cal_dev *cal)
545 /* Unregister all the V4L2 video devices. */
546 for (i = 0; i < ARRAY_SIZE(cal->ctx); i++) {
548 cal_ctx_v4l2_unregister(cal->ctx[i]);
551 cal_async_notifier_unregister(cal);
552 media_device_unregister(&cal->mdev);
556 * Initialize the in-kernel objects. To be called at the beginning of the probe
557 * function, before the V4L2 device is used by the driver.
559 static int cal_media_init(struct cal_dev *cal)
561 struct media_device *mdev = &cal->mdev;
564 mdev->dev = cal->dev;
565 mdev->hw_revision = cal->revision;
566 strscpy(mdev->model, "CAL", sizeof(mdev->model));
567 snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s",
568 dev_name(mdev->dev));
569 media_device_init(mdev);
572 * Initialize the V4L2 device (despite the function name, this performs
573 * initialization, not registration).
575 cal->v4l2_dev.mdev = mdev;
576 ret = v4l2_device_register(cal->dev, &cal->v4l2_dev);
578 cal_err(cal, "Failed to register V4L2 device\n");
582 vb2_dma_contig_set_max_seg_size(cal->dev, DMA_BIT_MASK(32));
588 * Cleanup the in-kernel objects, freeing memory. To be called at the very end
589 * of the remove sequence, when nothing (including userspace) can access the
592 static void cal_media_cleanup(struct cal_dev *cal)
596 for (i = 0; i < ARRAY_SIZE(cal->ctx); i++) {
598 cal_ctx_v4l2_cleanup(cal->ctx[i]);
601 v4l2_device_unregister(&cal->v4l2_dev);
602 media_device_cleanup(&cal->mdev);
604 vb2_dma_contig_clear_max_seg_size(cal->dev);
607 /* ------------------------------------------------------------------
608 * Initialization and module stuff
609 * ------------------------------------------------------------------
612 static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst)
617 ctx = devm_kzalloc(cal->dev, sizeof(*ctx), GFP_KERNEL);
622 ctx->phy = cal->phy[inst];
626 ret = cal_ctx_v4l2_init(ctx);
633 static const struct of_device_id cal_of_match[] = {
635 .compatible = "ti,dra72-cal",
636 .data = (void *)&dra72x_cal_data,
639 .compatible = "ti,dra72-pre-es2-cal",
640 .data = (void *)&dra72x_es1_cal_data,
643 .compatible = "ti,dra76-cal",
644 .data = (void *)&dra76x_cal_data,
647 .compatible = "ti,am654-cal",
648 .data = (void *)&am654_cal_data,
652 MODULE_DEVICE_TABLE(of, cal_of_match);
654 /* Get hardware revision and info. */
656 #define CAL_HL_HWINFO_VALUE 0xa3c90469
658 static void cal_get_hwinfo(struct cal_dev *cal)
662 cal->revision = cal_read(cal, CAL_HL_REVISION);
663 switch (FIELD_GET(CAL_HL_REVISION_SCHEME_MASK, cal->revision)) {
664 case CAL_HL_REVISION_SCHEME_H08:
665 cal_dbg(3, cal, "CAL HW revision %lu.%lu.%lu (0x%08x)\n",
666 FIELD_GET(CAL_HL_REVISION_MAJOR_MASK, cal->revision),
667 FIELD_GET(CAL_HL_REVISION_MINOR_MASK, cal->revision),
668 FIELD_GET(CAL_HL_REVISION_RTL_MASK, cal->revision),
672 case CAL_HL_REVISION_SCHEME_LEGACY:
674 cal_info(cal, "Unexpected CAL HW revision 0x%08x\n",
679 hwinfo = cal_read(cal, CAL_HL_HWINFO);
680 if (hwinfo != CAL_HL_HWINFO_VALUE)
681 cal_info(cal, "CAL_HL_HWINFO = 0x%08x, expected 0x%08x\n",
682 hwinfo, CAL_HL_HWINFO_VALUE);
685 static int cal_init_camerarx_regmap(struct cal_dev *cal)
687 struct platform_device *pdev = to_platform_device(cal->dev);
688 struct device_node *np = cal->dev->of_node;
689 struct regmap_config config = { };
690 struct regmap *syscon;
691 struct resource *res;
695 syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,camerrx-control",
697 if (!IS_ERR(syscon)) {
698 cal->syscon_camerrx = syscon;
699 cal->syscon_camerrx_offset = offset;
703 dev_warn(cal->dev, "failed to get ti,camerrx-control: %ld\n",
707 * Backward DTS compatibility. If syscon entry is not present then
708 * check if the camerrx_control resource is present.
710 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
712 base = devm_ioremap_resource(cal->dev, res);
714 cal_err(cal, "failed to ioremap camerrx_control\n");
715 return PTR_ERR(base);
718 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
719 res->name, &res->start, &res->end);
721 config.reg_bits = 32;
722 config.reg_stride = 4;
723 config.val_bits = 32;
724 config.max_register = resource_size(res) - 4;
726 syscon = regmap_init_mmio(NULL, base, &config);
727 if (IS_ERR(syscon)) {
728 pr_err("regmap init failed\n");
729 return PTR_ERR(syscon);
733 * In this case the base already point to the direct CM register so no
734 * need for an offset.
736 cal->syscon_camerrx = syscon;
737 cal->syscon_camerrx_offset = 0;
742 static int cal_probe(struct platform_device *pdev)
746 bool connected = false;
751 cal = devm_kzalloc(&pdev->dev, sizeof(*cal), GFP_KERNEL);
755 cal->data = of_device_get_match_data(&pdev->dev);
757 dev_err(&pdev->dev, "Could not get feature data based on compatible version\n");
761 cal->dev = &pdev->dev;
762 platform_set_drvdata(pdev, cal);
764 /* Acquire resources: clocks, CAMERARX regmap, I/O memory and IRQ. */
765 cal->fclk = devm_clk_get(&pdev->dev, "fck");
766 if (IS_ERR(cal->fclk)) {
767 dev_err(&pdev->dev, "cannot get CAL fclk\n");
768 return PTR_ERR(cal->fclk);
771 ret = cal_init_camerarx_regmap(cal);
775 cal->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
777 cal->base = devm_ioremap_resource(&pdev->dev, cal->res);
778 if (IS_ERR(cal->base))
779 return PTR_ERR(cal->base);
781 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
782 cal->res->name, &cal->res->start, &cal->res->end);
784 irq = platform_get_irq(pdev, 0);
785 cal_dbg(1, cal, "got irq# %d\n", irq);
786 ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME,
791 /* Read the revision and hardware info to verify hardware access. */
792 pm_runtime_enable(&pdev->dev);
793 ret = pm_runtime_get_sync(&pdev->dev);
795 goto error_pm_runtime;
798 pm_runtime_put_sync(&pdev->dev);
800 /* Create CAMERARX PHYs. */
801 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
802 cal->phy[i] = cal_camerarx_create(cal, i);
803 if (IS_ERR(cal->phy[i])) {
804 ret = PTR_ERR(cal->phy[i]);
809 if (cal->phy[i]->sensor_node)
814 cal_err(cal, "Neither port is configured, no point in staying up\n");
819 /* Initialize the media device. */
820 ret = cal_media_init(cal);
824 /* Create contexts. */
825 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
826 if (!cal->phy[i]->sensor_node)
829 cal->ctx[i] = cal_ctx_create(cal, i);
831 cal_err(cal, "Failed to create context %u\n", i);
837 /* Register the media device. */
838 ret = cal_media_register(cal);
845 for (i = 0; i < ARRAY_SIZE(cal->ctx); i++) {
848 cal_ctx_v4l2_cleanup(ctx);
851 cal_media_cleanup(cal);
854 for (i = 0; i < ARRAY_SIZE(cal->phy); i++)
855 cal_camerarx_destroy(cal->phy[i]);
858 pm_runtime_disable(&pdev->dev);
863 static int cal_remove(struct platform_device *pdev)
865 struct cal_dev *cal = platform_get_drvdata(pdev);
868 cal_dbg(1, cal, "Removing %s\n", CAL_MODULE_NAME);
870 pm_runtime_get_sync(&pdev->dev);
872 cal_media_unregister(cal);
874 for (i = 0; i < ARRAY_SIZE(cal->phy); i++) {
876 cal_camerarx_disable(cal->phy[i]);
879 cal_media_cleanup(cal);
881 for (i = 0; i < ARRAY_SIZE(cal->phy); i++)
882 cal_camerarx_destroy(cal->phy[i]);
884 pm_runtime_put_sync(&pdev->dev);
885 pm_runtime_disable(&pdev->dev);
890 static int cal_runtime_resume(struct device *dev)
892 struct cal_dev *cal = dev_get_drvdata(dev);
894 if (cal->data->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) {
896 * Apply errata on both port everytime we (re-)enable
899 cal_camerarx_i913_errata(cal->phy[0]);
900 cal_camerarx_i913_errata(cal->phy[1]);
906 static const struct dev_pm_ops cal_pm_ops = {
907 .runtime_resume = cal_runtime_resume,
910 static struct platform_driver cal_pdrv = {
912 .remove = cal_remove,
914 .name = CAL_MODULE_NAME,
916 .of_match_table = cal_of_match,
920 module_platform_driver(cal_pdrv);