1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Camera Access Layer (CAL) - CAMERARX
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
8 * Benoit Parrot <bparrot@ti.com>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
28 /* ------------------------------------------------------------------
29 * I/O Register Accessors
30 * ------------------------------------------------------------------
33 static inline u32 camerarx_read(struct cal_camerarx *phy, u32 offset)
35 return ioread32(phy->base + offset);
38 static inline void camerarx_write(struct cal_camerarx *phy, u32 offset, u32 val)
40 iowrite32(val, phy->base + offset);
43 /* ------------------------------------------------------------------
45 * ------------------------------------------------------------------
48 static s64 cal_camerarx_get_external_rate(struct cal_camerarx *phy)
50 struct v4l2_ctrl *ctrl;
53 ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
55 phy_err(phy, "no pixel rate control in subdev: %s\n",
60 rate = v4l2_ctrl_g_ctrl_int64(ctrl);
61 phy_dbg(3, phy, "sensor Pixel Rate: %llu\n", rate);
66 static void cal_camerarx_lane_config(struct cal_camerarx *phy)
68 u32 val = cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));
69 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
70 u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
71 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
72 &phy->endpoint.bus.mipi_csi2;
75 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
76 cal_set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
77 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
79 * Every lane are one nibble apart starting with the
80 * clock followed by the data lanes so shift masks by 4.
84 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
85 cal_set_field(&val, mipi_csi2->lane_polarities[lane + 1],
89 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val);
90 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
94 static void cal_camerarx_enable(struct cal_camerarx *phy)
96 u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes;
98 regmap_field_write(phy->fields[F_CAMMODE], 0);
99 /* Always enable all lanes at the phy control level */
100 regmap_field_write(phy->fields[F_LANEENABLE], (1 << num_lanes) - 1);
101 /* F_CSI_MODE is not present on every architecture */
102 if (phy->fields[F_CSI_MODE])
103 regmap_field_write(phy->fields[F_CSI_MODE], 1);
104 regmap_field_write(phy->fields[F_CTRLCLKEN], 1);
107 void cal_camerarx_disable(struct cal_camerarx *phy)
109 regmap_field_write(phy->fields[F_CTRLCLKEN], 0);
113 * TCLK values are OK at their reset values
117 #define TCLK_SETTLE 14
119 static void cal_camerarx_config(struct cal_camerarx *phy, s64 external_rate,
120 const struct cal_fmt *fmt)
122 unsigned int reg0, reg1;
123 unsigned int ths_term, ths_settle;
124 unsigned int csi2_ddrclk_khz;
125 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
126 &phy->endpoint.bus.mipi_csi2;
127 u32 num_lanes = mipi_csi2->num_data_lanes;
129 /* DPHY timing configuration */
132 * CSI-2 is DDR and we only count used lanes.
134 * csi2_ddrclk_khz = external_rate / 1000
135 * / (2 * num_lanes) * fmt->bpp;
137 csi2_ddrclk_khz = div_s64(external_rate * fmt->bpp,
138 2 * num_lanes * 1000);
140 phy_dbg(1, phy, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
142 /* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
143 ths_term = 20 * csi2_ddrclk_khz / 1000000;
144 phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
146 /* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
147 ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
148 phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
150 reg0 = camerarx_read(phy, CAL_CSI2_PHY_REG0);
151 cal_set_field(®0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
152 CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
153 cal_set_field(®0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
154 cal_set_field(®0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
156 phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0);
157 camerarx_write(phy, CAL_CSI2_PHY_REG0, reg0);
159 reg1 = camerarx_read(phy, CAL_CSI2_PHY_REG1);
160 cal_set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
161 cal_set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
162 cal_set_field(®1, TCLK_MISS,
163 CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
164 cal_set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
166 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1);
167 camerarx_write(phy, CAL_CSI2_PHY_REG1, reg1);
170 static void cal_camerarx_power(struct cal_camerarx *phy, bool enable)
175 target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
176 CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
178 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
179 target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
181 for (i = 0; i < 10; i++) {
184 current_state = cal_read_field(phy->cal,
185 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
186 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
188 if (current_state == target_state)
191 usleep_range(1000, 1100);
195 phy_err(phy, "Failed to power %s complexio\n",
196 enable ? "up" : "down");
199 static void cal_camerarx_wait_reset(struct cal_camerarx *phy)
201 unsigned long timeout;
203 timeout = jiffies + msecs_to_jiffies(750);
204 while (time_before(jiffies, timeout)) {
205 if (cal_read_field(phy->cal,
206 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
207 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
208 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
210 usleep_range(500, 5000);
213 if (cal_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
214 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
215 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
216 phy_err(phy, "Timeout waiting for Complex IO reset done\n");
219 static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy)
221 unsigned long timeout;
223 timeout = jiffies + msecs_to_jiffies(750);
224 while (time_before(jiffies, timeout)) {
225 if (cal_read_field(phy->cal,
226 CAL_CSI2_TIMING(phy->instance),
227 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0)
229 usleep_range(500, 5000);
232 if (cal_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
233 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0)
234 phy_err(phy, "Timeout waiting for stop state\n");
237 int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt)
244 external_rate = cal_camerarx_get_external_rate(phy);
245 if (external_rate < 0)
246 return external_rate;
248 ret = v4l2_subdev_call(phy->sensor, core, s_power, 1);
249 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) {
250 phy_err(phy, "power on failed in subdev\n");
255 * CSI-2 PHY Link Initialization Sequence, according to the DRA74xP /
256 * DRA75xP / DRA76xP / DRA77xP TRM. The DRA71x / DRA72x and the AM65x /
257 * DRA80xM TRMs have a a slightly simplified sequence.
261 * 1. Configure all CSI-2 low level protocol registers to be ready to
262 * receive signals/data from the CSI-2 PHY.
264 * i.-v. Configure the lanes position and polarity.
266 cal_camerarx_lane_config(phy);
269 * vi.-vii. Configure D-PHY mode, enable the required lanes and
270 * enable the CAMERARX clock.
272 cal_camerarx_enable(phy);
275 * 2. CSI PHY and link initialization sequence.
277 * a. Deassert the CSI-2 PHY reset. Do not wait for reset completion
278 * at this point, as it requires the external sensor to send the
281 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
282 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
283 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
284 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n",
286 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)));
288 /* Dummy read to allow SCP reset to complete. */
289 camerarx_read(phy, CAL_CSI2_PHY_REG0);
291 /* Program the PHY timing parameters. */
292 cal_camerarx_config(phy, external_rate, fmt);
295 * b. Assert the FORCERXMODE signal.
297 * The stop-state-counter is based on fclk cycles, and we always use
298 * the x16 and x4 settings, so stop-state-timeout =
299 * fclk-cycle * 16 * 4 * counter.
301 * Stop-state-timeout must be more than 100us as per CSI-2 spec, so we
302 * calculate a timeout that's 100us (rounding up).
304 sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4);
306 val = cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance));
307 cal_set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
308 cal_set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
309 cal_set_field(&val, sscounter,
310 CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
311 cal_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val);
312 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n",
314 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
316 /* Assert the FORCERXMODE signal. */
317 cal_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
318 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
319 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n",
321 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
324 * c. Connect pull-down on CSI-2 PHY link (using pad control).
326 * This is not required on DRA71x, DRA72x, AM65x and DRA80xM. Not
331 * d. Power up the CSI-2 PHY.
332 * e. Check whether the state status reaches the ON state.
334 cal_camerarx_power(phy, true);
337 * Start the sensor to enable the CSI-2 HS clock. We can now wait for
338 * CSI-2 PHY reset to complete.
340 ret = v4l2_subdev_call(phy->sensor, video, s_stream, 1);
342 v4l2_subdev_call(phy->sensor, core, s_power, 0);
343 phy_err(phy, "stream on failed in subdev\n");
347 cal_camerarx_wait_reset(phy);
349 /* f. Wait for STOPSTATE=1 for all enabled lane modules. */
350 cal_camerarx_wait_stop_state(phy);
352 phy_dbg(1, phy, "CSI2_%u_REG1 = 0x%08x (bits 31-28 should be set)\n",
353 phy->instance, camerarx_read(phy, CAL_CSI2_PHY_REG1));
356 * g. Disable pull-down on CSI-2 PHY link (using pad control).
358 * This is not required on DRA71x, DRA72x, AM65x and DRA80xM. Not
365 void cal_camerarx_stop(struct cal_camerarx *phy)
370 cal_camerarx_power(phy, false);
372 /* Assert Complex IO Reset */
373 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
374 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL,
375 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
377 /* Wait for power down completion */
378 for (i = 0; i < 10; i++) {
379 if (cal_read_field(phy->cal,
380 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
381 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
382 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING)
384 usleep_range(1000, 1100);
386 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n",
388 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)), i,
389 (i >= 10) ? "(timeout)" : "");
391 /* Disable the phy */
392 cal_camerarx_disable(phy);
394 if (v4l2_subdev_call(phy->sensor, video, s_stream, 0))
395 phy_err(phy, "stream off failed in subdev\n");
397 ret = v4l2_subdev_call(phy->sensor, core, s_power, 0);
398 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
399 phy_err(phy, "power off failed in subdev\n");
403 * Errata i913: CSI2 LDO Needs to be disabled when module is powered on
405 * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
406 * LDOs on the device are disabled if CSI-2 module is powered on
407 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
408 * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
409 * current draw on the module supply in active mode.
411 * Errata does not apply when CSI-2 module is powered off
412 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
415 * Set the following register bits to disable the LDO,
416 * which is essentially CSI2 REG10 bit 6:
418 * Core 0: 0x4845 B828 = 0x0000 0040
419 * Core 1: 0x4845 B928 = 0x0000 0040
421 void cal_camerarx_i913_errata(struct cal_camerarx *phy)
423 u32 reg10 = camerarx_read(phy, CAL_CSI2_PHY_REG10);
425 cal_set_field(®10, 1, CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK);
427 phy_dbg(1, phy, "CSI2_%d_REG10 = 0x%08x\n", phy->instance, reg10);
428 camerarx_write(phy, CAL_CSI2_PHY_REG10, reg10);
432 * Enable the expected IRQ sources
434 void cal_camerarx_enable_irqs(struct cal_camerarx *phy)
438 const u32 cio_err_mask =
439 CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK |
440 CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK |
441 CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK |
442 CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK;
444 /* Enable CIO error irqs */
445 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0),
446 CAL_HL_IRQ_CIO_MASK(phy->instance));
447 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance),
450 /* Always enable OCPO error */
451 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
453 /* Enable IRQ_WDMA_END 0/1 */
455 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
456 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(1), val);
457 /* Enable IRQ_WDMA_START 0/1 */
459 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
460 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(2), val);
461 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
462 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0xFF000000);
465 void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
469 /* Disable CIO error irqs */
470 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0),
471 CAL_HL_IRQ_CIO_MASK(phy->instance));
472 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0);
474 /* Disable IRQ_WDMA_END 0/1 */
476 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
477 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(1), val);
478 /* Disable IRQ_WDMA_START 0/1 */
480 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
481 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(2), val);
482 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
483 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0);
486 void cal_camerarx_ppi_enable(struct cal_camerarx *phy)
488 cal_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), BIT(3));
489 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
490 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
493 void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
495 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
496 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
499 static int cal_camerarx_regmap_init(struct cal_dev *cal,
500 struct cal_camerarx *phy)
502 const struct cal_camerarx_data *phy_data;
508 phy_data = &cal->data->camerarx[phy->instance];
510 for (i = 0; i < F_MAX_FIELDS; i++) {
511 struct reg_field field = {
512 .reg = cal->syscon_camerrx_offset,
513 .lsb = phy_data->fields[i].lsb,
514 .msb = phy_data->fields[i].msb,
518 * Here we update the reg offset with the
521 phy->fields[i] = devm_regmap_field_alloc(cal->dev,
524 if (IS_ERR(phy->fields[i])) {
525 cal_err(cal, "Unable to allocate regmap fields\n");
526 return PTR_ERR(phy->fields[i]);
533 static int cal_camerarx_parse_dt(struct cal_camerarx *phy)
535 struct v4l2_fwnode_endpoint *endpoint = &phy->endpoint;
536 struct device_node *ep_node;
537 char data_lanes[V4L2_FWNODE_CSI2_MAX_DATA_LANES * 2];
542 * Find the endpoint node for the port corresponding to the PHY
543 * instance, and parse its CSI-2-related properties.
545 ep_node = of_graph_get_endpoint_by_regs(phy->cal->dev->of_node,
549 * The endpoint is not mandatory, not all PHY instances need to
550 * be connected in DT.
552 phy_dbg(3, phy, "Port has no endpoint\n");
556 endpoint->bus_type = V4L2_MBUS_CSI2_DPHY;
557 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), endpoint);
559 phy_err(phy, "Failed to parse endpoint\n");
563 for (i = 0; i < endpoint->bus.mipi_csi2.num_data_lanes; i++) {
564 unsigned int lane = endpoint->bus.mipi_csi2.data_lanes[i];
567 phy_err(phy, "Invalid position %u for data lane %u\n",
573 data_lanes[i*2] = '0' + lane;
574 data_lanes[i*2+1] = ' ';
577 data_lanes[i*2-1] = '\0';
580 "CSI-2 bus: clock lane <%u>, data lanes <%s>, flags 0x%08x\n",
581 endpoint->bus.mipi_csi2.clock_lane, data_lanes,
582 endpoint->bus.mipi_csi2.flags);
584 /* Retrieve the connected device and store it for later use. */
585 phy->sensor_node = of_graph_get_remote_port_parent(ep_node);
586 if (!phy->sensor_node) {
587 phy_dbg(3, phy, "Can't get remote parent\n");
592 phy_dbg(1, phy, "Found connected device %pOFn\n", phy->sensor_node);
595 of_node_put(ep_node);
599 struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
600 unsigned int instance)
602 struct platform_device *pdev = to_platform_device(cal->dev);
603 struct cal_camerarx *phy;
606 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
608 return ERR_PTR(-ENOMEM);
611 phy->instance = instance;
613 phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
617 phy->base = devm_ioremap_resource(cal->dev, phy->res);
618 if (IS_ERR(phy->base)) {
619 cal_err(cal, "failed to ioremap\n");
620 ret = PTR_ERR(phy->base);
624 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
625 phy->res->name, &phy->res->start, &phy->res->end);
627 ret = cal_camerarx_regmap_init(cal, phy);
631 ret = cal_camerarx_parse_dt(phy);
642 void cal_camerarx_destroy(struct cal_camerarx *phy)
647 of_node_put(phy->sensor_node);