1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
4 * Author: Yong Deng <yong.deng@magewell.com>
5 * Copyright 2021-2022 Bootlin
6 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
9 #ifndef _SUN6I_CSI_REG_H_
10 #define _SUN6I_CSI_REG_H_
12 #include <linux/kernel.h>
14 #define SUN6I_CSI_ADDR_VALUE(a) ((a) >> 2)
16 #define SUN6I_CSI_EN_REG 0x0
17 #define SUN6I_CSI_EN_VER_EN BIT(30)
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16))
19 #define SUN6I_CSI_EN_SRAM_PWDN BIT(8)
20 #define SUN6I_CSI_EN_PTN_START BIT(4)
21 #define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)
22 #define SUN6I_CSI_EN_CLK_CNT_EN BIT(2)
23 #define SUN6I_CSI_EN_PTN_GEN_EN BIT(1)
24 #define SUN6I_CSI_EN_CSI_EN BIT(0)
26 /* Note that Allwinner manuals and code invert positive/negative definitions. */
28 #define SUN6I_CSI_IF_CFG_REG 0x4
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24))
30 #define SUN6I_CSI_IF_CFG_SRC_TYPE_PROGRESSIVE (0 << 21)
31 #define SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED (1 << 21)
32 #define SUN6I_CSI_IF_CFG_FPS_DS BIT(20)
33 #define SUN6I_CSI_IF_CFG_FIELD_POSITIVE (0 << 19)
34 #define SUN6I_CSI_IF_CFG_FIELD_NEGATIVE (1 << 19)
35 #define SUN6I_CSI_IF_CFG_VREF_POL_POSITIVE (0 << 18)
36 #define SUN6I_CSI_IF_CFG_VREF_POL_NEGATIVE (1 << 18)
37 #define SUN6I_CSI_IF_CFG_HREF_POL_POSITIVE (0 << 17)
38 #define SUN6I_CSI_IF_CFG_HREF_POL_NEGATIVE (1 << 17)
39 #define SUN6I_CSI_IF_CFG_CLK_POL_FALLING (0 << 16)
40 #define SUN6I_CSI_IF_CFG_CLK_POL_RISING (1 << 16)
41 #define SUN6I_CSI_IF_CFG_FIELD_DT_FIELD_VSYNC (0 << 14)
42 #define SUN6I_CSI_IF_CFG_FIELD_DT_FIELD (1 << 14)
43 #define SUN6I_CSI_IF_CFG_FIELD_DT_VSYNC (2 << 14)
44 #define SUN6I_CSI_IF_CFG_DATA_WIDTH_8 (0 << 8)
45 #define SUN6I_CSI_IF_CFG_DATA_WIDTH_10 (1 << 8)
46 #define SUN6I_CSI_IF_CFG_DATA_WIDTH_12 (2 << 8)
47 #define SUN6I_CSI_IF_CFG_DATA_WIDTH_8_PLUS_2 (3 << 8)
48 #define SUN6I_CSI_IF_CFG_DATA_WIDTH_2_TIMES_8 (4 << 8)
49 #define SUN6I_CSI_IF_CFG_IF_CSI (0 << 7)
50 #define SUN6I_CSI_IF_CFG_IF_MIPI (1 << 7)
51 #define SUN6I_CSI_IF_CFG_IF_CSI_YUV_RAW (0 << 0)
52 #define SUN6I_CSI_IF_CFG_IF_CSI_YUV_COMBINED (1 << 0)
53 #define SUN6I_CSI_IF_CFG_IF_CSI_BT656 (4 << 0)
54 #define SUN6I_CSI_IF_CFG_IF_CSI_BT1120 (5 << 0)
56 #define SUN6I_CSI_CAP_REG 0x8
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2))
58 #define SUN6I_CSI_CAP_VCAP_ON BIT(1)
59 #define SUN6I_CSI_CAP_SCAP_ON BIT(0)
61 #define SUN6I_CSI_SYNC_CNT_REG 0xc
62 #define SUN6I_CSI_FIFO_THRS_REG 0x10
63 #define SUN6I_CSI_BT656_HEAD_CFG_REG 0x14
65 #define SUN6I_CSI_PTN_LEN_REG 0x30
66 #define SUN6I_CSI_PTN_ADDR_REG 0x34
67 #define SUN6I_CSI_VER_REG 0x3c
69 #define SUN6I_CSI_CH_CFG_REG 0x44
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24))
71 #define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20))
72 #define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16))
73 #define SUN6I_CSI_CH_CFG_VFLIP_EN BIT(13)
74 #define SUN6I_CSI_CH_CFG_HFLIP_EN BIT(12)
75 #define SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD0 (0 << 10)
76 #define SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD1 (1 << 10)
77 #define SUN6I_CSI_CH_CFG_FIELD_SEL_EITHER (2 << 10)
78 #define SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(v) (((v) << 8) & GENMASK(9, 8))
80 #define SUN6I_CSI_INPUT_FMT_RAW 0
81 #define SUN6I_CSI_INPUT_FMT_YUV422 3
82 #define SUN6I_CSI_INPUT_FMT_YUV420 4
84 /* Note that Allwinner manuals and code invert frame/field definitions. */
87 #define SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8 0
88 #define SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10 1
89 #define SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12 2
90 #define SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565 4
91 #define SUN6I_CSI_OUTPUT_FMT_FRAME_RGB888 5
92 #define SUN6I_CSI_OUTPUT_FMT_FRAME_PRGB888 6
93 #define SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8 8
94 #define SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10 9
95 #define SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12 10
96 #define SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565 12
97 #define SUN6I_CSI_OUTPUT_FMT_FIELD_RGB888 13
98 #define SUN6I_CSI_OUTPUT_FMT_FIELD_PRGB888 14
101 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422P 0
102 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P 1
103 #define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P 2
104 #define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422P 3
105 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP 4
106 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP 5
107 #define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP 6
108 #define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP 7
109 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422MB 8
110 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420MB 9
111 #define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420MB 10
112 #define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422MB 11
113 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP_10 12
114 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP_10 13
117 #define SUN6I_CSI_INPUT_YUV_SEQ_YUYV 0
118 #define SUN6I_CSI_INPUT_YUV_SEQ_YVYU 1
119 #define SUN6I_CSI_INPUT_YUV_SEQ_UYVY 2
120 #define SUN6I_CSI_INPUT_YUV_SEQ_VYUY 3
122 /* YUV Semi-planar */
123 #define SUN6I_CSI_INPUT_YUV_SEQ_UV 0
124 #define SUN6I_CSI_INPUT_YUV_SEQ_VU 1
126 #define SUN6I_CSI_CH_SCALE_REG 0x4c
127 #define SUN6I_CSI_CH_SCALE_QUART_EN BIT(0)
129 #define SUN6I_CSI_CH_FIFO0_ADDR_REG 0x50
130 #define SUN6I_CSI_CH_FIFO1_ADDR_REG 0x58
131 #define SUN6I_CSI_CH_FIFO2_ADDR_REG 0x60
133 #define SUN6I_CSI_CH_STA_REG 0x6c
134 #define SUN6I_CSI_CH_STA_FIELD BIT(2)
135 #define SUN6I_CSI_CH_STA_VCAP BIT(1)
136 #define SUN6I_CSI_CH_STA_SCAP BIT(0)
138 #define SUN6I_CSI_CH_INT_EN_REG 0x70
139 #define SUN6I_CSI_CH_INT_EN_VS BIT(7)
140 #define SUN6I_CSI_CH_INT_EN_HB_OF BIT(6)
141 #define SUN6I_CSI_CH_INT_EN_MUL_ERR BIT(5)
142 #define SUN6I_CSI_CH_INT_EN_FIFO2_OF BIT(4)
143 #define SUN6I_CSI_CH_INT_EN_FIFO1_OF BIT(3)
144 #define SUN6I_CSI_CH_INT_EN_FIFO0_OF BIT(2)
145 #define SUN6I_CSI_CH_INT_EN_FD BIT(1)
146 #define SUN6I_CSI_CH_INT_EN_CD BIT(0)
148 #define SUN6I_CSI_CH_INT_STA_REG 0x74
149 #define SUN6I_CSI_CH_INT_STA_CLEAR 0xff
150 #define SUN6I_CSI_CH_INT_STA_VS BIT(7)
151 #define SUN6I_CSI_CH_INT_STA_HB_OF BIT(6)
152 #define SUN6I_CSI_CH_INT_STA_MUL_ERR BIT(5)
153 #define SUN6I_CSI_CH_INT_STA_FIFO2_OF BIT(4)
154 #define SUN6I_CSI_CH_INT_STA_FIFO1_OF BIT(3)
155 #define SUN6I_CSI_CH_INT_STA_FIFO0_OF BIT(2)
156 #define SUN6I_CSI_CH_INT_STA_FD BIT(1)
157 #define SUN6I_CSI_CH_INT_STA_CD BIT(0)
159 #define SUN6I_CSI_CH_FLD1_VSIZE_REG 0x78
160 #define SUN6I_CSI_CH_FLD1_VSIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))
161 #define SUN6I_CSI_CH_FLD1_VSIZE_VER_START(v) ((v) & GENMASK(12, 0))
163 #define SUN6I_CSI_CH_HSIZE_REG 0x80
164 #define SUN6I_CSI_CH_HSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))
165 #define SUN6I_CSI_CH_HSIZE_START(v) ((v) & GENMASK(12, 0))
167 #define SUN6I_CSI_CH_VSIZE_REG 0x84
168 #define SUN6I_CSI_CH_VSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))
169 #define SUN6I_CSI_CH_VSIZE_START(v) ((v) & GENMASK(12, 0))
171 #define SUN6I_CSI_CH_BUF_LEN_REG 0x88
172 #define SUN6I_CSI_CH_BUF_LEN_CHROMA_LINE(v) (((v) << 16) & GENMASK(29, 16))
173 #define SUN6I_CSI_CH_BUF_LEN_LUMA_LINE(v) ((v) & GENMASK(13, 0))
175 #define SUN6I_CSI_CH_FLIP_SIZE_REG 0x8c
176 #define SUN6I_CSI_CH_FLIP_SIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))
177 #define SUN6I_CSI_CH_FLIP_SIZE_VALID_LEN(v) ((v) & GENMASK(12, 0))
179 #define SUN6I_CSI_CH_FRM_CLK_CNT_REG 0x90
180 #define SUN6I_CSI_CH_ACC_ITNL_CLK_CNT_REG 0x94
181 #define SUN6I_CSI_CH_FIFO_STAT_REG 0x98
182 #define SUN6I_CSI_CH_PCLK_STAT_REG 0x9c