1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics SA 2015
4 * Authors: Yannick Fertre <yannick.fertre@st.com>
5 * Hugues Fruchet <hugues.fruchet@st.com>
9 #include <linux/interrupt.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
12 #ifdef CONFIG_VIDEO_STI_HVA_DEBUGFS
13 #include <linux/seq_file.h>
19 /* HVA register offsets */
20 #define HVA_HIF_REG_RST 0x0100U
21 #define HVA_HIF_REG_RST_ACK 0x0104U
22 #define HVA_HIF_REG_MIF_CFG 0x0108U
23 #define HVA_HIF_REG_HEC_MIF_CFG 0x010CU
24 #define HVA_HIF_REG_CFL 0x0110U
25 #define HVA_HIF_FIFO_CMD 0x0114U
26 #define HVA_HIF_FIFO_STS 0x0118U
27 #define HVA_HIF_REG_SFL 0x011CU
28 #define HVA_HIF_REG_IT_ACK 0x0120U
29 #define HVA_HIF_REG_ERR_IT_ACK 0x0124U
30 #define HVA_HIF_REG_LMI_ERR 0x0128U
31 #define HVA_HIF_REG_EMI_ERR 0x012CU
32 #define HVA_HIF_REG_HEC_MIF_ERR 0x0130U
33 #define HVA_HIF_REG_HEC_STS 0x0134U
34 #define HVA_HIF_REG_HVC_STS 0x0138U
35 #define HVA_HIF_REG_HJE_STS 0x013CU
36 #define HVA_HIF_REG_CNT 0x0140U
37 #define HVA_HIF_REG_HEC_CHKSYN_DIS 0x0144U
38 #define HVA_HIF_REG_CLK_GATING 0x0148U
39 #define HVA_HIF_REG_VERSION 0x014CU
40 #define HVA_HIF_REG_BSM 0x0150U
42 /* define value for version id register (HVA_HIF_REG_VERSION) */
43 #define VERSION_ID_MASK 0x0000FFFF
45 /* define values for BSM register (HVA_HIF_REG_BSM) */
46 #define BSM_CFG_VAL1 0x0003F000
47 #define BSM_CFG_VAL2 0x003F0000
49 /* define values for memory interface register (HVA_HIF_REG_MIF_CFG) */
50 #define MIF_CFG_VAL1 0x04460446
51 #define MIF_CFG_VAL2 0x04460806
52 #define MIF_CFG_VAL3 0x00000000
54 /* define value for HEC memory interface register (HVA_HIF_REG_MIF_CFG) */
55 #define HEC_MIF_CFG_VAL 0x000000C4
57 /* Bits definition for clock gating register (HVA_HIF_REG_CLK_GATING) */
58 #define CLK_GATING_HVC BIT(0)
59 #define CLK_GATING_HEC BIT(1)
60 #define CLK_GATING_HJE BIT(2)
62 /* fix hva clock rate */
63 #define CLK_RATE 300000000
65 /* fix delay for pmruntime */
66 #define AUTOSUSPEND_DELAY_MS 3
69 * hw encode error values
70 * NO_ERROR: Success, Task OK
71 * H264_BITSTREAM_OVERSIZE: VECH264 Bitstream size > bitstream buffer
72 * H264_FRAME_SKIPPED: VECH264 Frame skipped (refers to CPB Buffer Size)
73 * H264_SLICE_LIMIT_SIZE: VECH264 MB > slice limit size
74 * H264_MAX_SLICE_NUMBER: VECH264 max slice number reached
75 * H264_SLICE_READY: VECH264 Slice ready
76 * TASK_LIST_FULL: HVA/FPC task list full
77 (discard latest transform command)
78 * UNKNOWN_COMMAND: Transform command not known by HVA/FPC
79 * WRONG_CODEC_OR_RESOLUTION: Wrong Codec or Resolution Selection
80 * NO_INT_COMPLETION: Time-out on interrupt completion
81 * LMI_ERR: Local Memory Interface Error
82 * EMI_ERR: External Memory Interface Error
83 * HECMI_ERR: HEC Memory Interface Error
87 H264_BITSTREAM_OVERSIZE = 0x2,
88 H264_FRAME_SKIPPED = 0x4,
89 H264_SLICE_LIMIT_SIZE = 0x5,
90 H264_MAX_SLICE_NUMBER = 0x7,
91 H264_SLICE_READY = 0x8,
92 TASK_LIST_FULL = 0xF0,
93 UNKNOWN_COMMAND = 0xF1,
94 WRONG_CODEC_OR_RESOLUTION = 0xF4,
95 NO_INT_COMPLETION = 0x100,
101 static irqreturn_t hva_hw_its_interrupt(int irq, void *data)
103 struct hva_dev *hva = data;
105 /* read status registers */
106 hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
107 hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
109 /* acknowledge interruption */
110 writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
112 return IRQ_WAKE_THREAD;
115 static irqreturn_t hva_hw_its_irq_thread(int irq, void *arg)
117 struct hva_dev *hva = arg;
118 struct device *dev = hva_to_dev(hva);
119 u32 status = hva->sts_reg & 0xFF;
121 struct hva_ctx *ctx = NULL;
123 dev_dbg(dev, "%s %s: status: 0x%02x fifo level: 0x%02x\n",
124 HVA_PREFIX, __func__, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
127 * status: task_id[31:16] client_id[15:8] status[7:0]
128 * the context identifier is retrieved from the client identifier
130 ctx_id = (hva->sts_reg & 0xFF00) >> 8;
131 if (ctx_id >= HVA_MAX_INSTANCES) {
132 dev_err(dev, "%s %s: bad context identifier: %d\n",
133 HVA_PREFIX, __func__, ctx_id);
137 ctx = hva->instances[ctx_id];
143 dev_dbg(dev, "%s %s: no error\n",
144 ctx->name, __func__);
147 case H264_SLICE_READY:
148 dev_dbg(dev, "%s %s: h264 slice ready\n",
149 ctx->name, __func__);
152 case H264_FRAME_SKIPPED:
153 dev_dbg(dev, "%s %s: h264 frame skipped\n",
154 ctx->name, __func__);
157 case H264_BITSTREAM_OVERSIZE:
158 dev_err(dev, "%s %s:h264 bitstream oversize\n",
159 ctx->name, __func__);
162 case H264_SLICE_LIMIT_SIZE:
163 dev_err(dev, "%s %s: h264 slice limit size is reached\n",
164 ctx->name, __func__);
167 case H264_MAX_SLICE_NUMBER:
168 dev_err(dev, "%s %s: h264 max slice number is reached\n",
169 ctx->name, __func__);
173 dev_err(dev, "%s %s:task list full\n",
174 ctx->name, __func__);
177 case UNKNOWN_COMMAND:
178 dev_err(dev, "%s %s: command not known\n",
179 ctx->name, __func__);
182 case WRONG_CODEC_OR_RESOLUTION:
183 dev_err(dev, "%s %s: wrong codec or resolution\n",
184 ctx->name, __func__);
188 dev_err(dev, "%s %s: status not recognized\n",
189 ctx->name, __func__);
194 complete(&hva->interrupt);
199 static irqreturn_t hva_hw_err_interrupt(int irq, void *data)
201 struct hva_dev *hva = data;
203 /* read status registers */
204 hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
205 hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
207 /* read error registers */
208 hva->lmi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_LMI_ERR);
209 hva->emi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_EMI_ERR);
210 hva->hec_mif_err_reg = readl_relaxed(hva->regs +
211 HVA_HIF_REG_HEC_MIF_ERR);
213 /* acknowledge interruption */
214 writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
216 return IRQ_WAKE_THREAD;
219 static irqreturn_t hva_hw_err_irq_thread(int irq, void *arg)
221 struct hva_dev *hva = arg;
222 struct device *dev = hva_to_dev(hva);
226 dev_dbg(dev, "%s status: 0x%02x fifo level: 0x%02x\n",
227 HVA_PREFIX, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
230 * status: task_id[31:16] client_id[15:8] status[7:0]
231 * the context identifier is retrieved from the client identifier
233 ctx_id = (hva->sts_reg & 0xFF00) >> 8;
234 if (ctx_id >= HVA_MAX_INSTANCES) {
235 dev_err(dev, "%s bad context identifier: %d\n", HVA_PREFIX,
240 ctx = hva->instances[ctx_id];
244 if (hva->lmi_err_reg) {
245 dev_err(dev, "%s local memory interface error: 0x%08x\n",
246 ctx->name, hva->lmi_err_reg);
250 if (hva->emi_err_reg) {
251 dev_err(dev, "%s external memory interface error: 0x%08x\n",
252 ctx->name, hva->emi_err_reg);
256 if (hva->hec_mif_err_reg) {
257 dev_err(dev, "%s hec memory interface error: 0x%08x\n",
258 ctx->name, hva->hec_mif_err_reg);
262 complete(&hva->interrupt);
267 static unsigned long int hva_hw_get_ip_version(struct hva_dev *hva)
269 struct device *dev = hva_to_dev(hva);
270 unsigned long int version;
272 if (pm_runtime_get_sync(dev) < 0) {
273 dev_err(dev, "%s failed to get pm_runtime\n", HVA_PREFIX);
274 pm_runtime_put_noidle(dev);
275 mutex_unlock(&hva->protect_mutex);
279 version = readl_relaxed(hva->regs + HVA_HIF_REG_VERSION) &
282 pm_runtime_put_autosuspend(dev);
285 case HVA_VERSION_V400:
286 dev_dbg(dev, "%s IP hardware version 0x%lx\n",
287 HVA_PREFIX, version);
290 dev_err(dev, "%s unknown IP hardware version 0x%lx\n",
291 HVA_PREFIX, version);
292 version = HVA_VERSION_UNKNOWN;
299 int hva_hw_probe(struct platform_device *pdev, struct hva_dev *hva)
301 struct device *dev = &pdev->dev;
302 struct resource *regs;
303 struct resource *esram;
308 /* get memory for registers */
309 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
310 hva->regs = devm_ioremap_resource(dev, regs);
311 if (IS_ERR(hva->regs)) {
312 dev_err(dev, "%s failed to get regs\n", HVA_PREFIX);
313 return PTR_ERR(hva->regs);
316 /* get memory for esram */
317 esram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
319 dev_err(dev, "%s failed to get esram\n", HVA_PREFIX);
322 hva->esram_addr = esram->start;
323 hva->esram_size = resource_size(esram);
325 dev_info(dev, "%s esram reserved for address: 0x%x size:%d\n",
326 HVA_PREFIX, hva->esram_addr, hva->esram_size);
328 /* get clock resource */
329 hva->clk = devm_clk_get(dev, "clk_hva");
330 if (IS_ERR(hva->clk)) {
331 dev_err(dev, "%s failed to get clock\n", HVA_PREFIX);
332 return PTR_ERR(hva->clk);
335 ret = clk_prepare(hva->clk);
337 dev_err(dev, "%s failed to prepare clock\n", HVA_PREFIX);
338 hva->clk = ERR_PTR(-EINVAL);
342 /* get status interruption resource */
343 ret = platform_get_irq(pdev, 0);
345 dev_err(dev, "%s failed to get status IRQ\n", HVA_PREFIX);
350 ret = devm_request_threaded_irq(dev, hva->irq_its, hva_hw_its_interrupt,
351 hva_hw_its_irq_thread,
355 dev_err(dev, "%s failed to install status IRQ 0x%x\n",
356 HVA_PREFIX, hva->irq_its);
359 disable_irq(hva->irq_its);
361 /* get error interruption resource */
362 ret = platform_get_irq(pdev, 1);
364 dev_err(dev, "%s failed to get error IRQ\n", HVA_PREFIX);
369 ret = devm_request_threaded_irq(dev, hva->irq_err, hva_hw_err_interrupt,
370 hva_hw_err_irq_thread,
374 dev_err(dev, "%s failed to install error IRQ 0x%x\n",
375 HVA_PREFIX, hva->irq_err);
378 disable_irq(hva->irq_err);
380 /* initialise protection mutex */
381 mutex_init(&hva->protect_mutex);
383 /* initialise completion signal */
384 init_completion(&hva->interrupt);
386 /* initialise runtime power management */
387 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_DELAY_MS);
388 pm_runtime_use_autosuspend(dev);
389 pm_runtime_set_suspended(dev);
390 pm_runtime_enable(dev);
392 ret = pm_runtime_get_sync(dev);
394 dev_err(dev, "%s failed to set PM\n", HVA_PREFIX);
398 /* check IP hardware version */
399 hva->ip_version = hva_hw_get_ip_version(hva);
401 if (hva->ip_version == HVA_VERSION_UNKNOWN) {
406 dev_info(dev, "%s found hva device (version 0x%lx)\n", HVA_PREFIX,
415 clk_unprepare(hva->clk);
420 void hva_hw_remove(struct hva_dev *hva)
422 struct device *dev = hva_to_dev(hva);
424 disable_irq(hva->irq_its);
425 disable_irq(hva->irq_err);
427 pm_runtime_put_autosuspend(dev);
428 pm_runtime_disable(dev);
431 int hva_hw_runtime_suspend(struct device *dev)
433 struct hva_dev *hva = dev_get_drvdata(dev);
435 clk_disable_unprepare(hva->clk);
440 int hva_hw_runtime_resume(struct device *dev)
442 struct hva_dev *hva = dev_get_drvdata(dev);
444 if (clk_prepare_enable(hva->clk)) {
445 dev_err(hva->dev, "%s failed to prepare hva clk\n",
450 if (clk_set_rate(hva->clk, CLK_RATE)) {
451 dev_err(dev, "%s failed to set clock frequency\n",
459 int hva_hw_execute_task(struct hva_ctx *ctx, enum hva_hw_cmd_type cmd,
460 struct hva_buffer *task)
462 struct hva_dev *hva = ctx_to_hdev(ctx);
463 struct device *dev = hva_to_dev(hva);
464 u8 client_id = ctx->id;
468 mutex_lock(&hva->protect_mutex);
471 enable_irq(hva->irq_its);
472 enable_irq(hva->irq_err);
474 if (pm_runtime_get_sync(dev) < 0) {
475 dev_err(dev, "%s failed to get pm_runtime\n", ctx->name);
481 reg = readl_relaxed(hva->regs + HVA_HIF_REG_CLK_GATING);
484 reg |= CLK_GATING_HVC;
487 dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
488 ctx->encode_errors++;
492 writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
494 dev_dbg(dev, "%s %s: write configuration registers\n", ctx->name,
497 /* byte swap config */
498 writel_relaxed(BSM_CFG_VAL1, hva->regs + HVA_HIF_REG_BSM);
500 /* define Max Opcode Size and Max Message Size for LMI and EMI */
501 writel_relaxed(MIF_CFG_VAL3, hva->regs + HVA_HIF_REG_MIF_CFG);
502 writel_relaxed(HEC_MIF_CFG_VAL, hva->regs + HVA_HIF_REG_HEC_MIF_CFG);
505 * command FIFO: task_id[31:16] client_id[15:8] command_type[7:0]
506 * the context identifier is provided as client identifier to the
507 * hardware, and is retrieved in the interrupt functions from the
510 dev_dbg(dev, "%s %s: send task (cmd: %d, task_desc: %pad)\n",
511 ctx->name, __func__, cmd + (client_id << 8), &task->paddr);
512 writel_relaxed(cmd + (client_id << 8), hva->regs + HVA_HIF_FIFO_CMD);
513 writel_relaxed(task->paddr, hva->regs + HVA_HIF_FIFO_CMD);
515 if (!wait_for_completion_timeout(&hva->interrupt,
516 msecs_to_jiffies(2000))) {
517 dev_err(dev, "%s %s: time out on completion\n", ctx->name,
519 ctx->encode_errors++;
524 /* get encoding status */
525 ret = ctx->hw_err ? -EFAULT : 0;
527 ctx->encode_errors += ctx->hw_err ? 1 : 0;
530 disable_irq(hva->irq_its);
531 disable_irq(hva->irq_err);
535 reg &= ~CLK_GATING_HVC;
536 writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
539 dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
542 pm_runtime_put_autosuspend(dev);
543 mutex_unlock(&hva->protect_mutex);
548 #ifdef CONFIG_VIDEO_STI_HVA_DEBUGFS
549 #define DUMP(reg) seq_printf(s, "%-30s: 0x%08X\n",\
550 #reg, readl_relaxed(hva->regs + reg))
552 void hva_hw_dump_regs(struct hva_dev *hva, struct seq_file *s)
554 struct device *dev = hva_to_dev(hva);
556 mutex_lock(&hva->protect_mutex);
558 if (pm_runtime_get_sync(dev) < 0) {
559 seq_puts(s, "Cannot wake up IP\n");
560 pm_runtime_put_noidle(dev);
561 mutex_unlock(&hva->protect_mutex);
565 seq_printf(s, "Registers:\nReg @ = 0x%p\n", hva->regs);
567 DUMP(HVA_HIF_REG_RST);
568 DUMP(HVA_HIF_REG_RST_ACK);
569 DUMP(HVA_HIF_REG_MIF_CFG);
570 DUMP(HVA_HIF_REG_HEC_MIF_CFG);
571 DUMP(HVA_HIF_REG_CFL);
572 DUMP(HVA_HIF_REG_SFL);
573 DUMP(HVA_HIF_REG_LMI_ERR);
574 DUMP(HVA_HIF_REG_EMI_ERR);
575 DUMP(HVA_HIF_REG_HEC_MIF_ERR);
576 DUMP(HVA_HIF_REG_HEC_STS);
577 DUMP(HVA_HIF_REG_HVC_STS);
578 DUMP(HVA_HIF_REG_HJE_STS);
579 DUMP(HVA_HIF_REG_CNT);
580 DUMP(HVA_HIF_REG_HEC_CHKSYN_DIS);
581 DUMP(HVA_HIF_REG_CLK_GATING);
582 DUMP(HVA_HIF_REG_VERSION);
584 pm_runtime_put_autosuspend(dev);
585 mutex_unlock(&hva->protect_mutex);