2 * Copyright (C) STMicroelectronics SA 2015
3 * Authors: Yannick Fertre <yannick.fertre@st.com>
4 * Hugues Fruchet <hugues.fruchet@st.com>
5 * License terms: GNU General Public License (GPL), version 2
9 #include <linux/interrupt.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
16 /* HVA register offsets */
17 #define HVA_HIF_REG_RST 0x0100U
18 #define HVA_HIF_REG_RST_ACK 0x0104U
19 #define HVA_HIF_REG_MIF_CFG 0x0108U
20 #define HVA_HIF_REG_HEC_MIF_CFG 0x010CU
21 #define HVA_HIF_REG_CFL 0x0110U
22 #define HVA_HIF_FIFO_CMD 0x0114U
23 #define HVA_HIF_FIFO_STS 0x0118U
24 #define HVA_HIF_REG_SFL 0x011CU
25 #define HVA_HIF_REG_IT_ACK 0x0120U
26 #define HVA_HIF_REG_ERR_IT_ACK 0x0124U
27 #define HVA_HIF_REG_LMI_ERR 0x0128U
28 #define HVA_HIF_REG_EMI_ERR 0x012CU
29 #define HVA_HIF_REG_HEC_MIF_ERR 0x0130U
30 #define HVA_HIF_REG_HEC_STS 0x0134U
31 #define HVA_HIF_REG_HVC_STS 0x0138U
32 #define HVA_HIF_REG_HJE_STS 0x013CU
33 #define HVA_HIF_REG_CNT 0x0140U
34 #define HVA_HIF_REG_HEC_CHKSYN_DIS 0x0144U
35 #define HVA_HIF_REG_CLK_GATING 0x0148U
36 #define HVA_HIF_REG_VERSION 0x014CU
37 #define HVA_HIF_REG_BSM 0x0150U
39 /* define value for version id register (HVA_HIF_REG_VERSION) */
40 #define VERSION_ID_MASK 0x0000FFFF
42 /* define values for BSM register (HVA_HIF_REG_BSM) */
43 #define BSM_CFG_VAL1 0x0003F000
44 #define BSM_CFG_VAL2 0x003F0000
46 /* define values for memory interface register (HVA_HIF_REG_MIF_CFG) */
47 #define MIF_CFG_VAL1 0x04460446
48 #define MIF_CFG_VAL2 0x04460806
49 #define MIF_CFG_VAL3 0x00000000
51 /* define value for HEC memory interface register (HVA_HIF_REG_MIF_CFG) */
52 #define HEC_MIF_CFG_VAL 0x000000C4
54 /* Bits definition for clock gating register (HVA_HIF_REG_CLK_GATING) */
55 #define CLK_GATING_HVC BIT(0)
56 #define CLK_GATING_HEC BIT(1)
57 #define CLK_GATING_HJE BIT(2)
59 /* fix hva clock rate */
60 #define CLK_RATE 300000000
62 /* fix delay for pmruntime */
63 #define AUTOSUSPEND_DELAY_MS 3
66 * hw encode error values
67 * NO_ERROR: Success, Task OK
68 * H264_BITSTREAM_OVERSIZE: VECH264 Bitstream size > bitstream buffer
69 * H264_FRAME_SKIPPED: VECH264 Frame skipped (refers to CPB Buffer Size)
70 * H264_SLICE_LIMIT_SIZE: VECH264 MB > slice limit size
71 * H264_MAX_SLICE_NUMBER: VECH264 max slice number reached
72 * H264_SLICE_READY: VECH264 Slice ready
73 * TASK_LIST_FULL: HVA/FPC task list full
74 (discard latest transform command)
75 * UNKNOWN_COMMAND: Transform command not known by HVA/FPC
76 * WRONG_CODEC_OR_RESOLUTION: Wrong Codec or Resolution Selection
77 * NO_INT_COMPLETION: Time-out on interrupt completion
78 * LMI_ERR: Local Memory Interface Error
79 * EMI_ERR: External Memory Interface Error
80 * HECMI_ERR: HEC Memory Interface Error
84 H264_BITSTREAM_OVERSIZE = 0x2,
85 H264_FRAME_SKIPPED = 0x4,
86 H264_SLICE_LIMIT_SIZE = 0x5,
87 H264_MAX_SLICE_NUMBER = 0x7,
88 H264_SLICE_READY = 0x8,
89 TASK_LIST_FULL = 0xF0,
90 UNKNOWN_COMMAND = 0xF1,
91 WRONG_CODEC_OR_RESOLUTION = 0xF4,
92 NO_INT_COMPLETION = 0x100,
98 static irqreturn_t hva_hw_its_interrupt(int irq, void *data)
100 struct hva_dev *hva = data;
102 /* read status registers */
103 hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
104 hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
106 /* acknowledge interruption */
107 writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
109 return IRQ_WAKE_THREAD;
112 static irqreturn_t hva_hw_its_irq_thread(int irq, void *arg)
114 struct hva_dev *hva = arg;
115 struct device *dev = hva_to_dev(hva);
116 u32 status = hva->sts_reg & 0xFF;
118 struct hva_ctx *ctx = NULL;
120 dev_dbg(dev, "%s %s: status: 0x%02x fifo level: 0x%02x\n",
121 HVA_PREFIX, __func__, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
124 * status: task_id[31:16] client_id[15:8] status[7:0]
125 * the context identifier is retrieved from the client identifier
127 ctx_id = (hva->sts_reg & 0xFF00) >> 8;
128 if (ctx_id >= HVA_MAX_INSTANCES) {
129 dev_err(dev, "%s %s: bad context identifier: %d\n",
130 HVA_PREFIX, __func__, ctx_id);
134 ctx = hva->instances[ctx_id];
140 dev_dbg(dev, "%s %s: no error\n",
141 ctx->name, __func__);
144 case H264_SLICE_READY:
145 dev_dbg(dev, "%s %s: h264 slice ready\n",
146 ctx->name, __func__);
149 case H264_FRAME_SKIPPED:
150 dev_dbg(dev, "%s %s: h264 frame skipped\n",
151 ctx->name, __func__);
154 case H264_BITSTREAM_OVERSIZE:
155 dev_err(dev, "%s %s:h264 bitstream oversize\n",
156 ctx->name, __func__);
159 case H264_SLICE_LIMIT_SIZE:
160 dev_err(dev, "%s %s: h264 slice limit size is reached\n",
161 ctx->name, __func__);
164 case H264_MAX_SLICE_NUMBER:
165 dev_err(dev, "%s %s: h264 max slice number is reached\n",
166 ctx->name, __func__);
170 dev_err(dev, "%s %s:task list full\n",
171 ctx->name, __func__);
174 case UNKNOWN_COMMAND:
175 dev_err(dev, "%s %s: command not known\n",
176 ctx->name, __func__);
179 case WRONG_CODEC_OR_RESOLUTION:
180 dev_err(dev, "%s %s: wrong codec or resolution\n",
181 ctx->name, __func__);
185 dev_err(dev, "%s %s: status not recognized\n",
186 ctx->name, __func__);
191 complete(&hva->interrupt);
196 static irqreturn_t hva_hw_err_interrupt(int irq, void *data)
198 struct hva_dev *hva = data;
200 /* read status registers */
201 hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
202 hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
204 /* read error registers */
205 hva->lmi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_LMI_ERR);
206 hva->emi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_EMI_ERR);
207 hva->hec_mif_err_reg = readl_relaxed(hva->regs +
208 HVA_HIF_REG_HEC_MIF_ERR);
210 /* acknowledge interruption */
211 writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
213 return IRQ_WAKE_THREAD;
216 static irqreturn_t hva_hw_err_irq_thread(int irq, void *arg)
218 struct hva_dev *hva = arg;
219 struct device *dev = hva_to_dev(hva);
223 dev_dbg(dev, "%s status: 0x%02x fifo level: 0x%02x\n",
224 HVA_PREFIX, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
227 * status: task_id[31:16] client_id[15:8] status[7:0]
228 * the context identifier is retrieved from the client identifier
230 ctx_id = (hva->sts_reg & 0xFF00) >> 8;
231 if (ctx_id >= HVA_MAX_INSTANCES) {
232 dev_err(dev, "%s bad context identifier: %d\n", HVA_PREFIX,
237 ctx = hva->instances[ctx_id];
241 if (hva->lmi_err_reg) {
242 dev_err(dev, "%s local memory interface error: 0x%08x\n",
243 ctx->name, hva->lmi_err_reg);
247 if (hva->lmi_err_reg) {
248 dev_err(dev, "%s external memory interface error: 0x%08x\n",
249 ctx->name, hva->emi_err_reg);
253 if (hva->hec_mif_err_reg) {
254 dev_err(dev, "%s hec memory interface error: 0x%08x\n",
255 ctx->name, hva->hec_mif_err_reg);
259 complete(&hva->interrupt);
264 static unsigned long int hva_hw_get_ip_version(struct hva_dev *hva)
266 struct device *dev = hva_to_dev(hva);
267 unsigned long int version;
269 if (pm_runtime_get_sync(dev) < 0) {
270 dev_err(dev, "%s failed to get pm_runtime\n", HVA_PREFIX);
271 mutex_unlock(&hva->protect_mutex);
275 version = readl_relaxed(hva->regs + HVA_HIF_REG_VERSION) &
278 pm_runtime_put_autosuspend(dev);
281 case HVA_VERSION_V400:
282 dev_dbg(dev, "%s IP hardware version 0x%lx\n",
283 HVA_PREFIX, version);
286 dev_err(dev, "%s unknown IP hardware version 0x%lx\n",
287 HVA_PREFIX, version);
288 version = HVA_VERSION_UNKNOWN;
295 int hva_hw_probe(struct platform_device *pdev, struct hva_dev *hva)
297 struct device *dev = &pdev->dev;
298 struct resource *regs;
299 struct resource *esram;
304 /* get memory for registers */
305 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
306 hva->regs = devm_ioremap_resource(dev, regs);
307 if (IS_ERR(hva->regs)) {
308 dev_err(dev, "%s failed to get regs\n", HVA_PREFIX);
309 return PTR_ERR(hva->regs);
312 /* get memory for esram */
313 esram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
315 dev_err(dev, "%s failed to get esram\n", HVA_PREFIX);
318 hva->esram_addr = esram->start;
319 hva->esram_size = resource_size(esram);
321 dev_info(dev, "%s esram reserved for address: 0x%x size:%d\n",
322 HVA_PREFIX, hva->esram_addr, hva->esram_size);
324 /* get clock resource */
325 hva->clk = devm_clk_get(dev, "clk_hva");
326 if (IS_ERR(hva->clk)) {
327 dev_err(dev, "%s failed to get clock\n", HVA_PREFIX);
328 return PTR_ERR(hva->clk);
331 ret = clk_prepare(hva->clk);
333 dev_err(dev, "%s failed to prepare clock\n", HVA_PREFIX);
334 hva->clk = ERR_PTR(-EINVAL);
338 /* get status interruption resource */
339 ret = platform_get_irq(pdev, 0);
341 dev_err(dev, "%s failed to get status IRQ\n", HVA_PREFIX);
346 ret = devm_request_threaded_irq(dev, hva->irq_its, hva_hw_its_interrupt,
347 hva_hw_its_irq_thread,
351 dev_err(dev, "%s failed to install status IRQ 0x%x\n",
352 HVA_PREFIX, hva->irq_its);
355 disable_irq(hva->irq_its);
357 /* get error interruption resource */
358 ret = platform_get_irq(pdev, 1);
360 dev_err(dev, "%s failed to get error IRQ\n", HVA_PREFIX);
365 ret = devm_request_threaded_irq(dev, hva->irq_err, hva_hw_err_interrupt,
366 hva_hw_err_irq_thread,
370 dev_err(dev, "%s failed to install error IRQ 0x%x\n",
371 HVA_PREFIX, hva->irq_err);
374 disable_irq(hva->irq_err);
376 /* initialise protection mutex */
377 mutex_init(&hva->protect_mutex);
379 /* initialise completion signal */
380 init_completion(&hva->interrupt);
382 /* initialise runtime power management */
383 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_DELAY_MS);
384 pm_runtime_use_autosuspend(dev);
385 pm_runtime_set_suspended(dev);
386 pm_runtime_enable(dev);
388 ret = pm_runtime_get_sync(dev);
390 dev_err(dev, "%s failed to set PM\n", HVA_PREFIX);
394 /* check IP hardware version */
395 hva->ip_version = hva_hw_get_ip_version(hva);
397 if (hva->ip_version == HVA_VERSION_UNKNOWN) {
402 dev_info(dev, "%s found hva device (version 0x%lx)\n", HVA_PREFIX,
411 clk_unprepare(hva->clk);
416 void hva_hw_remove(struct hva_dev *hva)
418 struct device *dev = hva_to_dev(hva);
420 disable_irq(hva->irq_its);
421 disable_irq(hva->irq_err);
423 pm_runtime_put_autosuspend(dev);
424 pm_runtime_disable(dev);
427 int hva_hw_runtime_suspend(struct device *dev)
429 struct hva_dev *hva = dev_get_drvdata(dev);
431 clk_disable_unprepare(hva->clk);
436 int hva_hw_runtime_resume(struct device *dev)
438 struct hva_dev *hva = dev_get_drvdata(dev);
440 if (clk_prepare_enable(hva->clk)) {
441 dev_err(hva->dev, "%s failed to prepare hva clk\n",
446 if (clk_set_rate(hva->clk, CLK_RATE)) {
447 dev_err(dev, "%s failed to set clock frequency\n",
455 int hva_hw_execute_task(struct hva_ctx *ctx, enum hva_hw_cmd_type cmd,
456 struct hva_buffer *task)
458 struct hva_dev *hva = ctx_to_hdev(ctx);
459 struct device *dev = hva_to_dev(hva);
460 u8 client_id = ctx->id;
464 mutex_lock(&hva->protect_mutex);
467 enable_irq(hva->irq_its);
468 enable_irq(hva->irq_err);
470 if (pm_runtime_get_sync(dev) < 0) {
471 dev_err(dev, "%s failed to get pm_runtime\n", ctx->name);
476 reg = readl_relaxed(hva->regs + HVA_HIF_REG_CLK_GATING);
479 reg |= CLK_GATING_HVC;
482 dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
486 writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
488 dev_dbg(dev, "%s %s: write configuration registers\n", ctx->name,
491 /* byte swap config */
492 writel_relaxed(BSM_CFG_VAL1, hva->regs + HVA_HIF_REG_BSM);
494 /* define Max Opcode Size and Max Message Size for LMI and EMI */
495 writel_relaxed(MIF_CFG_VAL3, hva->regs + HVA_HIF_REG_MIF_CFG);
496 writel_relaxed(HEC_MIF_CFG_VAL, hva->regs + HVA_HIF_REG_HEC_MIF_CFG);
499 * command FIFO: task_id[31:16] client_id[15:8] command_type[7:0]
500 * the context identifier is provided as client identifier to the
501 * hardware, and is retrieved in the interrupt functions from the
504 dev_dbg(dev, "%s %s: send task (cmd: %d, task_desc: %pad)\n",
505 ctx->name, __func__, cmd + (client_id << 8), &task->paddr);
506 writel_relaxed(cmd + (client_id << 8), hva->regs + HVA_HIF_FIFO_CMD);
507 writel_relaxed(task->paddr, hva->regs + HVA_HIF_FIFO_CMD);
509 if (!wait_for_completion_timeout(&hva->interrupt,
510 msecs_to_jiffies(2000))) {
511 dev_err(dev, "%s %s: time out on completion\n", ctx->name,
517 /* get encoding status */
518 ret = ctx->hw_err ? -EFAULT : 0;
521 disable_irq(hva->irq_its);
522 disable_irq(hva->irq_err);
526 reg &= ~CLK_GATING_HVC;
527 writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
530 dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
533 pm_runtime_put_autosuspend(dev);
534 mutex_unlock(&hva->protect_mutex);