drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * c8sectpfe-core.c - C8SECTPFE STi DVB driver
   4  *
   5  * Copyright (c) STMicroelectronics 2015
   6  *
   7  *   Author:Peter Bennett <peter.bennett@st.com>
   8  *          Peter Griffin <peter.griffin@linaro.org>
   9  *
  10  */
  11 #include <linux/atomic.h>
  12 #include <linux/clk.h>
  13 #include <linux/completion.h>
  14 #include <linux/delay.h>
  15 #include <linux/device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dvb/dmx.h>
  18 #include <linux/dvb/frontend.h>
  19 #include <linux/errno.h>
  20 #include <linux/firmware.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/usb.h>
  29 #include <linux/slab.h>
  30 #include <linux/time.h>
  31 #include <linux/version.h>
  32 #include <linux/wait.h>
  33 #include <linux/pinctrl/pinctrl.h>
  34
  35 #include "c8sectpfe-core.h"
  36 #include "c8sectpfe-common.h"
  37 #include "c8sectpfe-debugfs.h"
  38 #include <media/dmxdev.h>
  39 #include <media/dvb_demux.h>
  40 #include <media/dvb_frontend.h>
  41 #include <media/dvb_net.h>
  42
  43 #define FIRMWARE_MEMDMA "/*(DEBLOBBED)*/"
  44 /*(DEBLOBBED)*/
  45
  46 #define PID_TABLE_SIZE 1024
  47 #define POLL_MSECS 50
  48
  49 static int load_c8sectpfe_fw(struct c8sectpfei *fei);
  50
  51 #define TS_PKT_SIZE 188
  52 #define HEADER_SIZE (4)
  53 #define PACKET_SIZE (TS_PKT_SIZE+HEADER_SIZE)
  54
  55 #define FEI_ALIGNMENT (32)
  56 /* hw requires minimum of 8*PACKET_SIZE and padded to 8byte boundary */
  57 #define FEI_BUFFER_SIZE (8*PACKET_SIZE*340)
  58
  59 #define FIFO_LEN 1024
  60
  61 static void c8sectpfe_timer_interrupt(struct timer_list *t)
  62 {
  63         struct c8sectpfei *fei = from_timer(fei, t, timer);
  64         struct channel_info *channel;
  65         int chan_num;
  66
  67         /* iterate through input block channels */
  68         for (chan_num = 0; chan_num < fei->tsin_count; chan_num++) {
  69                 channel = fei->channel_data[chan_num];
  70
  71                 /* is this descriptor initialised and TP enabled */
  72                 if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE))
  73                         tasklet_schedule(&channel->tsklet);
  74         }
  75
  76         fei->timer.expires = jiffies +  msecs_to_jiffies(POLL_MSECS);
  77         add_timer(&fei->timer);
  78 }
  79
  80 static void channel_swdemux_tsklet(struct tasklet_struct *t)
  81 {
  82         struct channel_info *channel = from_tasklet(channel, t, tsklet);
  83         struct c8sectpfei *fei;
  84         unsigned long wp, rp;
  85         int pos, num_packets, n, size;
  86         u8 *buf;
  87
  88         if (unlikely(!channel || !channel->irec))
  89                 return;
  90
  91         fei = channel->fei;
  92
  93         wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0));
  94         rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0));
  95
  96         pos = rp - channel->back_buffer_busaddr;
  97
  98         /* has it wrapped */
  99         if (wp < rp)
 100                 wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE;
 101
 102         size = wp - rp;
 103         num_packets = size / PACKET_SIZE;
 104
 105         /* manage cache so data is visible to CPU */
 106         dma_sync_single_for_cpu(fei->dev,
 107                                 rp,
 108                                 size,
 109                                 DMA_FROM_DEVICE);
 110
 111         buf = (u8 *) channel->back_buffer_aligned;
 112
 113         dev_dbg(fei->dev,
 114                 "chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n",
 115                 channel->tsin_id, channel, num_packets, buf, pos, rp, wp);
 116
 117         for (n = 0; n < num_packets; n++) {
 118                 dvb_dmx_swfilter_packets(
 119                         &fei->c8sectpfe[0]->
 120                                 demux[channel->demux_mapping].dvb_demux,
 121                         &buf[pos], 1);
 122
 123                 pos += PACKET_SIZE;
 124         }
 125
 126         /* advance the read pointer */
 127         if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE))
 128                 writel(channel->back_buffer_busaddr, channel->irec +
 129                         DMA_PRDS_BUSRP_TP(0));
 130         else
 131                 writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0));
 132 }
 133
 134 static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 135 {
 136         struct dvb_demux *demux = dvbdmxfeed->demux;
 137         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 138         struct c8sectpfei *fei = stdemux->c8sectpfei;
 139         struct channel_info *channel;
 140         u32 tmp;
 141         unsigned long *bitmap;
 142         int ret;
 143
 144         switch (dvbdmxfeed->type) {
 145         case DMX_TYPE_TS:
 146                 break;
 147         case DMX_TYPE_SEC:
 148                 break;
 149         default:
 150                 dev_err(fei->dev, "%s:%d Error bailing\n"
 151                         , __func__, __LINE__);
 152                 return -EINVAL;
 153         }
 154
 155         if (dvbdmxfeed->type == DMX_TYPE_TS) {
 156                 switch (dvbdmxfeed->pes_type) {
 157                 case DMX_PES_VIDEO:
 158                 case DMX_PES_AUDIO:
 159                 case DMX_PES_TELETEXT:
 160                 case DMX_PES_PCR:
 161                 case DMX_PES_OTHER:
 162                         break;
 163                 default:
 164                         dev_err(fei->dev, "%s:%d Error bailing\n"
 165                                 , __func__, __LINE__);
 166                         return -EINVAL;
 167                 }
 168         }
 169
 170         if (!atomic_read(&fei->fw_loaded)) {
 171                 ret = load_c8sectpfe_fw(fei);
 172                 if (ret)
 173                         return ret;
 174         }
 175
 176         mutex_lock(&fei->lock);
 177
 178         channel = fei->channel_data[stdemux->tsin_index];
 179
 180         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 181
 182         /* 8192 is a special PID */
 183         if (dvbdmxfeed->pid == 8192) {
 184                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 185                 tmp &= ~C8SECTPFE_PID_ENABLE;
 186                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 187
 188         } else {
 189                 bitmap_set(bitmap, dvbdmxfeed->pid, 1);
 190         }
 191
 192         /* manage cache so PID bitmap is visible to HW */
 193         dma_sync_single_for_device(fei->dev,
 194                                         channel->pid_buffer_busaddr,
 195                                         PID_TABLE_SIZE,
 196                                         DMA_TO_DEVICE);
 197
 198         channel->active = 1;
 199
 200         if (fei->global_feed_count == 0) {
 201                 fei->timer.expires = jiffies +
 202                         msecs_to_jiffies(msecs_to_jiffies(POLL_MSECS));
 203
 204                 add_timer(&fei->timer);
 205         }
 206
 207         if (stdemux->running_feed_count == 0) {
 208
 209                 dev_dbg(fei->dev, "Starting channel=%p\n", channel);
 210
 211                 tasklet_setup(&channel->tsklet, channel_swdemux_tsklet);
 212
 213                 /* Reset the internal inputblock sram pointers */
 214                 writel(channel->fifo,
 215                         fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id));
 216                 writel(channel->fifo + FIFO_LEN - 1,
 217                         fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id));
 218
 219                 writel(channel->fifo,
 220                         fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id));
 221                 writel(channel->fifo,
 222                         fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id));
 223
 224
 225                 /* reset read / write memdma ptrs for this channel */
 226                 writel(channel->back_buffer_busaddr, channel->irec +
 227                         DMA_PRDS_BUSBASE_TP(0));
 228
 229                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 230                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 231
 232                 writel(channel->back_buffer_busaddr, channel->irec +
 233                         DMA_PRDS_BUSWP_TP(0));
 234
 235                 /* Issue a reset and enable InputBlock */
 236                 writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET
 237                         , fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 238
 239                 /* and enable the tp */
 240                 writel(0x1, channel->irec + DMA_PRDS_TPENABLE);
 241
 242                 dev_dbg(fei->dev, "%s:%d Starting DMA feed on stdemux=%p\n"
 243                         , __func__, __LINE__, stdemux);
 244         }
 245
 246         stdemux->running_feed_count++;
 247         fei->global_feed_count++;
 248
 249         mutex_unlock(&fei->lock);
 250
 251         return 0;
 252 }
 253
 254 static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 255 {
 256
 257         struct dvb_demux *demux = dvbdmxfeed->demux;
 258         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 259         struct c8sectpfei *fei = stdemux->c8sectpfei;
 260         struct channel_info *channel;
 261         int idlereq;
 262         u32 tmp;
 263         int ret;
 264         unsigned long *bitmap;
 265
 266         if (!atomic_read(&fei->fw_loaded)) {
 267                 ret = load_c8sectpfe_fw(fei);
 268                 if (ret)
 269                         return ret;
 270         }
 271
 272         mutex_lock(&fei->lock);
 273
 274         channel = fei->channel_data[stdemux->tsin_index];
 275
 276         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 277
 278         if (dvbdmxfeed->pid == 8192) {
 279                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 280                 tmp |= C8SECTPFE_PID_ENABLE;
 281                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 282         } else {
 283                 bitmap_clear(bitmap, dvbdmxfeed->pid, 1);
 284         }
 285
 286         /* manage cache so data is visible to HW */
 287         dma_sync_single_for_device(fei->dev,
 288                                         channel->pid_buffer_busaddr,
 289                                         PID_TABLE_SIZE,
 290                                         DMA_TO_DEVICE);
 291
 292         if (--stdemux->running_feed_count == 0) {
 293
 294                 channel = fei->channel_data[stdemux->tsin_index];
 295
 296                 /* TP re-configuration on page 168 of functional spec */
 297
 298                 /* disable IB (prevents more TS data going to memdma) */
 299                 writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 300
 301                 /* disable this channels descriptor */
 302                 writel(0,  channel->irec + DMA_PRDS_TPENABLE);
 303
 304                 tasklet_disable(&channel->tsklet);
 305
 306                 /* now request memdma channel goes idle */
 307                 idlereq = (1 << channel->tsin_id) | IDLEREQ;
 308                 writel(idlereq, fei->io + DMA_IDLE_REQ);
 309
 310                 /* wait for idle irq handler to signal completion */
 311                 ret = wait_for_completion_timeout(&channel->idle_completion,
 312                                                 msecs_to_jiffies(100));
 313
 314                 if (ret == 0)
 315                         dev_warn(fei->dev,
 316                                 "Timeout waiting for idle irq on tsin%d\n",
 317                                 channel->tsin_id);
 318
 319                 reinit_completion(&channel->idle_completion);
 320
 321                 /* reset read / write ptrs for this channel */
 322
 323                 writel(channel->back_buffer_busaddr,
 324                         channel->irec + DMA_PRDS_BUSBASE_TP(0));
 325
 326                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 327                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 328
 329                 writel(channel->back_buffer_busaddr,
 330                         channel->irec + DMA_PRDS_BUSWP_TP(0));
 331
 332                 dev_dbg(fei->dev,
 333                         "%s:%d stopping DMA feed on stdemux=%p channel=%d\n",
 334                         __func__, __LINE__, stdemux, channel->tsin_id);
 335
 336                 /* turn off all PIDS in the bitmap */
 337                 memset((void *)channel->pid_buffer_aligned
 338                         , 0x00, PID_TABLE_SIZE);
 339
 340                 /* manage cache so data is visible to HW */
 341                 dma_sync_single_for_device(fei->dev,
 342                                         channel->pid_buffer_busaddr,
 343                                         PID_TABLE_SIZE,
 344                                         DMA_TO_DEVICE);
 345
 346                 channel->active = 0;
 347         }
 348
 349         if (--fei->global_feed_count == 0) {
 350                 dev_dbg(fei->dev, "%s:%d global_feed_count=%d\n"
 351                         , __func__, __LINE__, fei->global_feed_count);
 352
 353                 del_timer(&fei->timer);
 354         }
 355
 356         mutex_unlock(&fei->lock);
 357
 358         return 0;
 359 }
 360
 361 static struct channel_info *find_channel(struct c8sectpfei *fei, int tsin_num)
 362 {
 363         int i;
 364
 365         for (i = 0; i < C8SECTPFE_MAX_TSIN_CHAN; i++) {
 366                 if (!fei->channel_data[i])
 367                         continue;
 368
 369                 if (fei->channel_data[i]->tsin_id == tsin_num)
 370                         return fei->channel_data[i];
 371         }
 372
 373         return NULL;
 374 }
 375
 376 static void c8sectpfe_getconfig(struct c8sectpfei *fei)
 377 {
 378         struct c8sectpfe_hw *hw = &fei->hw_stats;
 379
 380         hw->num_ib = readl(fei->io + SYS_CFG_NUM_IB);
 381         hw->num_mib = readl(fei->io + SYS_CFG_NUM_MIB);
 382         hw->num_swts = readl(fei->io + SYS_CFG_NUM_SWTS);
 383         hw->num_tsout = readl(fei->io + SYS_CFG_NUM_TSOUT);
 384         hw->num_ccsc = readl(fei->io + SYS_CFG_NUM_CCSC);
 385         hw->num_ram = readl(fei->io + SYS_CFG_NUM_RAM);
 386         hw->num_tp = readl(fei->io + SYS_CFG_NUM_TP);
 387
 388         dev_info(fei->dev, "C8SECTPFE hw supports the following:\n");
 389         dev_info(fei->dev, "Input Blocks: %d\n", hw->num_ib);
 390         dev_info(fei->dev, "Merged Input Blocks: %d\n", hw->num_mib);
 391         dev_info(fei->dev, "Software Transport Stream Inputs: %d\n"
 392                                 , hw->num_swts);
 393         dev_info(fei->dev, "Transport Stream Output: %d\n", hw->num_tsout);
 394         dev_info(fei->dev, "Cable Card Converter: %d\n", hw->num_ccsc);
 395         dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram);
 396         dev_info(fei->dev, "Tango TPs supported by C8SECTPFE: %d\n"
 397                         , hw->num_tp);
 398 }
 399
 400 static irqreturn_t c8sectpfe_idle_irq_handler(int irq, void *priv)
 401 {
 402         struct c8sectpfei *fei = priv;
 403         struct channel_info *chan;
 404         int bit;
 405         unsigned long tmp = readl(fei->io + DMA_IDLE_REQ);
 406
 407         /* page 168 of functional spec: Clear the idle request
 408            by writing 0 to the C8SECTPFE_DMA_IDLE_REQ register. */
 409
 410         /* signal idle completion */
 411         for_each_set_bit(bit, &tmp, fei->hw_stats.num_ib) {
 412
 413                 chan = find_channel(fei, bit);
 414
 415                 if (chan)
 416                         complete(&chan->idle_completion);
 417         }
 418
 419         writel(0, fei->io + DMA_IDLE_REQ);
 420
 421         return IRQ_HANDLED;
 422 }
 423
 424
 425 static void free_input_block(struct c8sectpfei *fei, struct channel_info *tsin)
 426 {
 427         if (!fei || !tsin)
 428                 return;
 429
 430         if (tsin->back_buffer_busaddr)
 431                 if (!dma_mapping_error(fei->dev, tsin->back_buffer_busaddr))
 432                         dma_unmap_single(fei->dev, tsin->back_buffer_busaddr,
 433                                 FEI_BUFFER_SIZE, DMA_BIDIRECTIONAL);
 434
 435         kfree(tsin->back_buffer_start);
 436
 437         if (tsin->pid_buffer_busaddr)
 438                 if (!dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr))
 439                         dma_unmap_single(fei->dev, tsin->pid_buffer_busaddr,
 440                                 PID_TABLE_SIZE, DMA_BIDIRECTIONAL);
 441
 442         kfree(tsin->pid_buffer_start);
 443 }
 444
 445 #define MAX_NAME 20
 446
 447 static int configure_memdma_and_inputblock(struct c8sectpfei *fei,
 448                                 struct channel_info *tsin)
 449 {
 450         int ret;
 451         u32 tmp;
 452         char tsin_pin_name[MAX_NAME];
 453
 454         if (!fei || !tsin)
 455                 return -EINVAL;
 456
 457         dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n"
 458                 , __func__, __LINE__, tsin, tsin->tsin_id);
 459
 460         init_completion(&tsin->idle_completion);
 461
 462         tsin->back_buffer_start = kzalloc(FEI_BUFFER_SIZE +
 463                                         FEI_ALIGNMENT, GFP_KERNEL);
 464
 465         if (!tsin->back_buffer_start) {
 466                 ret = -ENOMEM;
 467                 goto err_unmap;
 468         }
 469
 470         /* Ensure backbuffer is 32byte aligned */
 471         tsin->back_buffer_aligned = tsin->back_buffer_start
 472                 + FEI_ALIGNMENT;
 473
 474         tsin->back_buffer_aligned = (void *)
 475                 (((uintptr_t) tsin->back_buffer_aligned) & ~0x1F);
 476
 477         tsin->back_buffer_busaddr = dma_map_single(fei->dev,
 478                                         (void *)tsin->back_buffer_aligned,
 479                                         FEI_BUFFER_SIZE,
 480                                         DMA_BIDIRECTIONAL);
 481
 482         if (dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) {
 483                 dev_err(fei->dev, "failed to map back_buffer\n");
 484                 ret = -EFAULT;
 485                 goto err_unmap;
 486         }
 487
 488         /*
 489          * The pid buffer can be configured (in hw) for byte or bit
 490          * per pid. By powers of deduction we conclude stih407 family
 491          * is configured (at SoC design stage) for bit per pid.
 492          */
 493         tsin->pid_buffer_start = kzalloc(2048, GFP_KERNEL);
 494
 495         if (!tsin->pid_buffer_start) {
 496                 ret = -ENOMEM;
 497                 goto err_unmap;
 498         }
 499
 500         /*
 501          * PID buffer needs to be aligned to size of the pid table
 502          * which at bit per pid is 1024 bytes (8192 pids / 8).
 503          * PIDF_BASE register enforces this alignment when writing
 504          * the register.
 505          */
 506
 507         tsin->pid_buffer_aligned = tsin->pid_buffer_start +
 508                 PID_TABLE_SIZE;
 509
 510         tsin->pid_buffer_aligned = (void *)
 511                 (((uintptr_t) tsin->pid_buffer_aligned) & ~0x3ff);
 512
 513         tsin->pid_buffer_busaddr = dma_map_single(fei->dev,
 514                                                 tsin->pid_buffer_aligned,
 515                                                 PID_TABLE_SIZE,
 516                                                 DMA_BIDIRECTIONAL);
 517
 518         if (dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) {
 519                 dev_err(fei->dev, "failed to map pid_bitmap\n");
 520                 ret = -EFAULT;
 521                 goto err_unmap;
 522         }
 523
 524         /* manage cache so pid bitmap is visible to HW */
 525         dma_sync_single_for_device(fei->dev,
 526                                 tsin->pid_buffer_busaddr,
 527                                 PID_TABLE_SIZE,
 528                                 DMA_TO_DEVICE);
 529
 530         snprintf(tsin_pin_name, MAX_NAME, "tsin%d-%s", tsin->tsin_id,
 531                 (tsin->serial_not_parallel ? "serial" : "parallel"));
 532
 533         tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name);
 534         if (IS_ERR(tsin->pstate)) {
 535                 dev_err(fei->dev, "%s: pinctrl_lookup_state couldn't find %s state\n"
 536                         , __func__, tsin_pin_name);
 537                 ret = PTR_ERR(tsin->pstate);
 538                 goto err_unmap;
 539         }
 540
 541         ret = pinctrl_select_state(fei->pinctrl, tsin->pstate);
 542
 543         if (ret) {
 544                 dev_err(fei->dev, "%s: pinctrl_select_state failed\n"
 545                         , __func__);
 546                 goto err_unmap;
 547         }
 548
 549         /* Enable this input block */
 550         tmp = readl(fei->io + SYS_INPUT_CLKEN);
 551         tmp |= BIT(tsin->tsin_id);
 552         writel(tmp, fei->io + SYS_INPUT_CLKEN);
 553
 554         if (tsin->serial_not_parallel)
 555                 tmp |= C8SECTPFE_SERIAL_NOT_PARALLEL;
 556
 557         if (tsin->invert_ts_clk)
 558                 tmp |= C8SECTPFE_INVERT_TSCLK;
 559
 560         if (tsin->async_not_sync)
 561                 tmp |= C8SECTPFE_ASYNC_NOT_SYNC;
 562
 563         tmp |= C8SECTPFE_ALIGN_BYTE_SOP | C8SECTPFE_BYTE_ENDIANNESS_MSB;
 564
 565         writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id));
 566
 567         writel(C8SECTPFE_SYNC(0x9) |
 568                 C8SECTPFE_DROP(0x9) |
 569                 C8SECTPFE_TOKEN(0x47),
 570                 fei->io + C8SECTPFE_IB_SYNCLCKDRP_CFG(tsin->tsin_id));
 571
 572         writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id));
 573
 574         /* Place the FIFO's at the end of the irec descriptors */
 575
 576         tsin->fifo = (tsin->tsin_id * FIFO_LEN);
 577
 578         writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id));
 579         writel(tsin->fifo + FIFO_LEN - 1,
 580                 fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id));
 581
 582         writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id));
 583         writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id));
 584
 585         writel(tsin->pid_buffer_busaddr,
 586                 fei->io + PIDF_BASE(tsin->tsin_id));
 587
 588         dev_dbg(fei->dev, "chan=%d PIDF_BASE=0x%x pid_bus_addr=%pad\n",
 589                 tsin->tsin_id, readl(fei->io + PIDF_BASE(tsin->tsin_id)),
 590                 &tsin->pid_buffer_busaddr);
 591
 592         /* Configure and enable HW PID filtering */
 593
 594         /*
 595          * The PID value is created by assembling the first 8 bytes of
 596          * the TS packet into a 64-bit word in big-endian format. A
 597          * slice of that 64-bit word is taken from
 598          * (PID_OFFSET+PID_NUM_BITS-1) to PID_OFFSET.
 599          */
 600         tmp = (C8SECTPFE_PID_ENABLE | C8SECTPFE_PID_NUMBITS(13)
 601                 | C8SECTPFE_PID_OFFSET(40));
 602
 603         writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id));
 604
 605         dev_dbg(fei->dev, "chan=%d setting wp: %d, rp: %d, buf: %d-%d\n",
 606                 tsin->tsin_id,
 607                 readl(fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)),
 608                 readl(fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)),
 609                 readl(fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)),
 610                 readl(fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id)));
 611
 612         /* Get base addpress of pointer record block from DMEM */
 613         tsin->irec = fei->io + DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET +
 614                         readl(fei->io + DMA_PTRREC_BASE);
 615
 616         /* fill out pointer record data structure */
 617
 618         /* advance pointer record block to our channel */
 619         tsin->irec += (tsin->tsin_id * DMA_PRDS_SIZE);
 620
 621         writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE);
 622
 623         writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP);
 624
 625         writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE);
 626
 627         writel(0x1, tsin->irec + DMA_PRDS_TPENABLE);
 628
 629         /* read/write pointers with physical bus address */
 630
 631         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0));
 632
 633         tmp = tsin->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 634         writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0));
 635
 636         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0));
 637         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0));
 638
 639         /* initialize tasklet */
 640         tasklet_setup(&tsin->tsklet, channel_swdemux_tsklet);
 641
 642         return 0;
 643
 644 err_unmap:
 645         free_input_block(fei, tsin);
 646         return ret;
 647 }
 648
 649 static irqreturn_t c8sectpfe_error_irq_handler(int irq, void *priv)
 650 {
 651         struct c8sectpfei *fei = priv;
 652
 653         dev_err(fei->dev, "%s: error handling not yet implemented\n"
 654                 , __func__);
 655
 656         /*
 657          * TODO FIXME we should detect some error conditions here
 658          * and ideally so something about them!
 659          */
 660
 661         return IRQ_HANDLED;
 662 }
 663
 664 static int c8sectpfe_probe(struct platform_device *pdev)
 665 {
 666         struct device *dev = &pdev->dev;
 667         struct device_node *child, *np = dev->of_node;
 668         struct c8sectpfei *fei;
 669         struct resource *res;
 670         int ret, index = 0;
 671         struct channel_info *tsin;
 672
 673         /* Allocate the c8sectpfei structure */
 674         fei = devm_kzalloc(dev, sizeof(struct c8sectpfei), GFP_KERNEL);
 675         if (!fei)
 676                 return -ENOMEM;
 677
 678         fei->dev = dev;
 679
 680         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "c8sectpfe");
 681         fei->io = devm_ioremap_resource(dev, res);
 682         if (IS_ERR(fei->io))
 683                 return PTR_ERR(fei->io);
 684
 685         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 686                                         "c8sectpfe-ram");
 687         fei->sram = devm_ioremap_resource(dev, res);
 688         if (IS_ERR(fei->sram))
 689                 return PTR_ERR(fei->sram);
 690
 691         fei->sram_size = resource_size(res);
 692
 693         fei->idle_irq = platform_get_irq_byname(pdev, "c8sectpfe-idle-irq");
 694         if (fei->idle_irq < 0)
 695                 return fei->idle_irq;
 696
 697         fei->error_irq = platform_get_irq_byname(pdev, "c8sectpfe-error-irq");
 698         if (fei->error_irq < 0)
 699                 return fei->error_irq;
 700
 701         platform_set_drvdata(pdev, fei);
 702
 703         fei->c8sectpfeclk = devm_clk_get(dev, "c8sectpfe");
 704         if (IS_ERR(fei->c8sectpfeclk)) {
 705                 dev_err(dev, "c8sectpfe clk not found\n");
 706                 return PTR_ERR(fei->c8sectpfeclk);
 707         }
 708
 709         ret = clk_prepare_enable(fei->c8sectpfeclk);
 710         if (ret) {
 711                 dev_err(dev, "Failed to enable c8sectpfe clock\n");
 712                 return ret;
 713         }
 714
 715         /* to save power disable all IP's (on by default) */
 716         writel(0, fei->io + SYS_INPUT_CLKEN);
 717
 718         /* Enable memdma clock */
 719         writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN);
 720
 721         /* clear internal sram */
 722         memset_io(fei->sram, 0x0, fei->sram_size);
 723
 724         c8sectpfe_getconfig(fei);
 725
 726         ret = devm_request_irq(dev, fei->idle_irq, c8sectpfe_idle_irq_handler,
 727                         0, "c8sectpfe-idle-irq", fei);
 728         if (ret) {
 729                 dev_err(dev, "Can't register c8sectpfe-idle-irq IRQ.\n");
 730                 goto err_clk_disable;
 731         }
 732
 733         ret = devm_request_irq(dev, fei->error_irq,
 734                                 c8sectpfe_error_irq_handler, 0,
 735                                 "c8sectpfe-error-irq", fei);
 736         if (ret) {
 737                 dev_err(dev, "Can't register c8sectpfe-error-irq IRQ.\n");
 738                 goto err_clk_disable;
 739         }
 740
 741         fei->tsin_count = of_get_child_count(np);
 742
 743         if (fei->tsin_count > C8SECTPFE_MAX_TSIN_CHAN ||
 744                 fei->tsin_count > fei->hw_stats.num_ib) {
 745
 746                 dev_err(dev, "More tsin declared than exist on SoC!\n");
 747                 ret = -EINVAL;
 748                 goto err_clk_disable;
 749         }
 750
 751         fei->pinctrl = devm_pinctrl_get(dev);
 752
 753         if (IS_ERR(fei->pinctrl)) {
 754                 dev_err(dev, "Error getting tsin pins\n");
 755                 ret = PTR_ERR(fei->pinctrl);
 756                 goto err_clk_disable;
 757         }
 758
 759         for_each_child_of_node(np, child) {
 760                 struct device_node *i2c_bus;
 761
 762                 fei->channel_data[index] = devm_kzalloc(dev,
 763                                                 sizeof(struct channel_info),
 764                                                 GFP_KERNEL);
 765
 766                 if (!fei->channel_data[index]) {
 767                         ret = -ENOMEM;
 768                         goto err_clk_disable;
 769                 }
 770
 771                 tsin = fei->channel_data[index];
 772
 773                 tsin->fei = fei;
 774
 775                 ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id);
 776                 if (ret) {
 777                         dev_err(&pdev->dev, "No tsin_num found\n");
 778                         goto err_clk_disable;
 779                 }
 780
 781                 /* sanity check value */
 782                 if (tsin->tsin_id > fei->hw_stats.num_ib) {
 783                         dev_err(&pdev->dev,
 784                                 "tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)",
 785                                 tsin->tsin_id, fei->hw_stats.num_ib);
 786                         ret = -EINVAL;
 787                         goto err_clk_disable;
 788                 }
 789
 790                 tsin->invert_ts_clk = of_property_read_bool(child,
 791                                                         "invert-ts-clk");
 792
 793                 tsin->serial_not_parallel = of_property_read_bool(child,
 794                                                         "serial-not-parallel");
 795
 796                 tsin->async_not_sync = of_property_read_bool(child,
 797                                                         "async-not-sync");
 798
 799                 ret = of_property_read_u32(child, "dvb-card",
 800                                         &tsin->dvb_card);
 801                 if (ret) {
 802                         dev_err(&pdev->dev, "No dvb-card found\n");
 803                         goto err_clk_disable;
 804                 }
 805
 806                 i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
 807                 if (!i2c_bus) {
 808                         dev_err(&pdev->dev, "No i2c-bus found\n");
 809                         ret = -ENODEV;
 810                         goto err_clk_disable;
 811                 }
 812                 tsin->i2c_adapter =
 813                         of_find_i2c_adapter_by_node(i2c_bus);
 814                 if (!tsin->i2c_adapter) {
 815                         dev_err(&pdev->dev, "No i2c adapter found\n");
 816                         of_node_put(i2c_bus);
 817                         ret = -ENODEV;
 818                         goto err_clk_disable;
 819                 }
 820                 of_node_put(i2c_bus);
 821
 822                 tsin->rst_gpio = of_get_named_gpio(child, "reset-gpios", 0);
 823
 824                 ret = gpio_is_valid(tsin->rst_gpio);
 825                 if (!ret) {
 826                         dev_err(dev,
 827                                 "reset gpio for tsin%d not valid (gpio=%d)\n",
 828                                 tsin->tsin_id, tsin->rst_gpio);
 829                         goto err_clk_disable;
 830                 }
 831
 832                 ret = devm_gpio_request_one(dev, tsin->rst_gpio,
 833                                         GPIOF_OUT_INIT_LOW, "NIM reset");
 834                 if (ret && ret != -EBUSY) {
 835                         dev_err(dev, "Can't request tsin%d reset gpio\n"
 836                                 , fei->channel_data[index]->tsin_id);
 837                         goto err_clk_disable;
 838                 }
 839
 840                 if (!ret) {
 841                         /* toggle reset lines */
 842                         gpio_direction_output(tsin->rst_gpio, 0);
 843                         usleep_range(3500, 5000);
 844                         gpio_direction_output(tsin->rst_gpio, 1);
 845                         usleep_range(3000, 5000);
 846                 }
 847
 848                 tsin->demux_mapping = index;
 849
 850                 dev_dbg(fei->dev,
 851                         "channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
 852                         fei->channel_data[index], index,
 853                         tsin->tsin_id, tsin->invert_ts_clk,
 854                         tsin->serial_not_parallel, tsin->async_not_sync,
 855                         tsin->dvb_card);
 856
 857                 index++;
 858         }
 859
 860         /* Setup timer interrupt */
 861         timer_setup(&fei->timer, c8sectpfe_timer_interrupt, 0);
 862
 863         mutex_init(&fei->lock);
 864
 865         /* Get the configuration information about the tuners */
 866         ret = c8sectpfe_tuner_register_frontend(&fei->c8sectpfe[0],
 867                                         (void *)fei,
 868                                         c8sectpfe_start_feed,
 869                                         c8sectpfe_stop_feed);
 870         if (ret) {
 871                 dev_err(dev, "c8sectpfe_tuner_register_frontend failed (%d)\n",
 872                         ret);
 873                 goto err_clk_disable;
 874         }
 875
 876         c8sectpfe_debugfs_init(fei);
 877
 878         return 0;
 879
 880 err_clk_disable:
 881         clk_disable_unprepare(fei->c8sectpfeclk);
 882         return ret;
 883 }
 884
 885 static int c8sectpfe_remove(struct platform_device *pdev)
 886 {
 887         struct c8sectpfei *fei = platform_get_drvdata(pdev);
 888         struct channel_info *channel;
 889         int i;
 890
 891         wait_for_completion(&fei->fw_ack);
 892
 893         c8sectpfe_tuner_unregister_frontend(fei->c8sectpfe[0], fei);
 894
 895         /*
 896          * Now loop through and un-configure each of the InputBlock resources
 897          */
 898         for (i = 0; i < fei->tsin_count; i++) {
 899                 channel = fei->channel_data[i];
 900                 free_input_block(fei, channel);
 901         }
 902
 903         c8sectpfe_debugfs_exit(fei);
 904
 905         dev_info(fei->dev, "Stopping memdma SLIM core\n");
 906         if (readl(fei->io + DMA_CPU_RUN))
 907                 writel(0x0,  fei->io + DMA_CPU_RUN);
 908
 909         /* unclock all internal IP's */
 910         if (readl(fei->io + SYS_INPUT_CLKEN))
 911                 writel(0, fei->io + SYS_INPUT_CLKEN);
 912
 913         if (readl(fei->io + SYS_OTHER_CLKEN))
 914                 writel(0, fei->io + SYS_OTHER_CLKEN);
 915
 916         if (fei->c8sectpfeclk)
 917                 clk_disable_unprepare(fei->c8sectpfeclk);
 918
 919         return 0;
 920 }
 921
 922
 923 static int configure_channels(struct c8sectpfei *fei)
 924 {
 925         int index = 0, ret;
 926         struct channel_info *tsin;
 927         struct device_node *child, *np = fei->dev->of_node;
 928
 929         /* iterate round each tsin and configure memdma descriptor and IB hw */
 930         for_each_child_of_node(np, child) {
 931
 932                 tsin = fei->channel_data[index];
 933
 934                 ret = configure_memdma_and_inputblock(fei,
 935                                                 fei->channel_data[index]);
 936
 937                 if (ret) {
 938                         dev_err(fei->dev,
 939                                 "configure_memdma_and_inputblock failed\n");
 940                         of_node_put(child);
 941                         goto err_unmap;
 942                 }
 943                 index++;
 944         }
 945
 946         return 0;
 947
 948 err_unmap:
 949         for (index = 0; index < fei->tsin_count; index++) {
 950                 tsin = fei->channel_data[index];
 951                 free_input_block(fei, tsin);
 952         }
 953         return ret;
 954 }
 955
 956 static int
 957 c8sectpfe_elf_sanity_check(struct c8sectpfei *fei, const struct firmware *fw)
 958 {
 959         struct elf32_hdr *ehdr;
 960         char class;
 961
 962         if (!fw) {
 963                 dev_err(fei->dev, "failed to load %s\n", FIRMWARE_MEMDMA);
 964                 return -EINVAL;
 965         }
 966
 967         if (fw->size < sizeof(struct elf32_hdr)) {
 968                 dev_err(fei->dev, "Image is too small\n");
 969                 return -EINVAL;
 970         }
 971
 972         ehdr = (struct elf32_hdr *)fw->data;
 973
 974         /* We only support ELF32 at this point */
 975         class = ehdr->e_ident[EI_CLASS];
 976         if (class != ELFCLASS32) {
 977                 dev_err(fei->dev, "Unsupported class: %d\n", class);
 978                 return -EINVAL;
 979         }
 980
 981         if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
 982                 dev_err(fei->dev, "Unsupported firmware endianness\n");
 983                 return -EINVAL;
 984         }
 985
 986         if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) {
 987                 dev_err(fei->dev, "Image is too small\n");
 988                 return -EINVAL;
 989         }
 990
 991         if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
 992                 dev_err(fei->dev, "Image is corrupted (bad magic)\n");
 993                 return -EINVAL;
 994         }
 995
 996         /* Check ELF magic */
 997         ehdr = (Elf32_Ehdr *)fw->data;
 998         if (ehdr->e_ident[EI_MAG0] != ELFMAG0 ||
 999             ehdr->e_ident[EI_MAG1] != ELFMAG1 ||
1000             ehdr->e_ident[EI_MAG2] != ELFMAG2 ||
1001             ehdr->e_ident[EI_MAG3] != ELFMAG3) {
1002                 dev_err(fei->dev, "Invalid ELF magic\n");
1003                 return -EINVAL;
1004         }
1005
1006         if (ehdr->e_type != ET_EXEC) {
1007                 dev_err(fei->dev, "Unsupported ELF header type\n");
1008                 return -EINVAL;
1009         }
1010
1011         if (ehdr->e_phoff > fw->size) {
1012                 dev_err(fei->dev, "Firmware size is too small\n");
1013                 return -EINVAL;
1014         }
1015
1016         return 0;
1017 }
1018
1019
1020 static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1021                         const struct firmware *fw, u8 __iomem *dest,
1022                         int seg_num)
1023 {
1024         const u8 *imem_src = fw->data + phdr->p_offset;
1025         int i;
1026
1027         /*
1028          * For IMEM segments, the segment contains 24-bit
1029          * instructions which must be padded to 32-bit
1030          * instructions before being written. The written
1031          * segment is padded with NOP instructions.
1032          */
1033
1034         dev_dbg(fei->dev,
1035                 "Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n",
1036 seg_num,
1037                 phdr->p_paddr, phdr->p_filesz,
1038                 dest, phdr->p_memsz + phdr->p_memsz / 3);
1039
1040         for (i = 0; i < phdr->p_filesz; i++) {
1041
1042                 writeb(readb((void __iomem *)imem_src), (void __iomem *)dest);
1043
1044                 /* Every 3 bytes, add an additional
1045                  * padding zero in destination */
1046                 if (i % 3 == 2) {
1047                         dest++;
1048                         writeb(0x00, (void __iomem *)dest);
1049                 }
1050
1051                 dest++;
1052                 imem_src++;
1053         }
1054 }
1055
1056 static void load_dmem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1057                         const struct firmware *fw, u8 __iomem *dst, int seg_num)
1058 {
1059         /*
1060          * For DMEM segments copy the segment data from the ELF
1061          * file and pad segment with zeroes
1062          */
1063
1064         dev_dbg(fei->dev,
1065                 "Loading DMEM segment %d 0x%08x\n\t(0x%x bytes) -> 0x%p (0x%x bytes)\n",
1066                 seg_num, phdr->p_paddr, phdr->p_filesz,
1067                 dst, phdr->p_memsz);
1068
1069         memcpy((void __force *)dst, (void *)fw->data + phdr->p_offset,
1070                 phdr->p_filesz);
1071
1072         memset((void __force *)dst + phdr->p_filesz, 0,
1073                 phdr->p_memsz - phdr->p_filesz);
1074 }
1075
1076 static int load_slim_core_fw(const struct firmware *fw, struct c8sectpfei *fei)
1077 {
1078         Elf32_Ehdr *ehdr;
1079         Elf32_Phdr *phdr;
1080         u8 __iomem *dst;
1081         int err = 0, i;
1082
1083         if (!fw || !fei)
1084                 return -EINVAL;
1085
1086         ehdr = (Elf32_Ehdr *)fw->data;
1087         phdr = (Elf32_Phdr *)(fw->data + ehdr->e_phoff);
1088
1089         /* go through the available ELF segments */
1090         for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
1091
1092                 /* Only consider LOAD segments */
1093                 if (phdr->p_type != PT_LOAD)
1094                         continue;
1095
1096                 /*
1097                  * Check segment is contained within the fw->data buffer
1098                  */
1099                 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1100                         dev_err(fei->dev,
1101                                 "Segment %d is outside of firmware file\n", i);
1102                         err = -EINVAL;
1103                         break;
1104                 }
1105
1106                 /*
1107                  * MEMDMA IMEM has executable flag set, otherwise load
1108                  * this segment into DMEM.
1109                  *
1110                  */
1111
1112                 if (phdr->p_flags & PF_X) {
1113                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_IMEM;
1114                         /*
1115                          * The Slim ELF file uses 32-bit word addressing for
1116                          * load offsets.
1117                          */
1118                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1119                         load_imem_segment(fei, phdr, fw, dst, i);
1120                 } else {
1121                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_DMEM;
1122                         /*
1123                          * The Slim ELF file uses 32-bit word addressing for
1124                          * load offsets.
1125                          */
1126                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1127                         load_dmem_segment(fei, phdr, fw, dst, i);
1128                 }
1129         }
1130
1131         release_firmware(fw);
1132         return err;
1133 }
1134
1135 static int load_c8sectpfe_fw(struct c8sectpfei *fei)
1136 {
1137         const struct firmware *fw;
1138         int err;
1139
1140         dev_info(fei->dev, "Loading firmware: %s\n", FIRMWARE_MEMDMA);
1141
1142         err = reject_firmware(&fw, FIRMWARE_MEMDMA, fei->dev);
1143         if (err)
1144                 return err;
1145
1146         err = c8sectpfe_elf_sanity_check(fei, fw);
1147         if (err) {
1148                 dev_err(fei->dev, "c8sectpfe_elf_sanity_check failed err=(%d)\n"
1149                         , err);
1150                 release_firmware(fw);
1151                 return err;
1152         }
1153
1154         err = load_slim_core_fw(fw, fei);
1155         if (err) {
1156                 dev_err(fei->dev, "load_slim_core_fw failed err=(%d)\n", err);
1157                 return err;
1158         }
1159
1160         /* now the firmware is loaded configure the input blocks */
1161         err = configure_channels(fei);
1162         if (err) {
1163                 dev_err(fei->dev, "configure_channels failed err=(%d)\n", err);
1164                 return err;
1165         }
1166
1167         /*
1168          * STBus target port can access IMEM and DMEM ports
1169          * without waiting for CPU
1170          */
1171         writel(0x1, fei->io + DMA_PER_STBUS_SYNC);
1172
1173         dev_info(fei->dev, "Boot the memdma SLIM core\n");
1174         writel(0x1,  fei->io + DMA_CPU_RUN);
1175
1176         atomic_set(&fei->fw_loaded, 1);
1177
1178         return 0;
1179 }
1180
1181 static const struct of_device_id c8sectpfe_match[] = {
1182         { .compatible = "st,stih407-c8sectpfe" },
1183         { /* sentinel */ },
1184 };
1185 MODULE_DEVICE_TABLE(of, c8sectpfe_match);
1186
1187 static struct platform_driver c8sectpfe_driver = {
1188         .driver = {
1189                 .name = "c8sectpfe",
1190                 .of_match_table = of_match_ptr(c8sectpfe_match),
1191         },
1192         .probe  = c8sectpfe_probe,
1193         .remove = c8sectpfe_remove,
1194 };
1195
1196 module_platform_driver(c8sectpfe_driver);
1197
1198 MODULE_AUTHOR("Peter Bennett <peter.bennett@st.com>");
1199 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
1200 MODULE_DESCRIPTION("C8SECTPFE STi DVB Driver");
1201 MODULE_LICENSE("GPL");