drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
   4  *
   5  * Samsung MFC (Multi Function Codec - FIMV) driver
   6  * This file contains hw related functions.
   7  *
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com/
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/delay.h>
  15 #include <linux/mm.h>
  16 #include <linux/io.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/firmware.h>
  19 #include <linux/err.h>
  20 #include <linux/sched.h>
  21 #include <linux/dma-mapping.h>
  22
  23 #include <asm/cacheflush.h>
  24
  25 #include "s5p_mfc_common.h"
  26 #include "s5p_mfc_cmd.h"
  27 #include "s5p_mfc_intr.h"
  28 #include "s5p_mfc_pm.h"
  29 #include "s5p_mfc_debug.h"
  30 #include "s5p_mfc_opr.h"
  31 #include "s5p_mfc_opr_v6.h"
  32
  33 /* #define S5P_MFC_DEBUG_REGWRITE  */
  34 #ifdef S5P_MFC_DEBUG_REGWRITE
  35 #undef writel
  36 #define writel(v, r)                                                    \
  37         do {                                                            \
  38                 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v);     \
  39         __raw_writel(v, r);                                             \
  40         } while (0)
  41 #endif /* S5P_MFC_DEBUG_REGWRITE */
  42
  43 #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
  44
  45 /* Allocate temporary buffers for decoding */
  46 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
  47 {
  48         /* NOP */
  49
  50         return 0;
  51 }
  52
  53 /* Release temporary buffers for decoding */
  54 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
  55 {
  56         /* NOP */
  57 }
  58
  59 /* Allocate codec buffers */
  60 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
  61 {
  62         struct s5p_mfc_dev *dev = ctx->dev;
  63         unsigned int mb_width, mb_height;
  64         unsigned int lcu_width = 0, lcu_height = 0;
  65         int ret;
  66
  67         mb_width = MB_WIDTH(ctx->img_width);
  68         mb_height = MB_HEIGHT(ctx->img_height);
  69
  70         if (ctx->type == MFCINST_DECODER) {
  71                 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
  72                           ctx->luma_size, ctx->chroma_size, ctx->mv_size);
  73                 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
  74         } else if (ctx->type == MFCINST_ENCODER) {
  75                 if (IS_MFCV10(dev)) {
  76                         ctx->tmv_buffer_size = 0;
  77                 } else if (IS_MFCV8_PLUS(dev))
  78                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  79                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
  80                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  81                 else
  82                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  83                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
  84                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  85                 if (IS_MFCV10(dev)) {
  86                         lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
  87                         lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
  88                         if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
  89                                 ctx->luma_dpb_size =
  90                                         ALIGN((mb_width * 16), 64)
  91                                         * ALIGN((mb_height * 16), 32)
  92                                                 + 64;
  93                                 ctx->chroma_dpb_size =
  94                                         ALIGN((mb_width * 16), 64)
  95                                                         * (mb_height * 8)
  96                                                         + 64;
  97                         } else {
  98                                 ctx->luma_dpb_size =
  99                                         ALIGN((lcu_width * 32), 64)
 100                                         * ALIGN((lcu_height * 32), 32)
 101                                                 + 64;
 102                                 ctx->chroma_dpb_size =
 103                                         ALIGN((lcu_width * 32), 64)
 104                                                         * (lcu_height * 16)
 105                                                         + 64;
 106                         }
 107                 } else {
 108                         ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
 109                                         S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
 110                                         S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
 111                         ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
 112                                         S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
 113                                         S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
 114                 }
 115                 if (IS_MFCV8_PLUS(dev))
 116                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
 117                                                 ctx->img_width, ctx->img_height,
 118                                                 mb_width, mb_height),
 119                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 120                 else
 121                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
 122                                                 ctx->img_width, ctx->img_height,
 123                                                 mb_width, mb_height),
 124                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 125
 126                 mfc_debug(2, "recon luma size: %zu chroma size: %zu\n",
 127                           ctx->luma_dpb_size, ctx->chroma_dpb_size);
 128         } else {
 129                 return -EINVAL;
 130         }
 131
 132         /* Codecs have different memory requirements */
 133         switch (ctx->codec_mode) {
 134         case S5P_MFC_CODEC_H264_DEC:
 135         case S5P_MFC_CODEC_H264_MVC_DEC:
 136                 if (IS_MFCV10(dev))
 137                         mfc_debug(2, "Use min scratch buffer size\n");
 138                 else if (IS_MFCV8_PLUS(dev))
 139                         ctx->scratch_buf_size =
 140                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 141                                         mb_width,
 142                                         mb_height);
 143                 else
 144                         ctx->scratch_buf_size =
 145                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
 146                                         mb_width,
 147                                         mb_height);
 148                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 149                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 150                 ctx->bank1.size =
 151                         ctx->scratch_buf_size +
 152                         (ctx->mv_count * ctx->mv_size);
 153                 break;
 154         case S5P_MFC_CODEC_MPEG4_DEC:
 155                 if (IS_MFCV10(dev))
 156                         mfc_debug(2, "Use min scratch buffer size\n");
 157                 else if (IS_MFCV7_PLUS(dev)) {
 158                         ctx->scratch_buf_size =
 159                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
 160                                                 mb_width,
 161                                                 mb_height);
 162                 } else {
 163                         ctx->scratch_buf_size =
 164                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
 165                                                 mb_width,
 166                                                 mb_height);
 167                 }
 168
 169                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 170                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 171                 ctx->bank1.size = ctx->scratch_buf_size;
 172                 break;
 173         case S5P_MFC_CODEC_VC1RCV_DEC:
 174         case S5P_MFC_CODEC_VC1_DEC:
 175                 if (IS_MFCV10(dev))
 176                         mfc_debug(2, "Use min scratch buffer size\n");
 177                 else
 178                         ctx->scratch_buf_size =
 179                                 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
 180                                                 mb_width,
 181                                                 mb_height);
 182
 183                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 184                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 185                 ctx->bank1.size = ctx->scratch_buf_size;
 186                 break;
 187         case S5P_MFC_CODEC_MPEG2_DEC:
 188                 ctx->bank1.size = 0;
 189                 ctx->bank2.size = 0;
 190                 break;
 191         case S5P_MFC_CODEC_H263_DEC:
 192                 if (IS_MFCV10(dev))
 193                         mfc_debug(2, "Use min scratch buffer size\n");
 194                 else
 195                         ctx->scratch_buf_size =
 196                                 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
 197                                                 mb_width,
 198                                                 mb_height);
 199                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 200                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 201                 ctx->bank1.size = ctx->scratch_buf_size;
 202                 break;
 203         case S5P_MFC_CODEC_VP8_DEC:
 204                 if (IS_MFCV10(dev))
 205                         mfc_debug(2, "Use min scratch buffer size\n");
 206                 else if (IS_MFCV8_PLUS(dev))
 207                         ctx->scratch_buf_size =
 208                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 209                                                 mb_width,
 210                                                 mb_height);
 211                 else
 212                         ctx->scratch_buf_size =
 213                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
 214                                                 mb_width,
 215                                                 mb_height);
 216                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 217                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 218                 ctx->bank1.size = ctx->scratch_buf_size;
 219                 break;
 220         case S5P_MFC_CODEC_HEVC_DEC:
 221                 mfc_debug(2, "Use min scratch buffer size\n");
 222                 ctx->bank1.size =
 223                         ctx->scratch_buf_size +
 224                         (ctx->mv_count * ctx->mv_size);
 225                 break;
 226         case S5P_MFC_CODEC_VP9_DEC:
 227                 mfc_debug(2, "Use min scratch buffer size\n");
 228                 ctx->bank1.size =
 229                         ctx->scratch_buf_size +
 230                         DEC_VP9_STATIC_BUFFER_SIZE;
 231                 break;
 232         case S5P_MFC_CODEC_H264_ENC:
 233                 if (IS_MFCV10(dev)) {
 234                         mfc_debug(2, "Use min scratch buffer size\n");
 235                         ctx->me_buffer_size =
 236                         ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
 237                 } else if (IS_MFCV8_PLUS(dev))
 238                         ctx->scratch_buf_size =
 239                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 240                                         mb_width,
 241                                         mb_height);
 242                 else
 243                         ctx->scratch_buf_size =
 244                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
 245                                                 mb_width,
 246                                                 mb_height);
 247                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 248                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 249                 ctx->bank1.size =
 250                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 251                         (ctx->pb_count * (ctx->luma_dpb_size +
 252                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 253                 ctx->bank2.size = 0;
 254                 break;
 255         case S5P_MFC_CODEC_MPEG4_ENC:
 256         case S5P_MFC_CODEC_H263_ENC:
 257                 if (IS_MFCV10(dev)) {
 258                         mfc_debug(2, "Use min scratch buffer size\n");
 259                         ctx->me_buffer_size =
 260                                 ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
 261                                                         mb_height), 16);
 262                 } else
 263                         ctx->scratch_buf_size =
 264                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
 265                                                 mb_width,
 266                                                 mb_height);
 267                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 268                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 269                 ctx->bank1.size =
 270                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 271                         (ctx->pb_count * (ctx->luma_dpb_size +
 272                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 273                 ctx->bank2.size = 0;
 274                 break;
 275         case S5P_MFC_CODEC_VP8_ENC:
 276                 if (IS_MFCV10(dev)) {
 277                         mfc_debug(2, "Use min scratch buffer size\n");
 278                         ctx->me_buffer_size =
 279                                 ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
 280                                                 16);
 281                 } else if (IS_MFCV8_PLUS(dev))
 282                         ctx->scratch_buf_size =
 283                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 284                                         mb_width,
 285                                         mb_height);
 286                 else
 287                         ctx->scratch_buf_size =
 288                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
 289                                                 mb_width,
 290                                                 mb_height);
 291                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 292                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 293                 ctx->bank1.size =
 294                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 295                         (ctx->pb_count * (ctx->luma_dpb_size +
 296                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 297                 ctx->bank2.size = 0;
 298                 break;
 299         case S5P_MFC_CODEC_HEVC_ENC:
 300                 mfc_debug(2, "Use min scratch buffer size\n");
 301                 ctx->me_buffer_size =
 302                         ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
 303                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
 304                 ctx->bank1.size =
 305                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 306                         (ctx->pb_count * (ctx->luma_dpb_size +
 307                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 308                 ctx->bank2.size = 0;
 309                 break;
 310         default:
 311                 break;
 312         }
 313
 314         /* Allocate only if memory from bank 1 is necessary */
 315         if (ctx->bank1.size > 0) {
 316                 ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1);
 317                 if (ret) {
 318                         mfc_err("Failed to allocate Bank1 memory\n");
 319                         return ret;
 320                 }
 321                 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
 322         }
 323         return 0;
 324 }
 325
 326 /* Release buffers allocated for codec */
 327 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 328 {
 329         s5p_mfc_release_generic_buf(ctx->dev, &ctx->bank1);
 330 }
 331
 332 /* Allocate memory for instance data buffer */
 333 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 334 {
 335         struct s5p_mfc_dev *dev = ctx->dev;
 336         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 337         int ret;
 338
 339         mfc_debug_enter();
 340
 341         switch (ctx->codec_mode) {
 342         case S5P_MFC_CODEC_H264_DEC:
 343         case S5P_MFC_CODEC_H264_MVC_DEC:
 344         case S5P_MFC_CODEC_HEVC_DEC:
 345                 ctx->ctx.size = buf_size->h264_dec_ctx;
 346                 break;
 347         case S5P_MFC_CODEC_MPEG4_DEC:
 348         case S5P_MFC_CODEC_H263_DEC:
 349         case S5P_MFC_CODEC_VC1RCV_DEC:
 350         case S5P_MFC_CODEC_VC1_DEC:
 351         case S5P_MFC_CODEC_MPEG2_DEC:
 352         case S5P_MFC_CODEC_VP8_DEC:
 353         case S5P_MFC_CODEC_VP9_DEC:
 354                 ctx->ctx.size = buf_size->other_dec_ctx;
 355                 break;
 356         case S5P_MFC_CODEC_H264_ENC:
 357                 ctx->ctx.size = buf_size->h264_enc_ctx;
 358                 break;
 359         case S5P_MFC_CODEC_HEVC_ENC:
 360                 ctx->ctx.size = buf_size->hevc_enc_ctx;
 361                 break;
 362         case S5P_MFC_CODEC_MPEG4_ENC:
 363         case S5P_MFC_CODEC_H263_ENC:
 364         case S5P_MFC_CODEC_VP8_ENC:
 365                 ctx->ctx.size = buf_size->other_enc_ctx;
 366                 break;
 367         default:
 368                 ctx->ctx.size = 0;
 369                 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
 370                 break;
 371         }
 372
 373         ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->ctx);
 374         if (ret) {
 375                 mfc_err("Failed to allocate instance buffer\n");
 376                 return ret;
 377         }
 378
 379         memset(ctx->ctx.virt, 0, ctx->ctx.size);
 380         wmb();
 381
 382         mfc_debug_leave();
 383
 384         return 0;
 385 }
 386
 387 /* Release instance buffer */
 388 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 389 {
 390         s5p_mfc_release_priv_buf(ctx->dev, &ctx->ctx);
 391 }
 392
 393 /* Allocate context buffers for SYS_INIT */
 394 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 395 {
 396         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 397         int ret;
 398
 399         mfc_debug_enter();
 400
 401         dev->ctx_buf.size = buf_size->dev_ctx;
 402         ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->ctx_buf);
 403         if (ret) {
 404                 mfc_err("Failed to allocate device context buffer\n");
 405                 return ret;
 406         }
 407
 408         memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
 409         wmb();
 410
 411         mfc_debug_leave();
 412
 413         return 0;
 414 }
 415
 416 /* Release context buffers for SYS_INIT */
 417 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 418 {
 419         s5p_mfc_release_priv_buf(dev, &dev->ctx_buf);
 420 }
 421
 422 static int calc_plane(int width, int height)
 423 {
 424         int mbX, mbY;
 425
 426         mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 427         mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
 428
 429         if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
 430                 mbY = (mbY + 1) / 2 * 2;
 431
 432         return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
 433                 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 434 }
 435
 436 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 437 {
 438         struct s5p_mfc_dev *dev = ctx->dev;
 439         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 440         ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
 441         mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
 442                         "buffer dimensions: %dx%d\n", ctx->img_width,
 443                         ctx->img_height, ctx->buf_width, ctx->buf_height);
 444
 445         ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
 446         ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
 447         if (IS_MFCV8_PLUS(ctx->dev)) {
 448                 /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
 449                 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 450                 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 451         }
 452
 453         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 454                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 455                 if (IS_MFCV10(dev)) {
 456                         ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
 457                                         ctx->img_height);
 458                 } else {
 459                         ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
 460                                         ctx->img_height);
 461                 }
 462         } else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
 463                 ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width,
 464                                 ctx->img_height);
 465                 ctx->mv_size = ALIGN(ctx->mv_size, 32);
 466         } else {
 467                 ctx->mv_size = 0;
 468         }
 469 }
 470
 471 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
 472 {
 473         unsigned int mb_width, mb_height;
 474
 475         mb_width = MB_WIDTH(ctx->img_width);
 476         mb_height = MB_HEIGHT(ctx->img_height);
 477
 478         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 479         ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
 480         ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
 481
 482         /* MFCv7 needs pad bytes for Luma and Chroma */
 483         if (IS_MFCV7_PLUS(ctx->dev)) {
 484                 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
 485                 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
 486         }
 487 }
 488
 489 /* Set registers for decoding stream buffer */
 490 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 491                         int buf_addr, unsigned int start_num_byte,
 492                         unsigned int strm_size)
 493 {
 494         struct s5p_mfc_dev *dev = ctx->dev;
 495         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 496         struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
 497
 498         mfc_debug_enter();
 499         mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
 500                 "buf_size: 0x%08x (%d)\n",
 501                 ctx->inst_no, buf_addr, strm_size, strm_size);
 502         writel(strm_size, mfc_regs->d_stream_data_size);
 503         writel(buf_addr, mfc_regs->d_cpb_buffer_addr);
 504         writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
 505         writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);
 506
 507         mfc_debug_leave();
 508         return 0;
 509 }
 510
 511 /* Set decoding frame buffer */
 512 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 513 {
 514         unsigned int frame_size, i;
 515         unsigned int frame_size_ch, frame_size_mv;
 516         struct s5p_mfc_dev *dev = ctx->dev;
 517         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 518         size_t buf_addr1;
 519         int buf_size1;
 520         int align_gap;
 521
 522         buf_addr1 = ctx->bank1.dma;
 523         buf_size1 = ctx->bank1.size;
 524
 525         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 526         mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
 527         mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
 528
 529         writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
 530         writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
 531         writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
 532
 533         writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
 534         writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
 535
 536         if (IS_MFCV8_PLUS(dev)) {
 537                 writel(ctx->img_width,
 538                         mfc_regs->d_first_plane_dpb_stride_size);
 539                 writel(ctx->img_width,
 540                         mfc_regs->d_second_plane_dpb_stride_size);
 541         }
 542
 543         buf_addr1 += ctx->scratch_buf_size;
 544         buf_size1 -= ctx->scratch_buf_size;
 545
 546         if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
 547                         ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC ||
 548                         ctx->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) {
 549                 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
 550                 writel(ctx->mv_count, mfc_regs->d_num_mv);
 551         }
 552
 553         frame_size = ctx->luma_size;
 554         frame_size_ch = ctx->chroma_size;
 555         frame_size_mv = ctx->mv_size;
 556         mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
 557                         frame_size, frame_size_ch, frame_size_mv);
 558
 559         for (i = 0; i < ctx->total_dpb_count; i++) {
 560                 /* Bank2 */
 561                 mfc_debug(2, "Luma %d: %zx\n", i,
 562                                         ctx->dst_bufs[i].cookie.raw.luma);
 563                 writel(ctx->dst_bufs[i].cookie.raw.luma,
 564                                 mfc_regs->d_first_plane_dpb + i * 4);
 565                 mfc_debug(2, "\tChroma %d: %zx\n", i,
 566                                         ctx->dst_bufs[i].cookie.raw.chroma);
 567                 writel(ctx->dst_bufs[i].cookie.raw.chroma,
 568                                 mfc_regs->d_second_plane_dpb + i * 4);
 569         }
 570         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 571                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||
 572                         ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
 573                 for (i = 0; i < ctx->mv_count; i++) {
 574                         /* To test alignment */
 575                         align_gap = buf_addr1;
 576                         buf_addr1 = ALIGN(buf_addr1, 16);
 577                         align_gap = buf_addr1 - align_gap;
 578                         buf_size1 -= align_gap;
 579
 580                         mfc_debug(2, "\tBuf1: %zx, size: %d\n",
 581                                         buf_addr1, buf_size1);
 582                         writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
 583                         buf_addr1 += frame_size_mv;
 584                         buf_size1 -= frame_size_mv;
 585                 }
 586         }
 587         if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {
 588                 writel(buf_addr1, mfc_regs->d_static_buffer_addr);
 589                 writel(DEC_VP9_STATIC_BUFFER_SIZE,
 590                                 mfc_regs->d_static_buffer_size);
 591                 buf_addr1 += DEC_VP9_STATIC_BUFFER_SIZE;
 592                 buf_size1 -= DEC_VP9_STATIC_BUFFER_SIZE;
 593         }
 594
 595         mfc_debug(2, "Buf1: %zx, buf_size1: %d (frames %d)\n",
 596                         buf_addr1, buf_size1, ctx->total_dpb_count);
 597         if (buf_size1 < 0) {
 598                 mfc_debug(2, "Not enough memory has been allocated.\n");
 599                 return -ENOMEM;
 600         }
 601
 602         writel(ctx->inst_no, mfc_regs->instance_id);
 603         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 604                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 605
 606         mfc_debug(2, "After setting buffers.\n");
 607         return 0;
 608 }
 609
 610 /* Set registers for encoding stream buffer */
 611 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 612                 unsigned long addr, unsigned int size)
 613 {
 614         struct s5p_mfc_dev *dev = ctx->dev;
 615         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 616
 617         writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
 618         writel(size, mfc_regs->e_stream_buffer_size);
 619
 620         mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%x\n",
 621                   addr, size);
 622
 623         return 0;
 624 }
 625
 626 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 627                 unsigned long y_addr, unsigned long c_addr)
 628 {
 629         struct s5p_mfc_dev *dev = ctx->dev;
 630         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 631
 632         writel(y_addr, mfc_regs->e_source_first_plane_addr);
 633         writel(c_addr, mfc_regs->e_source_second_plane_addr);
 634
 635         mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
 636         mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
 637 }
 638
 639 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 640                 unsigned long *y_addr, unsigned long *c_addr)
 641 {
 642         struct s5p_mfc_dev *dev = ctx->dev;
 643         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 644         unsigned long enc_recon_y_addr, enc_recon_c_addr;
 645
 646         *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);
 647         *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);
 648
 649         enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);
 650         enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);
 651
 652         mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);
 653         mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
 654 }
 655
 656 /* Set encoding ref & codec buffer */
 657 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
 658 {
 659         struct s5p_mfc_dev *dev = ctx->dev;
 660         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 661         size_t buf_addr1;
 662         int i, buf_size1;
 663
 664         mfc_debug_enter();
 665
 666         buf_addr1 = ctx->bank1.dma;
 667         buf_size1 = ctx->bank1.size;
 668
 669         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 670
 671         if (IS_MFCV10(dev)) {
 672                 /* start address of per buffer is aligned */
 673                 for (i = 0; i < ctx->pb_count; i++) {
 674                         writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 675                         buf_addr1 += ctx->luma_dpb_size;
 676                         buf_size1 -= ctx->luma_dpb_size;
 677                 }
 678                 for (i = 0; i < ctx->pb_count; i++) {
 679                         writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 680                         buf_addr1 += ctx->chroma_dpb_size;
 681                         buf_size1 -= ctx->chroma_dpb_size;
 682                 }
 683                 for (i = 0; i < ctx->pb_count; i++) {
 684                         writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 685                         buf_addr1 += ctx->me_buffer_size;
 686                         buf_size1 -= ctx->me_buffer_size;
 687                 }
 688         } else {
 689                 for (i = 0; i < ctx->pb_count; i++) {
 690                         writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 691                         buf_addr1 += ctx->luma_dpb_size;
 692                         writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 693                         buf_addr1 += ctx->chroma_dpb_size;
 694                         writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 695                         buf_addr1 += ctx->me_buffer_size;
 696                         buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
 697                                         + ctx->me_buffer_size);
 698                 }
 699         }
 700
 701         writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
 702         writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
 703         buf_addr1 += ctx->scratch_buf_size;
 704         buf_size1 -= ctx->scratch_buf_size;
 705
 706         writel(buf_addr1, mfc_regs->e_tmv_buffer0);
 707         buf_addr1 += ctx->tmv_buffer_size >> 1;
 708         writel(buf_addr1, mfc_regs->e_tmv_buffer1);
 709         buf_addr1 += ctx->tmv_buffer_size >> 1;
 710         buf_size1 -= ctx->tmv_buffer_size;
 711
 712         mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n",
 713                         buf_addr1, buf_size1, ctx->pb_count);
 714         if (buf_size1 < 0) {
 715                 mfc_debug(2, "Not enough memory has been allocated.\n");
 716                 return -ENOMEM;
 717         }
 718
 719         writel(ctx->inst_no, mfc_regs->instance_id);
 720         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 721                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 722
 723         mfc_debug_leave();
 724
 725         return 0;
 726 }
 727
 728 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
 729 {
 730         struct s5p_mfc_dev *dev = ctx->dev;
 731         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 732
 733         /* multi-slice control */
 734         /* multi-slice MB number or bit size */
 735         writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
 736         if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
 737                 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
 738         } else if (ctx->slice_mode ==
 739                         V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
 740                 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
 741         } else {
 742                 writel(0x0, mfc_regs->e_mslice_size_mb);
 743                 writel(0x0, mfc_regs->e_mslice_size_bits);
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
 750 {
 751         struct s5p_mfc_dev *dev = ctx->dev;
 752         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 753         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 754         unsigned int reg = 0;
 755
 756         mfc_debug_enter();
 757
 758         /* width */
 759         writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
 760         /* height */
 761         writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
 762
 763         /* cropped width */
 764         writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
 765         /* cropped height */
 766         writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
 767         /* cropped offset */
 768         writel(0x0, mfc_regs->e_frame_crop_offset);
 769
 770         /* pictype : IDR period */
 771         reg = 0;
 772         reg |= p->gop_size & 0xFFFF;
 773         writel(reg, mfc_regs->e_gop_config);
 774
 775         /* multi-slice control */
 776         /* multi-slice MB number or bit size */
 777         ctx->slice_mode = p->slice_mode;
 778         reg = 0;
 779         if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
 780                 reg |= (0x1 << 3);
 781                 writel(reg, mfc_regs->e_enc_options);
 782                 ctx->slice_size.mb = p->slice_mb;
 783         } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
 784                 reg |= (0x1 << 3);
 785                 writel(reg, mfc_regs->e_enc_options);
 786                 ctx->slice_size.bits = p->slice_bit;
 787         } else {
 788                 reg &= ~(0x1 << 3);
 789                 writel(reg, mfc_regs->e_enc_options);
 790         }
 791
 792         s5p_mfc_set_slice_mode(ctx);
 793
 794         /* cyclic intra refresh */
 795         writel(p->intra_refresh_mb, mfc_regs->e_ir_size);
 796         reg = readl(mfc_regs->e_enc_options);
 797         if (p->intra_refresh_mb == 0)
 798                 reg &= ~(0x1 << 4);
 799         else
 800                 reg |= (0x1 << 4);
 801         writel(reg, mfc_regs->e_enc_options);
 802
 803         /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
 804         reg = readl(mfc_regs->e_enc_options);
 805         reg &= ~(0x1 << 9);
 806         writel(reg, mfc_regs->e_enc_options);
 807
 808         /* memory structure cur. frame */
 809         if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
 810                 /* 0: Linear, 1: 2D tiled*/
 811                 reg = readl(mfc_regs->e_enc_options);
 812                 reg &= ~(0x1 << 7);
 813                 writel(reg, mfc_regs->e_enc_options);
 814                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 815                 writel(0x0, mfc_regs->pixel_format);
 816         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
 817                 /* 0: Linear, 1: 2D tiled*/
 818                 reg = readl(mfc_regs->e_enc_options);
 819                 reg &= ~(0x1 << 7);
 820                 writel(reg, mfc_regs->e_enc_options);
 821                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 822                 writel(0x1, mfc_regs->pixel_format);
 823         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
 824                 /* 0: Linear, 1: 2D tiled*/
 825                 reg = readl(mfc_regs->e_enc_options);
 826                 reg |= (0x1 << 7);
 827                 writel(reg, mfc_regs->e_enc_options);
 828                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 829                 writel(0x0, mfc_regs->pixel_format);
 830         }
 831
 832         /* memory structure recon. frame */
 833         /* 0: Linear, 1: 2D tiled */
 834         reg = readl(mfc_regs->e_enc_options);
 835         reg |= (0x1 << 8);
 836         writel(reg, mfc_regs->e_enc_options);
 837
 838         /* padding control & value */
 839         writel(0x0, mfc_regs->e_padding_ctrl);
 840         if (p->pad) {
 841                 reg = 0;
 842                 /** enable */
 843                 reg |= (1UL << 31);
 844                 /** cr value */
 845                 reg |= ((p->pad_cr & 0xFF) << 16);
 846                 /** cb value */
 847                 reg |= ((p->pad_cb & 0xFF) << 8);
 848                 /** y value */
 849                 reg |= p->pad_luma & 0xFF;
 850                 writel(reg, mfc_regs->e_padding_ctrl);
 851         }
 852
 853         /* rate control config. */
 854         reg = 0;
 855         /* frame-level rate control */
 856         reg |= ((p->rc_frame & 0x1) << 9);
 857         writel(reg, mfc_regs->e_rc_config);
 858
 859         /* bit rate */
 860         if (p->rc_frame)
 861                 writel(p->rc_bitrate,
 862                         mfc_regs->e_rc_bit_rate);
 863         else
 864                 writel(1, mfc_regs->e_rc_bit_rate);
 865
 866         /* reaction coefficient */
 867         if (p->rc_frame) {
 868                 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
 869                         writel(1, mfc_regs->e_rc_mode);
 870                 else                                      /* loose CBR */
 871                         writel(2, mfc_regs->e_rc_mode);
 872         }
 873
 874         /* seq header ctrl */
 875         reg = readl(mfc_regs->e_enc_options);
 876         reg &= ~(0x1 << 2);
 877         reg |= ((p->seq_hdr_mode & 0x1) << 2);
 878
 879         /* frame skip mode */
 880         reg &= ~(0x3);
 881         reg |= (p->frame_skip_mode & 0x3);
 882         writel(reg, mfc_regs->e_enc_options);
 883
 884         /* 'DROP_CONTROL_ENABLE', disable */
 885         reg = readl(mfc_regs->e_rc_config);
 886         reg &= ~(0x1 << 10);
 887         writel(reg, mfc_regs->e_rc_config);
 888
 889         /* setting for MV range [16, 256] */
 890         reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 891         writel(reg, mfc_regs->e_mv_hor_range);
 892
 893         reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 894         writel(reg, mfc_regs->e_mv_ver_range);
 895
 896         writel(0x0, mfc_regs->e_frame_insertion);
 897         writel(0x0, mfc_regs->e_roi_buffer_addr);
 898         writel(0x0, mfc_regs->e_param_change);
 899         writel(0x0, mfc_regs->e_rc_roi_ctrl);
 900         writel(0x0, mfc_regs->e_picture_tag);
 901
 902         writel(0x0, mfc_regs->e_bit_count_enable);
 903         writel(0x0, mfc_regs->e_max_bit_count);
 904         writel(0x0, mfc_regs->e_min_bit_count);
 905
 906         writel(0x0, mfc_regs->e_metadata_buffer_addr);
 907         writel(0x0, mfc_regs->e_metadata_buffer_size);
 908
 909         mfc_debug_leave();
 910
 911         return 0;
 912 }
 913
 914 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
 915 {
 916         struct s5p_mfc_dev *dev = ctx->dev;
 917         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 918         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 919         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
 920         unsigned int reg = 0;
 921         int i;
 922
 923         mfc_debug_enter();
 924
 925         s5p_mfc_set_enc_params(ctx);
 926
 927         /* pictype : number of B */
 928         reg = readl(mfc_regs->e_gop_config);
 929         reg &= ~(0x3 << 16);
 930         reg |= ((p->num_b_frame & 0x3) << 16);
 931         writel(reg, mfc_regs->e_gop_config);
 932
 933         /* profile & level */
 934         reg = 0;
 935         /** level */
 936         reg |= ((p_h264->level & 0xFF) << 8);
 937         /** profile - 0 ~ 3 */
 938         reg |= p_h264->profile & 0x3F;
 939         writel(reg, mfc_regs->e_picture_profile);
 940
 941         /* rate control config. */
 942         reg = readl(mfc_regs->e_rc_config);
 943         /** macroblock level rate control */
 944         reg &= ~(0x1 << 8);
 945         reg |= ((p->rc_mb & 0x1) << 8);
 946         writel(reg, mfc_regs->e_rc_config);
 947
 948         /** frame QP */
 949         reg &= ~(0x3F);
 950         reg |= p_h264->rc_frame_qp & 0x3F;
 951         writel(reg, mfc_regs->e_rc_config);
 952
 953         /* max & min value of QP */
 954         reg = 0;
 955         /** max QP */
 956         reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
 957         /** min QP */
 958         reg |= p_h264->rc_min_qp & 0x3F;
 959         writel(reg, mfc_regs->e_rc_qp_bound);
 960
 961         /* other QPs */
 962         writel(0x0, mfc_regs->e_fixed_picture_qp);
 963         if (!p->rc_frame && !p->rc_mb) {
 964                 reg = 0;
 965                 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
 966                 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
 967                 reg |= p_h264->rc_frame_qp & 0x3F;
 968                 writel(reg, mfc_regs->e_fixed_picture_qp);
 969         }
 970
 971         /* frame rate */
 972         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
 973                 reg = 0;
 974                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
 975                 reg |= p->rc_framerate_denom & 0xFFFF;
 976                 writel(reg, mfc_regs->e_rc_frame_rate);
 977         }
 978
 979         /* vbv buffer size */
 980         if (p->frame_skip_mode ==
 981                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
 982                 writel(p_h264->cpb_size & 0xFFFF,
 983                                 mfc_regs->e_vbv_buffer_size);
 984
 985                 if (p->rc_frame)
 986                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
 987         }
 988
 989         /* interlace */
 990         reg = 0;
 991         reg |= ((p_h264->interlace & 0x1) << 3);
 992         writel(reg, mfc_regs->e_h264_options);
 993
 994         /* height */
 995         if (p_h264->interlace) {
 996                 writel(ctx->img_height >> 1,
 997                                 mfc_regs->e_frame_height); /* 32 align */
 998                 /* cropped height */
 999                 writel(ctx->img_height >> 1,
1000                                 mfc_regs->e_cropped_frame_height);
1001         }
1002
1003         /* loop filter ctrl */
1004         reg = readl(mfc_regs->e_h264_options);
1005         reg &= ~(0x3 << 1);
1006         reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
1007         writel(reg, mfc_regs->e_h264_options);
1008
1009         /* loopfilter alpha offset */
1010         if (p_h264->loop_filter_alpha < 0) {
1011                 reg = 0x10;
1012                 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
1013         } else {
1014                 reg = 0x00;
1015                 reg |= (p_h264->loop_filter_alpha & 0xF);
1016         }
1017         writel(reg, mfc_regs->e_h264_lf_alpha_offset);
1018
1019         /* loopfilter beta offset */
1020         if (p_h264->loop_filter_beta < 0) {
1021                 reg = 0x10;
1022                 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
1023         } else {
1024                 reg = 0x00;
1025                 reg |= (p_h264->loop_filter_beta & 0xF);
1026         }
1027         writel(reg, mfc_regs->e_h264_lf_beta_offset);
1028
1029         /* entropy coding mode */
1030         reg = readl(mfc_regs->e_h264_options);
1031         reg &= ~(0x1);
1032         reg |= p_h264->entropy_mode & 0x1;
1033         writel(reg, mfc_regs->e_h264_options);
1034
1035         /* number of ref. picture */
1036         reg = readl(mfc_regs->e_h264_options);
1037         reg &= ~(0x1 << 7);
1038         reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
1039         writel(reg, mfc_regs->e_h264_options);
1040
1041         /* 8x8 transform enable */
1042         reg = readl(mfc_regs->e_h264_options);
1043         reg &= ~(0x3 << 12);
1044         reg |= ((p_h264->_8x8_transform & 0x3) << 12);
1045         writel(reg, mfc_regs->e_h264_options);
1046
1047         /* macroblock adaptive scaling features */
1048         writel(0x0, mfc_regs->e_mb_rc_config);
1049         if (p->rc_mb) {
1050                 reg = 0;
1051                 /** dark region */
1052                 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
1053                 /** smooth region */
1054                 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
1055                 /** static region */
1056                 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
1057                 /** high activity region */
1058                 reg |= p_h264->rc_mb_activity & 0x1;
1059                 writel(reg, mfc_regs->e_mb_rc_config);
1060         }
1061
1062         /* aspect ratio VUI */
1063         reg = readl(mfc_regs->e_h264_options);
1064         reg &= ~(0x1 << 5);
1065         reg |= ((p_h264->vui_sar & 0x1) << 5);
1066         writel(reg, mfc_regs->e_h264_options);
1067
1068         writel(0x0, mfc_regs->e_aspect_ratio);
1069         writel(0x0, mfc_regs->e_extended_sar);
1070         if (p_h264->vui_sar) {
1071                 /* aspect ration IDC */
1072                 reg = 0;
1073                 reg |= p_h264->vui_sar_idc & 0xFF;
1074                 writel(reg, mfc_regs->e_aspect_ratio);
1075                 if (p_h264->vui_sar_idc == 0xFF) {
1076                         /* extended SAR */
1077                         reg = 0;
1078                         reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
1079                         reg |= p_h264->vui_ext_sar_height & 0xFFFF;
1080                         writel(reg, mfc_regs->e_extended_sar);
1081                 }
1082         }
1083
1084         /* intra picture period for H.264 open GOP */
1085         /* control */
1086         reg = readl(mfc_regs->e_h264_options);
1087         reg &= ~(0x1 << 4);
1088         reg |= ((p_h264->open_gop & 0x1) << 4);
1089         writel(reg, mfc_regs->e_h264_options);
1090
1091         /* value */
1092         writel(0x0, mfc_regs->e_h264_i_period);
1093         if (p_h264->open_gop) {
1094                 reg = 0;
1095                 reg |= p_h264->open_gop_size & 0xFFFF;
1096                 writel(reg, mfc_regs->e_h264_i_period);
1097         }
1098
1099         /* 'WEIGHTED_BI_PREDICTION' for B is disable */
1100         reg = readl(mfc_regs->e_h264_options);
1101         reg &= ~(0x3 << 9);
1102         writel(reg, mfc_regs->e_h264_options);
1103
1104         /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
1105         reg = readl(mfc_regs->e_h264_options);
1106         reg &= ~(0x1 << 14);
1107         writel(reg, mfc_regs->e_h264_options);
1108
1109         /* ASO */
1110         reg = readl(mfc_regs->e_h264_options);
1111         reg &= ~(0x1 << 6);
1112         reg |= ((p_h264->aso & 0x1) << 6);
1113         writel(reg, mfc_regs->e_h264_options);
1114
1115         /* hier qp enable */
1116         reg = readl(mfc_regs->e_h264_options);
1117         reg &= ~(0x1 << 8);
1118         reg |= ((p_h264->open_gop & 0x1) << 8);
1119         writel(reg, mfc_regs->e_h264_options);
1120         reg = 0;
1121         if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1122                 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1123                 reg |= p_h264->hier_qp_layer & 0x7;
1124                 writel(reg, mfc_regs->e_h264_num_t_layer);
1125                 /* QP value for each layer */
1126                 for (i = 0; i < p_h264->hier_qp_layer &&
1127                                 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1128                         writel(p_h264->hier_qp_layer_qp[i],
1129                                 mfc_regs->e_h264_hierarchical_qp_layer0
1130                                 + i * 4);
1131                 }
1132         }
1133         /* number of coding layer should be zero when hierarchical is disable */
1134         writel(reg, mfc_regs->e_h264_num_t_layer);
1135
1136         /* frame packing SEI generation */
1137         reg = readl(mfc_regs->e_h264_options);
1138         reg &= ~(0x1 << 25);
1139         reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1140         writel(reg, mfc_regs->e_h264_options);
1141         if (p_h264->sei_frame_packing) {
1142                 reg = 0;
1143                 /** current frame0 flag */
1144                 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1145                 /** arrangement type */
1146                 reg |= p_h264->sei_fp_arrangement_type & 0x3;
1147                 writel(reg, mfc_regs->e_h264_frame_packing_sei_info);
1148         }
1149
1150         if (p_h264->fmo) {
1151                 switch (p_h264->fmo_map_type) {
1152                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
1153                         if (p_h264->fmo_slice_grp > 4)
1154                                 p_h264->fmo_slice_grp = 4;
1155                         for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1156                                 writel(p_h264->fmo_run_len[i] - 1,
1157                                         mfc_regs->e_h264_fmo_run_length_minus1_0
1158                                         + i * 4);
1159                         break;
1160                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1161                         if (p_h264->fmo_slice_grp > 4)
1162                                 p_h264->fmo_slice_grp = 4;
1163                         break;
1164                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1165                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1166                         if (p_h264->fmo_slice_grp > 2)
1167                                 p_h264->fmo_slice_grp = 2;
1168                         writel(p_h264->fmo_chg_dir & 0x1,
1169                                 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1170                         /* the valid range is 0 ~ number of macroblocks -1 */
1171                         writel(p_h264->fmo_chg_rate,
1172                         mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1173                         break;
1174                 default:
1175                         mfc_err("Unsupported map type for FMO: %d\n",
1176                                         p_h264->fmo_map_type);
1177                         p_h264->fmo_map_type = 0;
1178                         p_h264->fmo_slice_grp = 1;
1179                         break;
1180                 }
1181
1182                 writel(p_h264->fmo_map_type,
1183                                 mfc_regs->e_h264_fmo_slice_grp_map_type);
1184                 writel(p_h264->fmo_slice_grp - 1,
1185                                 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1186         } else {
1187                 writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1188         }
1189
1190         mfc_debug_leave();
1191
1192         return 0;
1193 }
1194
1195 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1196 {
1197         struct s5p_mfc_dev *dev = ctx->dev;
1198         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1199         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1200         struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1201         unsigned int reg = 0;
1202
1203         mfc_debug_enter();
1204
1205         s5p_mfc_set_enc_params(ctx);
1206
1207         /* pictype : number of B */
1208         reg = readl(mfc_regs->e_gop_config);
1209         reg &= ~(0x3 << 16);
1210         reg |= ((p->num_b_frame & 0x3) << 16);
1211         writel(reg, mfc_regs->e_gop_config);
1212
1213         /* profile & level */
1214         reg = 0;
1215         /** level */
1216         reg |= ((p_mpeg4->level & 0xFF) << 8);
1217         /** profile - 0 ~ 1 */
1218         reg |= p_mpeg4->profile & 0x3F;
1219         writel(reg, mfc_regs->e_picture_profile);
1220
1221         /* rate control config. */
1222         reg = readl(mfc_regs->e_rc_config);
1223         /** macroblock level rate control */
1224         reg &= ~(0x1 << 8);
1225         reg |= ((p->rc_mb & 0x1) << 8);
1226         writel(reg, mfc_regs->e_rc_config);
1227
1228         /** frame QP */
1229         reg &= ~(0x3F);
1230         reg |= p_mpeg4->rc_frame_qp & 0x3F;
1231         writel(reg, mfc_regs->e_rc_config);
1232
1233         /* max & min value of QP */
1234         reg = 0;
1235         /** max QP */
1236         reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1237         /** min QP */
1238         reg |= p_mpeg4->rc_min_qp & 0x3F;
1239         writel(reg, mfc_regs->e_rc_qp_bound);
1240
1241         /* other QPs */
1242         writel(0x0, mfc_regs->e_fixed_picture_qp);
1243         if (!p->rc_frame && !p->rc_mb) {
1244                 reg = 0;
1245                 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1246                 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1247                 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1248                 writel(reg, mfc_regs->e_fixed_picture_qp);
1249         }
1250
1251         /* frame rate */
1252         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1253                 reg = 0;
1254                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1255                 reg |= p->rc_framerate_denom & 0xFFFF;
1256                 writel(reg, mfc_regs->e_rc_frame_rate);
1257         }
1258
1259         /* vbv buffer size */
1260         if (p->frame_skip_mode ==
1261                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1262                 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1263
1264                 if (p->rc_frame)
1265                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1266         }
1267
1268         /* Disable HEC */
1269         writel(0x0, mfc_regs->e_mpeg4_options);
1270         writel(0x0, mfc_regs->e_mpeg4_hec_period);
1271
1272         mfc_debug_leave();
1273
1274         return 0;
1275 }
1276
1277 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1278 {
1279         struct s5p_mfc_dev *dev = ctx->dev;
1280         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1281         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1282         struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1283         unsigned int reg = 0;
1284
1285         mfc_debug_enter();
1286
1287         s5p_mfc_set_enc_params(ctx);
1288
1289         /* profile & level */
1290         reg = 0;
1291         /** profile */
1292         reg |= (0x1 << 4);
1293         writel(reg, mfc_regs->e_picture_profile);
1294
1295         /* rate control config. */
1296         reg = readl(mfc_regs->e_rc_config);
1297         /** macroblock level rate control */
1298         reg &= ~(0x1 << 8);
1299         reg |= ((p->rc_mb & 0x1) << 8);
1300         writel(reg, mfc_regs->e_rc_config);
1301
1302         /** frame QP */
1303         reg &= ~(0x3F);
1304         reg |= p_h263->rc_frame_qp & 0x3F;
1305         writel(reg, mfc_regs->e_rc_config);
1306
1307         /* max & min value of QP */
1308         reg = 0;
1309         /** max QP */
1310         reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1311         /** min QP */
1312         reg |= p_h263->rc_min_qp & 0x3F;
1313         writel(reg, mfc_regs->e_rc_qp_bound);
1314
1315         /* other QPs */
1316         writel(0x0, mfc_regs->e_fixed_picture_qp);
1317         if (!p->rc_frame && !p->rc_mb) {
1318                 reg = 0;
1319                 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1320                 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1321                 reg |= p_h263->rc_frame_qp & 0x3F;
1322                 writel(reg, mfc_regs->e_fixed_picture_qp);
1323         }
1324
1325         /* frame rate */
1326         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1327                 reg = 0;
1328                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1329                 reg |= p->rc_framerate_denom & 0xFFFF;
1330                 writel(reg, mfc_regs->e_rc_frame_rate);
1331         }
1332
1333         /* vbv buffer size */
1334         if (p->frame_skip_mode ==
1335                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1336                 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1337
1338                 if (p->rc_frame)
1339                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1340         }
1341
1342         mfc_debug_leave();
1343
1344         return 0;
1345 }
1346
1347 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1348 {
1349         struct s5p_mfc_dev *dev = ctx->dev;
1350         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1351         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1352         struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1353         unsigned int reg = 0;
1354         unsigned int val = 0;
1355
1356         mfc_debug_enter();
1357
1358         s5p_mfc_set_enc_params(ctx);
1359
1360         /* pictype : number of B */
1361         reg = readl(mfc_regs->e_gop_config);
1362         reg &= ~(0x3 << 16);
1363         reg |= ((p->num_b_frame & 0x3) << 16);
1364         writel(reg, mfc_regs->e_gop_config);
1365
1366         /* profile - 0 ~ 3 */
1367         reg = p_vp8->profile & 0x3;
1368         writel(reg, mfc_regs->e_picture_profile);
1369
1370         /* rate control config. */
1371         reg = readl(mfc_regs->e_rc_config);
1372         /** macroblock level rate control */
1373         reg &= ~(0x1 << 8);
1374         reg |= ((p->rc_mb & 0x1) << 8);
1375         writel(reg, mfc_regs->e_rc_config);
1376
1377         /* frame rate */
1378         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1379                 reg = 0;
1380                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1381                 reg |= p->rc_framerate_denom & 0xFFFF;
1382                 writel(reg, mfc_regs->e_rc_frame_rate);
1383         }
1384
1385         /* frame QP */
1386         reg &= ~(0x7F);
1387         reg |= p_vp8->rc_frame_qp & 0x7F;
1388         writel(reg, mfc_regs->e_rc_config);
1389
1390         /* other QPs */
1391         writel(0x0, mfc_regs->e_fixed_picture_qp);
1392         if (!p->rc_frame && !p->rc_mb) {
1393                 reg = 0;
1394                 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1395                 reg |= p_vp8->rc_frame_qp & 0x7F;
1396                 writel(reg, mfc_regs->e_fixed_picture_qp);
1397         }
1398
1399         /* max QP */
1400         reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1401         /* min QP */
1402         reg |= p_vp8->rc_min_qp & 0x7F;
1403         writel(reg, mfc_regs->e_rc_qp_bound);
1404
1405         /* vbv buffer size */
1406         if (p->frame_skip_mode ==
1407                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1408                 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1409
1410                 if (p->rc_frame)
1411                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1412         }
1413
1414         /* VP8 specific params */
1415         reg = 0;
1416         reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1417         switch (p_vp8->num_partitions) {
1418         case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1419                 val = 0;
1420                 break;
1421         case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1422                 val = 2;
1423                 break;
1424         case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1425                 val = 4;
1426                 break;
1427         case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1428                 val = 8;
1429                 break;
1430         }
1431         reg |= (val & 0xF) << 3;
1432         reg |= (p_vp8->num_ref & 0x2);
1433         writel(reg, mfc_regs->e_vp8_options);
1434
1435         mfc_debug_leave();
1436
1437         return 0;
1438 }
1439
1440 static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
1441 {
1442         struct s5p_mfc_dev *dev = ctx->dev;
1443         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1444         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1445         struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
1446         unsigned int reg = 0;
1447         int i;
1448
1449         mfc_debug_enter();
1450
1451         s5p_mfc_set_enc_params(ctx);
1452
1453         /* pictype : number of B */
1454         reg = readl(mfc_regs->e_gop_config);
1455         /* num_b_frame - 0 ~ 2 */
1456         reg &= ~(0x3 << 16);
1457         reg |= (p->num_b_frame << 16);
1458         writel(reg, mfc_regs->e_gop_config);
1459
1460         /* UHD encoding case */
1461         if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
1462                 p_hevc->level = 51;
1463                 p_hevc->tier = 0;
1464         /* this tier can be changed */
1465         }
1466
1467         /* tier & level */
1468         reg = 0;
1469         /* profile */
1470         reg |= p_hevc->profile & 0x3;
1471         /* level */
1472         reg &= ~(0xFF << 8);
1473         reg |= (p_hevc->level << 8);
1474         /* tier - 0 ~ 1 */
1475         reg |= (p_hevc->tier << 16);
1476         writel(reg, mfc_regs->e_picture_profile);
1477
1478         switch (p_hevc->loopfilter) {
1479         case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED:
1480                 p_hevc->loopfilter_disable = 1;
1481                 break;
1482         case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED:
1483                 p_hevc->loopfilter_disable = 0;
1484                 p_hevc->loopfilter_across = 1;
1485                 break;
1486         case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY:
1487                 p_hevc->loopfilter_disable = 0;
1488                 p_hevc->loopfilter_across = 0;
1489                 break;
1490         }
1491
1492         /* max partition depth */
1493         reg = 0;
1494         reg |= (p_hevc->max_partition_depth & 0x1);
1495         reg |= (p_hevc->num_refs_for_p-1) << 2;
1496         reg |= (p_hevc->refreshtype & 0x3) << 3;
1497         reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
1498         reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
1499         reg |= (p_hevc->wavefront_enable & 0x1) << 7;
1500         reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
1501         reg |= (p_hevc->loopfilter_across & 0x1) << 9;
1502         reg |= (p_hevc->enable_ltr & 0x1) << 10;
1503         reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
1504         reg |= (p_hevc->general_pb_enable & 0x1) << 13;
1505         reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
1506         reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
1507         reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
1508         reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
1509         reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
1510         reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 23;
1511         reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
1512
1513         writel(reg, mfc_regs->e_hevc_options);
1514         /* refresh period */
1515         if (p_hevc->refreshtype) {
1516                 reg = 0;
1517                 reg |= (p_hevc->refreshperiod & 0xFFFF);
1518                 writel(reg, mfc_regs->e_hevc_refresh_period);
1519         }
1520         /* loop filter setting */
1521         if (!(p_hevc->loopfilter_disable & 0x1)) {
1522                 reg = 0;
1523                 reg |= (p_hevc->lf_beta_offset_div2);
1524                 writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
1525                 reg = 0;
1526                 reg |= (p_hevc->lf_tc_offset_div2);
1527                 writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
1528         }
1529         /* hier qp enable */
1530         if (p_hevc->num_hier_layer) {
1531                 reg = 0;
1532                 reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
1533                 reg |= p_hevc->num_hier_layer & 0x7;
1534                 writel(reg, mfc_regs->e_num_t_layer);
1535                 /* QP value for each layer */
1536                 if (p_hevc->hier_qp_enable) {
1537                         for (i = 0; i < 7; i++)
1538                                 writel(p_hevc->hier_qp_layer[i],
1539                                         mfc_regs->e_hier_qp_layer0 + i * 4);
1540                 }
1541                 if (p->rc_frame) {
1542                         for (i = 0; i < 7; i++)
1543                                 writel(p_hevc->hier_bit_layer[i],
1544                                                 mfc_regs->e_hier_bit_rate_layer0
1545                                                 + i * 4);
1546                 }
1547         }
1548
1549         /* rate control config. */
1550         reg = readl(mfc_regs->e_rc_config);
1551         /* macroblock level rate control */
1552         reg &= ~(0x1 << 8);
1553         reg |= (p->rc_mb << 8);
1554         writel(reg, mfc_regs->e_rc_config);
1555         /* frame QP */
1556         reg &= ~(0xFF);
1557         reg |= p_hevc->rc_frame_qp;
1558         writel(reg, mfc_regs->e_rc_config);
1559
1560         /* frame rate */
1561         if (p->rc_frame) {
1562                 reg = 0;
1563                 reg &= ~(0xFFFF << 16);
1564                 reg |= ((p_hevc->rc_framerate) << 16);
1565                 reg &= ~(0xFFFF);
1566                 reg |= FRAME_DELTA_DEFAULT;
1567                 writel(reg, mfc_regs->e_rc_frame_rate);
1568         }
1569
1570         /* max & min value of QP */
1571         reg = 0;
1572         /* max QP */
1573         reg &= ~(0xFF << 8);
1574         reg |= (p_hevc->rc_max_qp << 8);
1575         /* min QP */
1576         reg &= ~(0xFF);
1577         reg |= p_hevc->rc_min_qp;
1578         writel(reg, mfc_regs->e_rc_qp_bound);
1579
1580         writel(0x0, mfc_regs->e_fixed_picture_qp);
1581         if (!p->rc_frame && !p->rc_mb) {
1582                 reg = 0;
1583                 reg &= ~(0xFF << 16);
1584                 reg |= (p_hevc->rc_b_frame_qp << 16);
1585                 reg &= ~(0xFF << 8);
1586                 reg |= (p_hevc->rc_p_frame_qp << 8);
1587                 reg &= ~(0xFF);
1588                 reg |= p_hevc->rc_frame_qp;
1589                 writel(reg, mfc_regs->e_fixed_picture_qp);
1590         }
1591         mfc_debug_leave();
1592
1593         return 0;
1594 }
1595
1596 /* Initialize decoding */
1597 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1598 {
1599         struct s5p_mfc_dev *dev = ctx->dev;
1600         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1601         unsigned int reg = 0;
1602         int fmo_aso_ctrl = 0;
1603
1604         mfc_debug_enter();
1605         mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1606                         S5P_FIMV_CH_SEQ_HEADER_V6);
1607         mfc_debug(2, "BUFs: %08x %08x %08x\n",
1608                   readl(mfc_regs->d_cpb_buffer_addr),
1609                   readl(mfc_regs->d_cpb_buffer_addr),
1610                   readl(mfc_regs->d_cpb_buffer_addr));
1611
1612         /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1613         reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1614
1615         if (ctx->display_delay_enable) {
1616                 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1617                 writel(ctx->display_delay, mfc_regs->d_display_delay);
1618         }
1619
1620         if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
1621                 writel(reg, mfc_regs->d_dec_options);
1622                 reg = 0;
1623         }
1624
1625         /* Setup loop filter, for decoding this is only valid for MPEG4 */
1626         if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1627                 mfc_debug(2, "Set loop filter to: %d\n",
1628                                 ctx->loop_filter_mpeg4);
1629                 reg |= (ctx->loop_filter_mpeg4 <<
1630                                 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1631         }
1632         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1633                 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1634
1635         if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
1636                 writel(reg, mfc_regs->d_init_buffer_options);
1637         else
1638                 writel(reg, mfc_regs->d_dec_options);
1639
1640         /* 0: NV12(CbCr), 1: NV21(CrCb) */
1641         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1642                 writel(0x1, mfc_regs->pixel_format);
1643         else
1644                 writel(0x0, mfc_regs->pixel_format);
1645
1646
1647         /* sei parse */
1648         writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1649
1650         writel(ctx->inst_no, mfc_regs->instance_id);
1651         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1652                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1653
1654         mfc_debug_leave();
1655         return 0;
1656 }
1657
1658 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1659 {
1660         struct s5p_mfc_dev *dev = ctx->dev;
1661         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1662
1663         if (flush) {
1664                 dev->curr_ctx = ctx->num;
1665                 writel(ctx->inst_no, mfc_regs->instance_id);
1666                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1667                                 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1668         }
1669 }
1670
1671 /* Decode a single frame */
1672 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1673                         enum s5p_mfc_decode_arg last_frame)
1674 {
1675         struct s5p_mfc_dev *dev = ctx->dev;
1676         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1677
1678         writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1679         writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1680
1681         writel(ctx->inst_no, mfc_regs->instance_id);
1682         /* Issue different commands to instance basing on whether it
1683          * is the last frame or not. */
1684         switch (last_frame) {
1685         case 0:
1686                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1687                                 S5P_FIMV_CH_FRAME_START_V6, NULL);
1688                 break;
1689         case 1:
1690                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1691                                 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1692                 break;
1693         default:
1694                 mfc_err("Unsupported last frame arg.\n");
1695                 return -EINVAL;
1696         }
1697
1698         mfc_debug(2, "Decoding a usual frame.\n");
1699         return 0;
1700 }
1701
1702 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1703 {
1704         struct s5p_mfc_dev *dev = ctx->dev;
1705         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1706
1707         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1708                 s5p_mfc_set_enc_params_h264(ctx);
1709         else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1710                 s5p_mfc_set_enc_params_mpeg4(ctx);
1711         else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1712                 s5p_mfc_set_enc_params_h263(ctx);
1713         else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1714                 s5p_mfc_set_enc_params_vp8(ctx);
1715         else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
1716                 s5p_mfc_set_enc_params_hevc(ctx);
1717         else {
1718                 mfc_err("Unknown codec for encoding (%x).\n",
1719                         ctx->codec_mode);
1720                 return -EINVAL;
1721         }
1722
1723         /* Set stride lengths for v7 & above */
1724         if (IS_MFCV7_PLUS(dev)) {
1725                 writel(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1726                 writel(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1727         }
1728
1729         writel(ctx->inst_no, mfc_regs->instance_id);
1730         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1731                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1732
1733         return 0;
1734 }
1735
1736 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1737 {
1738         struct s5p_mfc_dev *dev = ctx->dev;
1739         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1740         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1741         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1742         int i;
1743
1744         if (p_h264->aso) {
1745                 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1746                         writel(p_h264->aso_slice_order[i],
1747                                 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1748                 }
1749         }
1750         return 0;
1751 }
1752
1753 /* Encode a single frame */
1754 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1755 {
1756         struct s5p_mfc_dev *dev = ctx->dev;
1757         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1758         int cmd;
1759
1760         mfc_debug(2, "++\n");
1761
1762         /* memory structure cur. frame */
1763
1764         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1765                 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1766
1767         s5p_mfc_set_slice_mode(ctx);
1768
1769         if (ctx->state != MFCINST_FINISHING)
1770                 cmd = S5P_FIMV_CH_FRAME_START_V6;
1771         else
1772                 cmd = S5P_FIMV_CH_LAST_FRAME_V6;
1773
1774         writel(ctx->inst_no, mfc_regs->instance_id);
1775         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, cmd, NULL);
1776
1777         mfc_debug(2, "--\n");
1778
1779         return 0;
1780 }
1781
1782 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1783 {
1784         struct s5p_mfc_dev *dev = ctx->dev;
1785
1786         s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1787         dev->curr_ctx = ctx->num;
1788         s5p_mfc_decode_one_frame_v6(ctx, MFC_DEC_LAST_FRAME);
1789 }
1790
1791 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1792 {
1793         struct s5p_mfc_dev *dev = ctx->dev;
1794         struct s5p_mfc_buf *temp_vb;
1795         int last_frame = 0;
1796
1797         if (ctx->state == MFCINST_FINISHING) {
1798                 last_frame = MFC_DEC_LAST_FRAME;
1799                 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1800                 dev->curr_ctx = ctx->num;
1801                 s5p_mfc_clean_ctx_int_flags(ctx);
1802                 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1803                 return 0;
1804         }
1805
1806         /* Frames are being decoded */
1807         if (list_empty(&ctx->src_queue)) {
1808                 mfc_debug(2, "No src buffers.\n");
1809                 return -EAGAIN;
1810         }
1811         /* Get the next source buffer */
1812         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1813         temp_vb->flags |= MFC_BUF_FLAG_USED;
1814         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1815                 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1816                         ctx->consumed_stream,
1817                         temp_vb->b->vb2_buf.planes[0].bytesused);
1818
1819         dev->curr_ctx = ctx->num;
1820         if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) {
1821                 last_frame = 1;
1822                 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1823                 ctx->state = MFCINST_FINISHING;
1824         }
1825         s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1826
1827         return 0;
1828 }
1829
1830 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1831 {
1832         struct s5p_mfc_dev *dev = ctx->dev;
1833         struct s5p_mfc_buf *dst_mb;
1834         struct s5p_mfc_buf *src_mb;
1835         unsigned long src_y_addr, src_c_addr, dst_addr;
1836         /*
1837         unsigned int src_y_size, src_c_size;
1838         */
1839         unsigned int dst_size;
1840
1841         if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
1842                 mfc_debug(2, "no src buffers.\n");
1843                 return -EAGAIN;
1844         }
1845
1846         if (list_empty(&ctx->dst_queue)) {
1847                 mfc_debug(2, "no dst buffers.\n");
1848                 return -EAGAIN;
1849         }
1850
1851         if (list_empty(&ctx->src_queue)) {
1852                 /* send null frame */
1853                 s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
1854                 src_mb = NULL;
1855         } else {
1856                 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1857                 src_mb->flags |= MFC_BUF_FLAG_USED;
1858                 if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {
1859                         s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
1860                         ctx->state = MFCINST_FINISHING;
1861                 } else {
1862                         src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);
1863                         src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);
1864
1865                         mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1866                         mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1867
1868                         s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1869                         if (src_mb->flags & MFC_BUF_FLAG_EOS)
1870                                 ctx->state = MFCINST_FINISHING;
1871                 }
1872         }
1873
1874         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1875         dst_mb->flags |= MFC_BUF_FLAG_USED;
1876         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1877         dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1878
1879         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1880
1881         dev->curr_ctx = ctx->num;
1882         s5p_mfc_encode_one_frame_v6(ctx);
1883
1884         return 0;
1885 }
1886
1887 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1888 {
1889         struct s5p_mfc_dev *dev = ctx->dev;
1890         struct s5p_mfc_buf *temp_vb;
1891
1892         /* Initializing decoding - parsing header */
1893         mfc_debug(2, "Preparing to init decoding.\n");
1894         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1895         mfc_debug(2, "Header size: %d\n", temp_vb->b->vb2_buf.planes[0].bytesused);
1896         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1897                 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), 0,
1898                         temp_vb->b->vb2_buf.planes[0].bytesused);
1899         dev->curr_ctx = ctx->num;
1900         s5p_mfc_init_decode_v6(ctx);
1901 }
1902
1903 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1904 {
1905         struct s5p_mfc_dev *dev = ctx->dev;
1906         struct s5p_mfc_buf *dst_mb;
1907         unsigned long dst_addr;
1908         unsigned int dst_size;
1909
1910         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1911         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1912         dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1913         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1914         dev->curr_ctx = ctx->num;
1915         s5p_mfc_init_encode_v6(ctx);
1916 }
1917
1918 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1919 {
1920         struct s5p_mfc_dev *dev = ctx->dev;
1921         int ret;
1922         /* Header was parsed now start processing
1923          * First set the output frame buffers
1924          * s5p_mfc_alloc_dec_buffers(ctx); */
1925
1926         if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1927                 mfc_err("It seems that not all destination buffers were\n"
1928                         "mmapped.MFC requires that all destination are mmapped\n"
1929                         "before starting processing.\n");
1930                 return -EAGAIN;
1931         }
1932
1933         dev->curr_ctx = ctx->num;
1934         ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1935         if (ret) {
1936                 mfc_err("Failed to alloc frame mem.\n");
1937                 ctx->state = MFCINST_ERROR;
1938         }
1939         return ret;
1940 }
1941
1942 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1943 {
1944         struct s5p_mfc_dev *dev = ctx->dev;
1945         int ret;
1946
1947         dev->curr_ctx = ctx->num;
1948         ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1949         if (ret) {
1950                 mfc_err("Failed to alloc frame mem.\n");
1951                 ctx->state = MFCINST_ERROR;
1952         }
1953         return ret;
1954 }
1955
1956 /* Try running an operation on hardware */
1957 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1958 {
1959         struct s5p_mfc_ctx *ctx;
1960         int new_ctx;
1961         unsigned int ret = 0;
1962
1963         mfc_debug(1, "Try run dev: %p\n", dev);
1964
1965         /* Check whether hardware is not running */
1966         if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1967                 /* This is perfectly ok, the scheduled ctx should wait */
1968                 mfc_debug(1, "Couldn't lock HW.\n");
1969                 return;
1970         }
1971
1972         /* Choose the context to run */
1973         new_ctx = s5p_mfc_get_new_ctx(dev);
1974         if (new_ctx < 0) {
1975                 /* No contexts to run */
1976                 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1977                         mfc_err("Failed to unlock hardware.\n");
1978                         return;
1979                 }
1980
1981                 mfc_debug(1, "No ctx is scheduled to be run.\n");
1982                 return;
1983         }
1984
1985         mfc_debug(1, "New context: %d\n", new_ctx);
1986         ctx = dev->ctx[new_ctx];
1987         mfc_debug(1, "Setting new context to %p\n", ctx);
1988         /* Got context to run in ctx */
1989         mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1990                 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1991         mfc_debug(1, "ctx->state=%d\n", ctx->state);
1992         /* Last frame has already been sent to MFC
1993          * Now obtaining frames from MFC buffer */
1994
1995         s5p_mfc_clock_on();
1996         s5p_mfc_clean_ctx_int_flags(ctx);
1997
1998         if (ctx->type == MFCINST_DECODER) {
1999                 switch (ctx->state) {
2000                 case MFCINST_FINISHING:
2001                         s5p_mfc_run_dec_last_frames(ctx);
2002                         break;
2003                 case MFCINST_RUNNING:
2004                         ret = s5p_mfc_run_dec_frame(ctx);
2005                         break;
2006                 case MFCINST_INIT:
2007                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
2008                                         ctx);
2009                         break;
2010                 case MFCINST_RETURN_INST:
2011                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
2012                                         ctx);
2013                         break;
2014                 case MFCINST_GOT_INST:
2015                         s5p_mfc_run_init_dec(ctx);
2016                         break;
2017                 case MFCINST_HEAD_PARSED:
2018                         ret = s5p_mfc_run_init_dec_buffers(ctx);
2019                         break;
2020                 case MFCINST_FLUSH:
2021                         s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
2022                         break;
2023                 case MFCINST_RES_CHANGE_INIT:
2024                         s5p_mfc_run_dec_last_frames(ctx);
2025                         break;
2026                 case MFCINST_RES_CHANGE_FLUSH:
2027                         s5p_mfc_run_dec_last_frames(ctx);
2028                         break;
2029                 case MFCINST_RES_CHANGE_END:
2030                         mfc_debug(2, "Finished remaining frames after resolution change.\n");
2031                         ctx->capture_state = QUEUE_FREE;
2032                         mfc_debug(2, "Will re-init the codec`.\n");
2033                         s5p_mfc_run_init_dec(ctx);
2034                         break;
2035                 default:
2036                         ret = -EAGAIN;
2037                 }
2038         } else if (ctx->type == MFCINST_ENCODER) {
2039                 switch (ctx->state) {
2040                 case MFCINST_FINISHING:
2041                 case MFCINST_RUNNING:
2042                         ret = s5p_mfc_run_enc_frame(ctx);
2043                         break;
2044                 case MFCINST_INIT:
2045                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
2046                                         ctx);
2047                         break;
2048                 case MFCINST_RETURN_INST:
2049                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
2050                                         ctx);
2051                         break;
2052                 case MFCINST_GOT_INST:
2053                         s5p_mfc_run_init_enc(ctx);
2054                         break;
2055                 case MFCINST_HEAD_PRODUCED:
2056                         ret = s5p_mfc_run_init_enc_buffers(ctx);
2057                         break;
2058                 default:
2059                         ret = -EAGAIN;
2060                 }
2061         } else {
2062                 mfc_err("invalid context type: %d\n", ctx->type);
2063                 ret = -EAGAIN;
2064         }
2065
2066         if (ret) {
2067                 /* Free hardware lock */
2068                 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
2069                         mfc_err("Failed to unlock hardware.\n");
2070
2071                 /* This is in deed imporant, as no operation has been
2072                  * scheduled, reduce the clock count as no one will
2073                  * ever do this, because no interrupt related to this try_run
2074                  * will ever come from hardware. */
2075                 s5p_mfc_clock_off();
2076         }
2077 }
2078
2079 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
2080 {
2081         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
2082         writel(0, mfc_regs->risc2host_command);
2083         writel(0, mfc_regs->risc2host_int);
2084 }
2085
2086 static unsigned int
2087 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned long ofs)
2088 {
2089         int ret;
2090
2091         s5p_mfc_clock_on();
2092         ret = readl((void __iomem *)ofs);
2093         s5p_mfc_clock_off();
2094
2095         return ret;
2096 }
2097
2098 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
2099 {
2100         return readl(dev->mfc_regs->d_display_first_plane_addr);
2101 }
2102
2103 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
2104 {
2105         return readl(dev->mfc_regs->d_decoded_first_plane_addr);
2106 }
2107
2108 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
2109 {
2110         return readl(dev->mfc_regs->d_display_status);
2111 }
2112
2113 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
2114 {
2115         return readl(dev->mfc_regs->d_decoded_status);
2116 }
2117
2118 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
2119 {
2120         return readl(dev->mfc_regs->d_decoded_frame_type) &
2121                 S5P_FIMV_DECODE_FRAME_MASK_V6;
2122 }
2123
2124 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
2125 {
2126         struct s5p_mfc_dev *dev = ctx->dev;
2127         return readl(dev->mfc_regs->d_display_frame_type) &
2128                 S5P_FIMV_DECODE_FRAME_MASK_V6;
2129 }
2130
2131 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
2132 {
2133         return readl(dev->mfc_regs->d_decoded_nal_size);
2134 }
2135
2136 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
2137 {
2138         return readl(dev->mfc_regs->risc2host_command) &
2139                 S5P_FIMV_RISC2HOST_CMD_MASK;
2140 }
2141
2142 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
2143 {
2144         return readl(dev->mfc_regs->error_code);
2145 }
2146
2147 static int s5p_mfc_err_dec_v6(unsigned int err)
2148 {
2149         return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
2150 }
2151
2152 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
2153 {
2154         return readl(dev->mfc_regs->d_display_frame_width);
2155 }
2156
2157 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
2158 {
2159         return readl(dev->mfc_regs->d_display_frame_height);
2160 }
2161
2162 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
2163 {
2164         return readl(dev->mfc_regs->d_min_num_dpb);
2165 }
2166
2167 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
2168 {
2169         return readl(dev->mfc_regs->d_min_num_mv);
2170 }
2171
2172 static int s5p_mfc_get_min_scratch_buf_size(struct s5p_mfc_dev *dev)
2173 {
2174         return readl(dev->mfc_regs->d_min_scratch_buffer_size);
2175 }
2176
2177 static int s5p_mfc_get_e_min_scratch_buf_size(struct s5p_mfc_dev *dev)
2178 {
2179         return readl(dev->mfc_regs->e_min_scratch_buffer_size);
2180 }
2181
2182 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
2183 {
2184         return readl(dev->mfc_regs->ret_instance_id);
2185 }
2186
2187 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
2188 {
2189         return readl(dev->mfc_regs->e_num_dpb);
2190 }
2191
2192 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
2193 {
2194         return readl(dev->mfc_regs->e_stream_size);
2195 }
2196
2197 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
2198 {
2199         return readl(dev->mfc_regs->e_slice_type);
2200 }
2201
2202 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2203 {
2204         return s5p_mfc_read_info_v6(ctx,
2205                 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2206 }
2207
2208 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2209 {
2210         return s5p_mfc_read_info_v6(ctx,
2211                 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2212 }
2213
2214 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2215 {
2216         return s5p_mfc_read_info_v6(ctx,
2217                 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1);
2218 }
2219
2220 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2221 {
2222         return s5p_mfc_read_info_v6(ctx,
2223                 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2);
2224 }
2225
2226 static struct s5p_mfc_regs mfc_regs;
2227
2228 /* Initialize registers for MFC v6 onwards */
2229 const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2230 {
2231         memset(&mfc_regs, 0, sizeof(mfc_regs));
2232
2233 #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2234 #define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2235         /* codec common registers */
2236         R(risc_on, S5P_FIMV_RISC_ON_V6);
2237         R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2238         R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2239         R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2240         R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2241         R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2242         R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2243         R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2244         R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2245         R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2246         R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2247         R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2248         R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2249         R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2250         R(error_code, S5P_FIMV_ERROR_CODE_V6);
2251
2252         /* decoder registers */
2253         R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2254         R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2255         R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2256         R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2257         R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2258         R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2259         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2260         R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2261         R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2262         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2263         R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2264         R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2265         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2266         R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2267         R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2268         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2269         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2270         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2271         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2272         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2273         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2274         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2275         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2276         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2277         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2278         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2279         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2280         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2281         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2282         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2283         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2284         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2285         R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2286         R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2287         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2288         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2289         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2290         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2291         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2292         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2293         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2294         R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2295         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2296         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2297
2298         /* encoder registers */
2299         R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2300         R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2301         R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2302         R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2303         R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2304         R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2305         R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2306         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2307         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2308         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2309         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2310         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2311         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2312         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2313         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2314         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2315         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2316         R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2317         R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2318         R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2319         R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2320         R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2321         R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2322         R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2323         R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2324         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2325         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2326         R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2327         R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2328         R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2329         R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2330         R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2331         R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2332         R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2333         R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2334         R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2335         R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2336         R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2337         R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2338         R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2339         R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2340         R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2341         R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2342         R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2343         R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2344         R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2345         R(e_encoded_source_first_plane_addr,
2346                         S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2347         R(e_encoded_source_second_plane_addr,
2348                         S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2349         R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2350         R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2351         R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2352         R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2353         R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2354         R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2355         R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2356         R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2357         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2358         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2359         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2360         R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2361         R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2362         R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2363         R(e_h264_fmo_slice_grp_map_type,
2364                         S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2365         R(e_h264_fmo_num_slice_grp_minus1,
2366                         S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2367         R(e_h264_fmo_slice_grp_change_dir,
2368                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2369         R(e_h264_fmo_slice_grp_change_rate_minus1,
2370                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2371         R(e_h264_fmo_run_length_minus1_0,
2372                         S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2373         R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2374         R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2375         R(e_h264_hierarchical_qp_layer0,
2376                         S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2377         R(e_h264_frame_packing_sei_info,
2378                         S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2379
2380         if (!IS_MFCV7_PLUS(dev))
2381                 goto done;
2382
2383         /* Initialize registers used in MFC v7+ */
2384         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2385         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2386         R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2387         R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2388         R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2389         R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2390         R(e_encoded_source_first_plane_addr,
2391                         S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2392         R(e_encoded_source_second_plane_addr,
2393                         S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2394         R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2395
2396         if (!IS_MFCV8_PLUS(dev))
2397                 goto done;
2398
2399         /* Initialize registers used in MFC v8 only.
2400          * Also, over-write the registers which have
2401          * a different offset for MFC v8. */
2402         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);
2403         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);
2404         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);
2405         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
2406         R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
2407         R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
2408         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
2409         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
2410         R(d_first_plane_dpb_stride_size,
2411                         S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
2412         R(d_second_plane_dpb_stride_size,
2413                         S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
2414         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
2415         R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
2416         R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
2417         R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
2418         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
2419         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
2420         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
2421         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);
2422         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);
2423         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);
2424         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);
2425         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);
2426         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);
2427         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);
2428         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);
2429         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);
2430         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);
2431         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);
2432         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);
2433         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);
2434         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);
2435         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);
2436         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);
2437         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
2438         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
2439         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
2440         R(d_min_scratch_buffer_size, S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8);
2441
2442         /* encoder registers */
2443         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
2444         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);
2445         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);
2446         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);
2447         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);
2448         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);
2449         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);
2450         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);
2451         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);
2452         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);
2453         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
2454         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
2455         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
2456         R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
2457
2458         if (!IS_MFCV10(dev))
2459                 goto done;
2460
2461         /* Initialize registers used in MFC v10 only.
2462          * Also, over-write the registers which have
2463          * a different offset for MFC v10.
2464          */
2465
2466         /* decoder registers */
2467         R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
2468         R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
2469
2470         /* encoder registers */
2471         R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
2472         R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
2473         R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
2474         R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
2475         R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
2476         R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
2477         R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
2478         R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
2479
2480 done:
2481         return &mfc_regs;
2482 #undef S5P_MFC_REG_ADDR
2483 #undef R
2484 }
2485
2486 /* Initialize opr function pointers for MFC v6 */
2487 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
2488         .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
2489         .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
2490         .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
2491         .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
2492         .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
2493         .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
2494         .alloc_dev_context_buffer =
2495                 s5p_mfc_alloc_dev_context_buffer_v6,
2496         .release_dev_context_buffer =
2497                 s5p_mfc_release_dev_context_buffer_v6,
2498         .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
2499         .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
2500         .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
2501         .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
2502         .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
2503         .try_run = s5p_mfc_try_run_v6,
2504         .clear_int_flags = s5p_mfc_clear_int_flags_v6,
2505         .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2506         .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2507         .get_dspl_status = s5p_mfc_get_dspl_status_v6,
2508         .get_dec_status = s5p_mfc_get_dec_status_v6,
2509         .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2510         .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2511         .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2512         .get_int_reason = s5p_mfc_get_int_reason_v6,
2513         .get_int_err = s5p_mfc_get_int_err_v6,
2514         .err_dec = s5p_mfc_err_dec_v6,
2515         .get_img_width = s5p_mfc_get_img_width_v6,
2516         .get_img_height = s5p_mfc_get_img_height_v6,
2517         .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2518         .get_mv_count = s5p_mfc_get_mv_count_v6,
2519         .get_inst_no = s5p_mfc_get_inst_no_v6,
2520         .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2521         .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2522         .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2523         .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2524         .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2525         .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2526         .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2527         .get_min_scratch_buf_size = s5p_mfc_get_min_scratch_buf_size,
2528         .get_e_min_scratch_buf_size = s5p_mfc_get_e_min_scratch_buf_size,
2529 };
2530
2531 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2532 {
2533         return &s5p_mfc_ops_v6;
2534 }