1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Samsung S5P Multi Format Codec v 5.0
5 * This file contains definitions of enums and structs used by the codec
8 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
9 * Kamil Debski, <k.debski@samsung.com>
12 #ifndef S5P_MFC_COMMON_H_
13 #define S5P_MFC_COMMON_H_
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-ioctl.h>
20 #include <media/videobuf2-v4l2.h>
22 #include "regs-mfc-v10.h"
24 #define S5P_MFC_NAME "s5p-mfc"
26 /* Definitions related to MFC memory */
28 /* Offset base used to differentiate between CAPTURE and OUTPUT
30 #define DST_QUEUE_OFF_BASE (1 << 30)
34 #define BANK_CTX_NUM 2
36 #define MFC_BANK1_ALIGN_ORDER 13
37 #define MFC_BANK2_ALIGN_ORDER 13
38 #define MFC_BASE_ALIGN_ORDER 17
40 #define MFC_FW_MAX_VERSIONS 2
42 #include <media/videobuf2-dma-contig.h>
45 #define MFC_MAX_EXTRA_DPB 5
46 #define MFC_MAX_BUFFERS 32
47 #define MFC_NUM_CONTEXTS 4
48 /* Interrupt timeout */
49 #define MFC_INT_TIMEOUT 2000
50 /* Busy wait timeout */
51 #define MFC_BW_TIMEOUT 500
52 /* Watchdog interval */
53 #define MFC_WATCHDOG_INTERVAL 1000
54 /* After how many executions watchdog should assume lock up */
55 #define MFC_WATCHDOG_CNT 10
56 #define MFC_NO_INSTANCE_SET -1
57 #define MFC_ENC_CAP_PLANE_COUNT 1
58 #define MFC_ENC_OUT_PLANE_COUNT 2
60 #define MFC_MAX_CTRLS 128
62 #define S5P_MFC_CODEC_NONE -1
63 #define S5P_MFC_CODEC_H264_DEC 0
64 #define S5P_MFC_CODEC_H264_MVC_DEC 1
65 #define S5P_MFC_CODEC_VC1_DEC 2
66 #define S5P_MFC_CODEC_MPEG4_DEC 3
67 #define S5P_MFC_CODEC_MPEG2_DEC 4
68 #define S5P_MFC_CODEC_H263_DEC 5
69 #define S5P_MFC_CODEC_VC1RCV_DEC 6
70 #define S5P_MFC_CODEC_VP8_DEC 7
71 #define S5P_MFC_CODEC_HEVC_DEC 17
72 #define S5P_MFC_CODEC_VP9_DEC 18
74 #define S5P_MFC_CODEC_H264_ENC 20
75 #define S5P_MFC_CODEC_H264_MVC_ENC 21
76 #define S5P_MFC_CODEC_MPEG4_ENC 22
77 #define S5P_MFC_CODEC_H263_ENC 23
78 #define S5P_MFC_CODEC_VP8_ENC 24
79 #define S5P_MFC_CODEC_HEVC_ENC 26
81 #define S5P_MFC_R2H_CMD_EMPTY 0
82 #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
83 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
84 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
85 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
86 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
87 #define S5P_MFC_R2H_CMD_SLEEP_RET 7
88 #define S5P_MFC_R2H_CMD_WAKEUP_RET 8
89 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
90 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
91 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
92 #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
93 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
94 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
95 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
96 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
97 #define S5P_MFC_R2H_CMD_ERR_RET 32
99 #define MFC_MAX_CLOCKS 4
101 #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
102 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
106 * enum s5p_mfc_fmt_type - type of the pixelformat
108 enum s5p_mfc_fmt_type {
115 * enum s5p_mfc_inst_type - The type of an MFC instance.
117 enum s5p_mfc_inst_type {
124 * enum s5p_mfc_inst_state - The state of an MFC instance.
126 enum s5p_mfc_inst_state {
131 MFCINST_HEAD_PRODUCED,
140 MFCINST_RES_CHANGE_INIT,
141 MFCINST_RES_CHANGE_FLUSH,
142 MFCINST_RES_CHANGE_END,
146 * enum s5p_mfc_queue_state - The state of buffer queue.
148 enum s5p_mfc_queue_state {
150 QUEUE_BUFS_REQUESTED,
156 * enum s5p_mfc_decode_arg - type of frame decoding
158 enum s5p_mfc_decode_arg {
164 enum s5p_mfc_fw_ver {
169 #define MFC_BUF_FLAG_USED (1 << 0)
170 #define MFC_BUF_FLAG_EOS (1 << 1)
175 * struct s5p_mfc_buf - MFC buffer
178 struct vb2_v4l2_buffer *b;
179 struct list_head list;
191 * struct s5p_mfc_pm - power management data structure
194 struct clk *clock_gate;
195 const char * const *clk_names;
196 struct clk *clocks[MFC_MAX_CLOCKS];
198 bool use_clock_gating;
200 struct device *device;
203 struct s5p_mfc_buf_size_v5 {
204 unsigned int h264_ctx;
205 unsigned int non_h264_ctx;
210 struct s5p_mfc_buf_size_v6 {
211 unsigned int dev_ctx;
212 unsigned int h264_dec_ctx;
213 unsigned int other_dec_ctx;
214 unsigned int h264_enc_ctx;
215 unsigned int hevc_enc_ctx;
216 unsigned int other_enc_ctx;
219 struct s5p_mfc_buf_size {
225 struct s5p_mfc_variant {
226 unsigned int version;
227 unsigned int port_num;
229 struct s5p_mfc_buf_size *buf_size;
230 char *fw_name[MFC_FW_MAX_VERSIONS];
231 const char *clk_names[MFC_MAX_CLOCKS];
233 bool use_clock_gating;
237 * struct s5p_mfc_priv_buf - represents internal used buffer
238 * @ofs: offset of each buffer, will be used for MFC
239 * @virt: kernel virtual address, only valid when the
240 * buffer accessed by driver
241 * @dma: DMA address, only valid when kernel DMA API used
242 * @size: size of the buffer
243 * @ctx: memory context (bank) used for this allocation
245 struct s5p_mfc_priv_buf {
254 * struct s5p_mfc_dev - The struct containing driver internal parameters.
256 * @v4l2_dev: v4l2_device
257 * @vfd_dec: video device for decoding
258 * @vfd_enc: video device for encoding
259 * @plat_dev: platform device
260 * @mem_dev: child devices of the memory banks
261 * @regs_base: base address of the MFC hw registers
263 * @dec_ctrl_handler: control framework handler for decoding
264 * @enc_ctrl_handler: control framework handler for encoding
265 * @pm: power management control
266 * @variant: MFC hardware variant information
267 * @num_inst: counter of active MFC instances
268 * @irqlock: lock for operations on videobuf2 queues
269 * @condlock: lock for changing/checking if a context is ready to be
271 * @mfc_mutex: lock for video_device
272 * @int_cond: variable used by the waitqueue
273 * @int_type: type of last interrupt
274 * @int_err: error number for last interrupt
275 * @queue: waitqueue for waiting for completion of device commands
276 * @fw_buf: the firmware buffer data structure
277 * @mem_size: size of the firmware operation memory
278 * @mem_base: base DMA address of the firmware operation memory
279 * @mem_bitmap: bitmap for managing MFC internal buffer allocations
280 * @mem_virt: virtual address of the firmware operation memory
281 * @dma_base: address of the beginning of memory banks
282 * @hw_lock: used for hardware locking
283 * @ctx: array of driver contexts
284 * @curr_ctx: number of the currently running context
285 * @ctx_work_bits: used to mark which contexts are waiting for hardware
286 * @watchdog_cnt: counter for the watchdog
287 * @watchdog_timer: timer for the watchdog
288 * @watchdog_workqueue: workqueue for the watchdog
289 * @watchdog_work: worker for the watchdog
290 * @enter_suspend: flag set when entering suspend
291 * @ctx_buf: common context memory (MFCv6)
292 * @warn_start: hardware error code from which warnings start
293 * @mfc_ops: ops structure holding HW operation function pointers
294 * @mfc_cmds: cmd structure holding HW commands function pointers
295 * @mfc_regs: structure holding MFC registers
296 * @fw_ver: loaded firmware sub-version
297 * @fw_get_done: flag set when request_firmware() is complete and
299 * @risc_on: flag indicates RISC is on or off
303 struct v4l2_device v4l2_dev;
304 struct video_device *vfd_dec;
305 struct video_device *vfd_enc;
306 struct platform_device *plat_dev;
307 struct device *mem_dev[BANK_CTX_NUM];
308 void __iomem *regs_base;
310 struct v4l2_ctrl_handler dec_ctrl_handler;
311 struct v4l2_ctrl_handler enc_ctrl_handler;
312 struct s5p_mfc_pm pm;
313 const struct s5p_mfc_variant *variant;
315 spinlock_t irqlock; /* lock when operating on context */
316 spinlock_t condlock; /* lock when changing/checking if a context is
317 ready to be processed */
318 struct mutex mfc_mutex; /* video_device lock */
321 unsigned int int_err;
322 wait_queue_head_t queue;
323 struct s5p_mfc_priv_buf fw_buf;
326 unsigned long *mem_bitmap;
328 dma_addr_t dma_base[BANK_CTX_NUM];
329 unsigned long hw_lock;
330 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
332 unsigned long ctx_work_bits;
333 atomic_t watchdog_cnt;
334 struct timer_list watchdog_timer;
335 struct workqueue_struct *watchdog_workqueue;
336 struct work_struct watchdog_work;
337 unsigned long enter_suspend;
339 struct s5p_mfc_priv_buf ctx_buf;
341 struct s5p_mfc_hw_ops *mfc_ops;
342 struct s5p_mfc_hw_cmds *mfc_cmds;
343 const struct s5p_mfc_regs *mfc_regs;
344 enum s5p_mfc_fw_ver fw_ver;
346 bool risc_on; /* indicates if RISC is on or off */
350 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
352 struct s5p_mfc_h264_enc_params {
353 enum v4l2_mpeg_video_h264_profile profile;
354 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
355 s8 loop_filter_alpha;
357 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
367 u16 vui_ext_sar_width;
368 u16 vui_ext_sar_height;
376 enum v4l2_mpeg_video_h264_level level_v4l2;
383 u8 hier_qp_layer_qp[7];
384 u8 sei_frame_packing;
385 u8 sei_fp_curr_frame_0;
386 u8 sei_fp_arrangement_type;
395 u32 aso_slice_order[8];
399 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
401 struct s5p_mfc_mpeg4_enc_params {
403 enum v4l2_mpeg_video_mpeg4_profile profile;
405 /* Common for MPEG4, H263 */
413 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
418 * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
420 struct s5p_mfc_vp8_enc_params {
422 enum v4l2_vp8_num_partitions num_partitions;
423 enum v4l2_vp8_num_ref_frames num_ref;
426 u32 golden_frame_ref_period;
427 enum v4l2_vp8_golden_frame_sel golden_frame_sel;
437 struct s5p_mfc_hevc_enc_params {
438 enum v4l2_mpeg_video_hevc_profile profile;
440 enum v4l2_mpeg_video_h264_level level_v4l2;
452 u8 max_partition_depth;
456 s32 lf_beta_offset_div2;
457 s32 lf_tc_offset_div2;
459 u8 loopfilter_disable;
460 u8 loopfilter_across;
461 u8 nal_control_length_filed;
462 u8 nal_control_user_ref;
463 u8 nal_control_store_ref;
464 u8 const_intra_period_enable;
465 u8 lossless_cu_enable;
469 enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
472 u32 hier_bit_layer[7];
474 u8 general_pb_enable;
475 u8 temporal_id_enable;
476 u8 strong_intra_smooth;
477 u8 intra_pu_split_disable;
478 u8 tmv_prediction_disable;
481 u8 encoding_nostartcode_enable;
482 u8 size_of_length_field;
483 u8 prepend_sps_pps_to_idr;
487 * struct s5p_mfc_enc_params - general encoding parameters
489 struct s5p_mfc_enc_params {
496 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
499 u16 intra_refresh_mb;
507 u16 rc_reaction_coeff;
511 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
512 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
513 int fixed_target_bit;
516 u32 rc_framerate_num;
517 u32 rc_framerate_denom;
520 struct s5p_mfc_h264_enc_params h264;
521 struct s5p_mfc_mpeg4_enc_params mpeg4;
522 struct s5p_mfc_vp8_enc_params vp8;
523 struct s5p_mfc_hevc_enc_params hevc;
529 * struct s5p_mfc_codec_ops - codec ops, used by encoding
531 struct s5p_mfc_codec_ops {
532 /* initialization routines */
533 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
534 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
535 /* execution routines */
536 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
537 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
540 #define call_cop(c, op, args...) \
541 (((c)->c_ops->op) ? \
542 ((c)->c_ops->op(args)) : 0)
545 * struct s5p_mfc_ctx - This struct contains the instance context
547 * @dev: pointer to the s5p_mfc_dev of the device
548 * @fh: struct v4l2_fh
549 * @num: number of the context that this structure describes
550 * @int_cond: variable used by the waitqueue
551 * @int_type: type of the last interrupt
552 * @int_err: error number received from MFC hw in the interrupt
553 * @queue: waitqueue that can be used to wait for this context to
555 * @src_fmt: source pixelformat information
556 * @dst_fmt: destination pixelformat information
557 * @vq_src: vb2 queue for source buffers
558 * @vq_dst: vb2 queue for destination buffers
559 * @src_queue: driver internal queue for source buffers
560 * @dst_queue: driver internal queue for destination buffers
561 * @src_queue_cnt: number of buffers queued on the source internal queue
562 * @dst_queue_cnt: number of buffers queued on the dest internal queue
563 * @type: type of the instance - decoder or encoder
564 * @state: state of the context
565 * @inst_no: number of hw instance associated with the context
566 * @img_width: width of the image that is decoded or encoded
567 * @img_height: height of the image that is decoded or encoded
568 * @buf_width: width of the buffer for processed image
569 * @buf_height: height of the buffer for processed image
570 * @luma_size: size of a luma plane
571 * @chroma_size: size of a chroma plane
572 * @mv_size: size of a motion vectors buffer
573 * @consumed_stream: number of bytes that have been used so far from the
575 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
577 * @head_processed: flag mentioning whether the header data is processed
579 * @bank1: handle to memory allocated for temporary buffers from
581 * @bank2: handle to memory allocated for temporary buffers from
583 * @capture_state: state of the capture buffers queue
584 * @output_state: state of the output buffers queue
585 * @src_bufs: information on allocated source buffers
586 * @src_bufs_cnt: number of allocated source buffers
587 * @dst_bufs: information on allocated destination buffers
588 * @dst_bufs_cnt: number of allocated destination buffers
589 * @sequence: counter for the sequence number for v4l2
590 * @dec_dst_flag: flags for buffers queued in the hardware
591 * @dec_src_buf_size: size of the buffer for source buffers in decoding
592 * @codec_mode: number of codec mode used by MFC hw
593 * @slice_interface: slice interface flag
594 * @loop_filter_mpeg4: loop filter for MPEG4 flag
595 * @display_delay: value of the display delay for H264
596 * @display_delay_enable: display delay for H264 enable flag
597 * @after_packed_pb: flag used to track buffer when stream is in
599 * @sei_fp_parse: enable/disable parsing of frame packing SEI information
600 * @pb_count: count of the DPB buffers required by MFC hw
601 * @total_dpb_count: count of DPB buffers with additional buffers
602 * requested by the application
603 * @ctx: context buffer information
604 * @dsc: descriptor buffer information
605 * @shm: shared memory buffer information
606 * @mv_count: number of MV buffers allocated for decoding
607 * @enc_params: encoding parameters for MFC
608 * @enc_dst_buf_size: size of the buffers for encoder output
609 * @luma_dpb_size: dpb buffer size for luma
610 * @chroma_dpb_size: dpb buffer size for chroma
611 * @me_buffer_size: size of the motion estimation buffer
612 * @tmv_buffer_size: size of temporal predictor motion vector buffer
613 * @frame_type: used to force the type of the next encoded frame
614 * @ref_queue: list of the reference buffers for encoding
615 * @force_frame_type: encoder's frame type forcing control
616 * @ref_queue_cnt: number of the buffers in the reference list
617 * @slice_size: slice size
618 * @slice_mode: mode of dividing frames into slices
619 * @c_ops: ops for encoding
620 * @ctrls: array of controls, used when adding controls to the
621 * v4l2 control framework
622 * @ctrl_handler: handler for v4l2 framework
623 * @scratch_buf_size: scratch buffer size
626 struct s5p_mfc_dev *dev;
633 unsigned int int_err;
634 wait_queue_head_t queue;
636 struct s5p_mfc_fmt *src_fmt;
637 struct s5p_mfc_fmt *dst_fmt;
639 struct vb2_queue vq_src;
640 struct vb2_queue vq_dst;
642 struct list_head src_queue;
643 struct list_head dst_queue;
645 unsigned int src_queue_cnt;
646 unsigned int dst_queue_cnt;
648 enum s5p_mfc_inst_type type;
649 enum s5p_mfc_inst_state state;
652 /* Image parameters */
662 unsigned long consumed_stream;
664 unsigned int dpb_flush_flag;
665 unsigned int head_processed;
667 struct s5p_mfc_priv_buf bank1;
668 struct s5p_mfc_priv_buf bank2;
670 enum s5p_mfc_queue_state capture_state;
671 enum s5p_mfc_queue_state output_state;
673 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
675 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
678 unsigned int sequence;
679 unsigned long dec_dst_flag;
680 size_t dec_src_buf_size;
685 int loop_filter_mpeg4;
687 int display_delay_enable;
695 struct s5p_mfc_priv_buf ctx;
696 struct s5p_mfc_priv_buf dsc;
697 struct s5p_mfc_priv_buf shm;
699 struct s5p_mfc_enc_params enc_params;
701 size_t enc_dst_buf_size;
702 size_t luma_dpb_size;
703 size_t chroma_dpb_size;
704 size_t me_buffer_size;
705 size_t tmv_buffer_size;
707 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
709 struct list_head ref_queue;
710 unsigned int ref_queue_cnt;
712 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
718 const struct s5p_mfc_codec_ops *c_ops;
720 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
721 struct v4l2_ctrl_handler ctrl_handler;
722 size_t scratch_buf_size;
726 * struct s5p_mfc_fmt - structure used to store information about pixelformats
732 enum s5p_mfc_fmt_type type;
739 * struct mfc_control - structure used to store information about MFC controls
740 * it is used to initialize the control framework.
744 enum v4l2_ctrl_type type;
745 __u8 name[32]; /* Whatever */
746 __s32 minimum; /* Note signedness */
749 __u32 menu_skip_mask;
756 /* Macro for making hardware specific calls */
757 #define s5p_mfc_hw_call(f, op, args...) \
758 ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
760 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
761 #define ctrl_to_ctx(__ctrl) \
762 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
764 void clear_work_bit(struct s5p_mfc_ctx *ctx);
765 void set_work_bit(struct s5p_mfc_ctx *ctx);
766 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
767 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
768 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
769 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
771 #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
772 (dev->variant->port_num ? 1 : 0) : 0) : 0)
773 #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
774 #define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
775 #define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0)
776 #define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0)
777 #define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0)
778 #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
780 #define MFC_V5_BIT BIT(0)
781 #define MFC_V6_BIT BIT(1)
782 #define MFC_V7_BIT BIT(2)
783 #define MFC_V8_BIT BIT(3)
784 #define MFC_V10_BIT BIT(5)
786 #define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
787 MFC_V8_BIT | MFC_V10_BIT)
788 #define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
790 #define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
792 #endif /* S5P_MFC_COMMON_H_ */