drivers/media/platform/samsung/exynos4-is/fimc-core.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver
   4  *
   5  * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
   6  * Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/types.h>
  12 #include <linux/errno.h>
  13 #include <linux/bug.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/list.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/slab.h>
  23 #include <linux/clk.h>
  24 #include <media/v4l2-ioctl.h>
  25 #include <media/videobuf2-v4l2.h>
  26 #include <media/videobuf2-dma-contig.h>
  27
  28 #include "fimc-core.h"
  29 #include "fimc-reg.h"
  30 #include "media-dev.h"
  31
  32 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  33         "sclk_fimc", "fimc"
  34 };
  35
  36 static struct fimc_fmt fimc_formats[] = {
  37         {
  38                 .fourcc         = V4L2_PIX_FMT_RGB565,
  39                 .depth          = { 16 },
  40                 .color          = FIMC_FMT_RGB565,
  41                 .memplanes      = 1,
  42                 .colplanes      = 1,
  43                 .flags          = FMT_FLAGS_M2M,
  44         }, {
  45                 .fourcc         = V4L2_PIX_FMT_BGR666,
  46                 .depth          = { 32 },
  47                 .color          = FIMC_FMT_RGB666,
  48                 .memplanes      = 1,
  49                 .colplanes      = 1,
  50                 .flags          = FMT_FLAGS_M2M,
  51         }, {
  52                 .fourcc         = V4L2_PIX_FMT_BGR32,
  53                 .depth          = { 32 },
  54                 .color          = FIMC_FMT_RGB888,
  55                 .memplanes      = 1,
  56                 .colplanes      = 1,
  57                 .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  58         }, {
  59                 .fourcc         = V4L2_PIX_FMT_RGB555,
  60                 .depth          = { 16 },
  61                 .color          = FIMC_FMT_RGB555,
  62                 .memplanes      = 1,
  63                 .colplanes      = 1,
  64                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  65         }, {
  66                 .fourcc         = V4L2_PIX_FMT_RGB444,
  67                 .depth          = { 16 },
  68                 .color          = FIMC_FMT_RGB444,
  69                 .memplanes      = 1,
  70                 .colplanes      = 1,
  71                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  72         }, {
  73                 .mbus_code      = MEDIA_BUS_FMT_YUV10_1X30,
  74                 .flags          = FMT_FLAGS_WRITEBACK,
  75         }, {
  76                 .fourcc         = V4L2_PIX_FMT_YUYV,
  77                 .depth          = { 16 },
  78                 .color          = FIMC_FMT_YCBYCR422,
  79                 .memplanes      = 1,
  80                 .colplanes      = 1,
  81                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
  82                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  83         }, {
  84                 .fourcc         = V4L2_PIX_FMT_UYVY,
  85                 .depth          = { 16 },
  86                 .color          = FIMC_FMT_CBYCRY422,
  87                 .memplanes      = 1,
  88                 .colplanes      = 1,
  89                 .mbus_code      = MEDIA_BUS_FMT_UYVY8_2X8,
  90                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  91         }, {
  92                 .fourcc         = V4L2_PIX_FMT_VYUY,
  93                 .depth          = { 16 },
  94                 .color          = FIMC_FMT_CRYCBY422,
  95                 .memplanes      = 1,
  96                 .colplanes      = 1,
  97                 .mbus_code      = MEDIA_BUS_FMT_VYUY8_2X8,
  98                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  99         }, {
 100                 .fourcc         = V4L2_PIX_FMT_YVYU,
 101                 .depth          = { 16 },
 102                 .color          = FIMC_FMT_YCRYCB422,
 103                 .memplanes      = 1,
 104                 .colplanes      = 1,
 105                 .mbus_code      = MEDIA_BUS_FMT_YVYU8_2X8,
 106                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 107         }, {
 108                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 109                 .depth          = { 16 },
 110                 .color          = FIMC_FMT_YCBYCR422,
 111                 .memplanes      = 1,
 112                 .colplanes      = 3,
 113                 .flags          = FMT_FLAGS_M2M,
 114         }, {
 115                 .fourcc         = V4L2_PIX_FMT_NV16,
 116                 .depth          = { 16 },
 117                 .color          = FIMC_FMT_YCBYCR422,
 118                 .memplanes      = 1,
 119                 .colplanes      = 2,
 120                 .flags          = FMT_FLAGS_M2M,
 121         }, {
 122                 .fourcc         = V4L2_PIX_FMT_NV61,
 123                 .depth          = { 16 },
 124                 .color          = FIMC_FMT_YCRYCB422,
 125                 .memplanes      = 1,
 126                 .colplanes      = 2,
 127                 .flags          = FMT_FLAGS_M2M,
 128         }, {
 129                 .fourcc         = V4L2_PIX_FMT_YUV420,
 130                 .depth          = { 12 },
 131                 .color          = FIMC_FMT_YCBCR420,
 132                 .memplanes      = 1,
 133                 .colplanes      = 3,
 134                 .flags          = FMT_FLAGS_M2M,
 135         }, {
 136                 .fourcc         = V4L2_PIX_FMT_NV12,
 137                 .depth          = { 12 },
 138                 .color          = FIMC_FMT_YCBCR420,
 139                 .memplanes      = 1,
 140                 .colplanes      = 2,
 141                 .flags          = FMT_FLAGS_M2M,
 142         }, {
 143                 .fourcc         = V4L2_PIX_FMT_NV12M,
 144                 .color          = FIMC_FMT_YCBCR420,
 145                 .depth          = { 8, 4 },
 146                 .memplanes      = 2,
 147                 .colplanes      = 2,
 148                 .flags          = FMT_FLAGS_M2M,
 149         }, {
 150                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 151                 .color          = FIMC_FMT_YCBCR420,
 152                 .depth          = { 8, 2, 2 },
 153                 .memplanes      = 3,
 154                 .colplanes      = 3,
 155                 .flags          = FMT_FLAGS_M2M,
 156         }, {
 157                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 158                 .color          = FIMC_FMT_YCBCR420,
 159                 .depth          = { 8, 4 },
 160                 .memplanes      = 2,
 161                 .colplanes      = 2,
 162                 .flags          = FMT_FLAGS_M2M,
 163         }, {
 164                 .fourcc         = V4L2_PIX_FMT_JPEG,
 165                 .color          = FIMC_FMT_JPEG,
 166                 .depth          = { 8 },
 167                 .memplanes      = 1,
 168                 .colplanes      = 1,
 169                 .mbus_code      = MEDIA_BUS_FMT_JPEG_1X8,
 170                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 171         }, {
 172                 .fourcc         = V4L2_PIX_FMT_S5C_UYVY_JPG,
 173                 .color          = FIMC_FMT_YUYV_JPEG,
 174                 .depth          = { 8 },
 175                 .memplanes      = 2,
 176                 .colplanes      = 1,
 177                 .mdataplanes    = 0x2, /* plane 1 holds frame meta data */
 178                 .mbus_code      = MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8,
 179                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 180         },
 181 };
 182
 183 struct fimc_fmt *fimc_get_format(unsigned int index)
 184 {
 185         if (index >= ARRAY_SIZE(fimc_formats))
 186                 return NULL;
 187
 188         return &fimc_formats[index];
 189 }
 190
 191 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 192                             int dw, int dh, int rotation)
 193 {
 194         if (rotation == 90 || rotation == 270)
 195                 swap(dw, dh);
 196
 197         if (!ctx->scaler.enabled)
 198                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 199
 200         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 201                 return -EINVAL;
 202
 203         return 0;
 204 }
 205
 206 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 207 {
 208         u32 sh = 6;
 209
 210         if (src >= 64 * tar)
 211                 return -EINVAL;
 212
 213         while (sh--) {
 214                 u32 tmp = 1 << sh;
 215                 if (src >= tar * tmp) {
 216                         *shift = sh;
 217                         *ratio = tmp;
 218                         return 0;
 219                 }
 220         }
 221         *shift = 0;
 222         *ratio = 1;
 223         return 0;
 224 }
 225
 226 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 227 {
 228         const struct fimc_variant *variant = ctx->fimc_dev->variant;
 229         struct device *dev = &ctx->fimc_dev->pdev->dev;
 230         struct fimc_scaler *sc = &ctx->scaler;
 231         struct fimc_frame *s_frame = &ctx->s_frame;
 232         struct fimc_frame *d_frame = &ctx->d_frame;
 233         int tx, ty, sx, sy;
 234         int ret;
 235
 236         if (ctx->rotation == 90 || ctx->rotation == 270) {
 237                 ty = d_frame->width;
 238                 tx = d_frame->height;
 239         } else {
 240                 tx = d_frame->width;
 241                 ty = d_frame->height;
 242         }
 243         if (tx <= 0 || ty <= 0) {
 244                 dev_err(dev, "Invalid target size: %dx%d\n", tx, ty);
 245                 return -EINVAL;
 246         }
 247
 248         sx = s_frame->width;
 249         sy = s_frame->height;
 250         if (sx <= 0 || sy <= 0) {
 251                 dev_err(dev, "Invalid source size: %dx%d\n", sx, sy);
 252                 return -EINVAL;
 253         }
 254         sc->real_width = sx;
 255         sc->real_height = sy;
 256
 257         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 258         if (ret)
 259                 return ret;
 260
 261         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 262         if (ret)
 263                 return ret;
 264
 265         sc->pre_dst_width = sx / sc->pre_hratio;
 266         sc->pre_dst_height = sy / sc->pre_vratio;
 267
 268         if (variant->has_mainscaler_ext) {
 269                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 270                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 271         } else {
 272                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 273                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 274
 275         }
 276
 277         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 278         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 279
 280         /* check to see if input and output size/format differ */
 281         if (s_frame->fmt->color == d_frame->fmt->color
 282                 && s_frame->width == d_frame->width
 283                 && s_frame->height == d_frame->height)
 284                 sc->copy_mode = 1;
 285         else
 286                 sc->copy_mode = 0;
 287
 288         return 0;
 289 }
 290
 291 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 292 {
 293         struct fimc_dev *fimc = priv;
 294         struct fimc_ctx *ctx;
 295
 296         fimc_hw_clear_irq(fimc);
 297
 298         spin_lock(&fimc->slock);
 299
 300         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 301                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 302                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 303                         wake_up(&fimc->irq_queue);
 304                         goto out;
 305                 }
 306                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 307                 if (ctx != NULL) {
 308                         spin_unlock(&fimc->slock);
 309                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 310
 311                         if (ctx->state & FIMC_CTX_SHUT) {
 312                                 ctx->state &= ~FIMC_CTX_SHUT;
 313                                 wake_up(&fimc->irq_queue);
 314                         }
 315                         return IRQ_HANDLED;
 316                 }
 317         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 318                 int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) &&
 319                                 fimc->vid_cap.reqbufs_count == 1;
 320                 fimc_capture_irq_handler(fimc, !last_buf);
 321         }
 322 out:
 323         spin_unlock(&fimc->slock);
 324         return IRQ_HANDLED;
 325 }
 326
 327 /* The color format (colplanes, memplanes) must be already configured. */
 328 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 329                       struct fimc_frame *frame, struct fimc_addr *addr)
 330 {
 331         int ret = 0;
 332         u32 pix_size;
 333
 334         if (vb == NULL || frame == NULL)
 335                 return -EINVAL;
 336
 337         pix_size = frame->width * frame->height;
 338
 339         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 340                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 341
 342         addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 343
 344         if (frame->fmt->memplanes == 1) {
 345                 switch (frame->fmt->colplanes) {
 346                 case 1:
 347                         addr->cb = 0;
 348                         addr->cr = 0;
 349                         break;
 350                 case 2:
 351                         /* decompose Y into Y/Cb */
 352                         addr->cb = (u32)(addr->y + pix_size);
 353                         addr->cr = 0;
 354                         break;
 355                 case 3:
 356                         addr->cb = (u32)(addr->y + pix_size);
 357                         /* decompose Y into Y/Cb/Cr */
 358                         if (FIMC_FMT_YCBCR420 == frame->fmt->color)
 359                                 addr->cr = (u32)(addr->cb + (pix_size >> 2));
 360                         else /* 422 */
 361                                 addr->cr = (u32)(addr->cb + (pix_size >> 1));
 362                         break;
 363                 default:
 364                         return -EINVAL;
 365                 }
 366         } else if (!frame->fmt->mdataplanes) {
 367                 if (frame->fmt->memplanes >= 2)
 368                         addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 369
 370                 if (frame->fmt->memplanes == 3)
 371                         addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 372         }
 373
 374         dbg("DMA ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 375             addr->y, addr->cb, addr->cr, ret);
 376
 377         return ret;
 378 }
 379
 380 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 381 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 382 {
 383         /* The one only mode supported in SoC. */
 384         ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 385         ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 386
 387         /* Set order for 1 plane input formats. */
 388         switch (ctx->s_frame.fmt->color) {
 389         case FIMC_FMT_YCRYCB422:
 390                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
 391                 break;
 392         case FIMC_FMT_CBYCRY422:
 393                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
 394                 break;
 395         case FIMC_FMT_CRYCBY422:
 396                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
 397                 break;
 398         case FIMC_FMT_YCBYCR422:
 399         default:
 400                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
 401                 break;
 402         }
 403         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 404
 405         switch (ctx->d_frame.fmt->color) {
 406         case FIMC_FMT_YCRYCB422:
 407                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
 408                 break;
 409         case FIMC_FMT_CBYCRY422:
 410                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
 411                 break;
 412         case FIMC_FMT_CRYCBY422:
 413                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
 414                 break;
 415         case FIMC_FMT_YCBYCR422:
 416         default:
 417                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
 418                 break;
 419         }
 420         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 421 }
 422
 423 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 424 {
 425         bool pix_hoff = ctx->fimc_dev->drv_data->dma_pix_hoff;
 426         u32 i, depth = 0;
 427
 428         for (i = 0; i < f->fmt->memplanes; i++)
 429                 depth += f->fmt->depth[i];
 430
 431         f->dma_offset.y_h = f->offs_h;
 432         if (!pix_hoff)
 433                 f->dma_offset.y_h *= (depth >> 3);
 434
 435         f->dma_offset.y_v = f->offs_v;
 436
 437         f->dma_offset.cb_h = f->offs_h;
 438         f->dma_offset.cb_v = f->offs_v;
 439
 440         f->dma_offset.cr_h = f->offs_h;
 441         f->dma_offset.cr_v = f->offs_v;
 442
 443         if (!pix_hoff) {
 444                 if (f->fmt->colplanes == 3) {
 445                         f->dma_offset.cb_h >>= 1;
 446                         f->dma_offset.cr_h >>= 1;
 447                 }
 448                 if (f->fmt->color == FIMC_FMT_YCBCR420) {
 449                         f->dma_offset.cb_v >>= 1;
 450                         f->dma_offset.cr_v >>= 1;
 451                 }
 452         }
 453
 454         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 455             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 456 }
 457
 458 static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx)
 459 {
 460         struct fimc_effect *effect = &ctx->effect;
 461
 462         switch (colorfx) {
 463         case V4L2_COLORFX_NONE:
 464                 effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 465                 break;
 466         case V4L2_COLORFX_BW:
 467                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 468                 effect->pat_cb = 128;
 469                 effect->pat_cr = 128;
 470                 break;
 471         case V4L2_COLORFX_SEPIA:
 472                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 473                 effect->pat_cb = 115;
 474                 effect->pat_cr = 145;
 475                 break;
 476         case V4L2_COLORFX_NEGATIVE:
 477                 effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE;
 478                 break;
 479         case V4L2_COLORFX_EMBOSS:
 480                 effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING;
 481                 break;
 482         case V4L2_COLORFX_ART_FREEZE:
 483                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE;
 484                 break;
 485         case V4L2_COLORFX_SILHOUETTE:
 486                 effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE;
 487                 break;
 488         case V4L2_COLORFX_SET_CBCR:
 489                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 490                 effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8;
 491                 effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff;
 492                 break;
 493         default:
 494                 return -EINVAL;
 495         }
 496
 497         return 0;
 498 }
 499
 500 /*
 501  * V4L2 controls handling
 502  */
 503 #define ctrl_to_ctx(__ctrl) \
 504         container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler)
 505
 506 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 507 {
 508         struct fimc_dev *fimc = ctx->fimc_dev;
 509         const struct fimc_variant *variant = fimc->variant;
 510         int ret = 0;
 511
 512         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 513                 return 0;
 514
 515         switch (ctrl->id) {
 516         case V4L2_CID_HFLIP:
 517                 ctx->hflip = ctrl->val;
 518                 break;
 519
 520         case V4L2_CID_VFLIP:
 521                 ctx->vflip = ctrl->val;
 522                 break;
 523
 524         case V4L2_CID_ROTATE:
 525                 if (fimc_capture_pending(fimc)) {
 526                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 527                                         ctx->s_frame.height, ctx->d_frame.width,
 528                                         ctx->d_frame.height, ctrl->val);
 529                         if (ret)
 530                                 return -EINVAL;
 531                 }
 532                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 533                     !variant->has_out_rot)
 534                         return -EINVAL;
 535
 536                 ctx->rotation = ctrl->val;
 537                 break;
 538
 539         case V4L2_CID_ALPHA_COMPONENT:
 540                 ctx->d_frame.alpha = ctrl->val;
 541                 break;
 542
 543         case V4L2_CID_COLORFX:
 544                 ret = fimc_set_color_effect(ctx, ctrl->val);
 545                 if (ret)
 546                         return ret;
 547                 break;
 548         }
 549
 550         ctx->state |= FIMC_PARAMS;
 551         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 552         return 0;
 553 }
 554
 555 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 556 {
 557         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 558         unsigned long flags;
 559         int ret;
 560
 561         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 562         ret = __fimc_s_ctrl(ctx, ctrl);
 563         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 564
 565         return ret;
 566 }
 567
 568 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 569         .s_ctrl = fimc_s_ctrl,
 570 };
 571
 572 int fimc_ctrls_create(struct fimc_ctx *ctx)
 573 {
 574         unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 575         struct fimc_ctrls *ctrls = &ctx->ctrls;
 576         struct v4l2_ctrl_handler *handler = &ctrls->handler;
 577
 578         if (ctx->ctrls.ready)
 579                 return 0;
 580
 581         v4l2_ctrl_handler_init(handler, 6);
 582
 583         ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 584                                         V4L2_CID_ROTATE, 0, 270, 90, 0);
 585         ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 586                                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 587         ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 588                                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 589
 590         if (ctx->fimc_dev->drv_data->alpha_color)
 591                 ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 592                                         V4L2_CID_ALPHA_COMPONENT,
 593                                         0, max_alpha, 1, 0);
 594         else
 595                 ctrls->alpha = NULL;
 596
 597         ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops,
 598                                 V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR,
 599                                 ~0x983f, V4L2_COLORFX_NONE);
 600
 601         ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 602                                 V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0);
 603
 604         ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 605
 606         if (!handler->error) {
 607                 v4l2_ctrl_cluster(2, &ctrls->colorfx);
 608                 ctrls->ready = true;
 609         }
 610
 611         return handler->error;
 612 }
 613
 614 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 615 {
 616         struct fimc_ctrls *ctrls = &ctx->ctrls;
 617
 618         if (ctrls->ready) {
 619                 v4l2_ctrl_handler_free(&ctrls->handler);
 620                 ctrls->ready = false;
 621                 ctrls->alpha = NULL;
 622         }
 623 }
 624
 625 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 626 {
 627         unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 628         struct fimc_ctrls *ctrls = &ctx->ctrls;
 629
 630         if (!ctrls->ready)
 631                 return;
 632
 633         mutex_lock(ctrls->handler.lock);
 634         v4l2_ctrl_activate(ctrls->rotate, active);
 635         v4l2_ctrl_activate(ctrls->hflip, active);
 636         v4l2_ctrl_activate(ctrls->vflip, active);
 637         v4l2_ctrl_activate(ctrls->colorfx, active);
 638         if (ctrls->alpha)
 639                 v4l2_ctrl_activate(ctrls->alpha, active && has_alpha);
 640
 641         if (active) {
 642                 fimc_set_color_effect(ctx, ctrls->colorfx->cur.val);
 643                 ctx->rotation = ctrls->rotate->val;
 644                 ctx->hflip    = ctrls->hflip->val;
 645                 ctx->vflip    = ctrls->vflip->val;
 646         } else {
 647                 ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 648                 ctx->rotation = 0;
 649                 ctx->hflip    = 0;
 650                 ctx->vflip    = 0;
 651         }
 652         mutex_unlock(ctrls->handler.lock);
 653 }
 654
 655 /* Update maximum value of the alpha color control */
 656 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 657 {
 658         struct fimc_dev *fimc = ctx->fimc_dev;
 659         struct v4l2_ctrl *ctrl = ctx->ctrls.alpha;
 660
 661         if (ctrl == NULL || !fimc->drv_data->alpha_color)
 662                 return;
 663
 664         v4l2_ctrl_lock(ctrl);
 665         ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 666
 667         if (ctrl->cur.val > ctrl->maximum)
 668                 ctrl->cur.val = ctrl->maximum;
 669
 670         v4l2_ctrl_unlock(ctrl);
 671 }
 672
 673 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f)
 674 {
 675         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 676         int i;
 677
 678         pixm->width = frame->o_width;
 679         pixm->height = frame->o_height;
 680         pixm->field = V4L2_FIELD_NONE;
 681         pixm->pixelformat = frame->fmt->fourcc;
 682         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 683         pixm->num_planes = frame->fmt->memplanes;
 684
 685         for (i = 0; i < pixm->num_planes; ++i) {
 686                 pixm->plane_fmt[i].bytesperline = frame->bytesperline[i];
 687                 pixm->plane_fmt[i].sizeimage = frame->payload[i];
 688         }
 689 }
 690
 691 /**
 692  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 693  * @fmt: fimc pixel format description (input)
 694  * @width: requested pixel width
 695  * @height: requested pixel height
 696  * @pix: multi-plane format to adjust
 697  */
 698 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 699                                struct v4l2_pix_format_mplane *pix)
 700 {
 701         u32 bytesperline = 0;
 702         int i;
 703
 704         pix->colorspace = V4L2_COLORSPACE_JPEG;
 705         pix->field = V4L2_FIELD_NONE;
 706         pix->num_planes = fmt->memplanes;
 707         pix->pixelformat = fmt->fourcc;
 708         pix->height = height;
 709         pix->width = width;
 710
 711         for (i = 0; i < pix->num_planes; ++i) {
 712                 struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i];
 713                 u32 bpl = plane_fmt->bytesperline;
 714                 u32 sizeimage;
 715
 716                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 717                         bpl = pix->width; /* Planar */
 718
 719                 if (fmt->colplanes == 1 && /* Packed */
 720                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 721                         bpl = (pix->width * fmt->depth[0]) / 8;
 722                 /*
 723                  * Currently bytesperline for each plane is same, except
 724                  * V4L2_PIX_FMT_YUV420M format. This calculation may need
 725                  * to be changed when other multi-planar formats are added
 726                  * to the fimc_formats[] array.
 727                  */
 728                 if (i == 0)
 729                         bytesperline = bpl;
 730                 else if (i == 1 && fmt->memplanes == 3)
 731                         bytesperline /= 2;
 732
 733                 plane_fmt->bytesperline = bytesperline;
 734                 sizeimage = pix->width * pix->height * fmt->depth[i] / 8;
 735
 736                 /* Ensure full last row for tiled formats */
 737                 if (tiled_fmt(fmt)) {
 738                         /* 64 * 32 * plane_fmt->bytesperline / 64 */
 739                         u32 row_size = plane_fmt->bytesperline * 32;
 740
 741                         sizeimage = roundup(sizeimage, row_size);
 742                 }
 743
 744                 plane_fmt->sizeimage = max(sizeimage, plane_fmt->sizeimage);
 745         }
 746 }
 747
 748 /**
 749  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 750  * @pixelformat: fourcc to match, ignored if null
 751  * @mbus_code: media bus code to match, ignored if null
 752  * @mask: the color flags to match
 753  * @index: offset in the fimc_formats array, ignored if negative
 754  */
 755 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
 756                                   unsigned int mask, int index)
 757 {
 758         struct fimc_fmt *fmt, *def_fmt = NULL;
 759         unsigned int i;
 760         int id = 0;
 761
 762         if (index >= (int)ARRAY_SIZE(fimc_formats))
 763                 return NULL;
 764
 765         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 766                 fmt = &fimc_formats[i];
 767                 if (!(fmt->flags & mask))
 768                         continue;
 769                 if (pixelformat && fmt->fourcc == *pixelformat)
 770                         return fmt;
 771                 if (mbus_code && fmt->mbus_code == *mbus_code)
 772                         return fmt;
 773                 if (index == id)
 774                         def_fmt = fmt;
 775                 id++;
 776         }
 777         return def_fmt;
 778 }
 779
 780 static void fimc_clk_put(struct fimc_dev *fimc)
 781 {
 782         int i;
 783         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 784                 if (IS_ERR(fimc->clock[i]))
 785                         continue;
 786                 clk_unprepare(fimc->clock[i]);
 787                 clk_put(fimc->clock[i]);
 788                 fimc->clock[i] = ERR_PTR(-EINVAL);
 789         }
 790 }
 791
 792 static int fimc_clk_get(struct fimc_dev *fimc)
 793 {
 794         int i, ret;
 795
 796         for (i = 0; i < MAX_FIMC_CLOCKS; i++)
 797                 fimc->clock[i] = ERR_PTR(-EINVAL);
 798
 799         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 800                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
 801                 if (IS_ERR(fimc->clock[i])) {
 802                         ret = PTR_ERR(fimc->clock[i]);
 803                         goto err;
 804                 }
 805                 ret = clk_prepare(fimc->clock[i]);
 806                 if (ret < 0) {
 807                         clk_put(fimc->clock[i]);
 808                         fimc->clock[i] = ERR_PTR(-EINVAL);
 809                         goto err;
 810                 }
 811         }
 812         return 0;
 813 err:
 814         fimc_clk_put(fimc);
 815         dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
 816                 fimc_clocks[i]);
 817         return -ENXIO;
 818 }
 819
 820 #ifdef CONFIG_PM
 821 static int fimc_m2m_suspend(struct fimc_dev *fimc)
 822 {
 823         unsigned long flags;
 824         int timeout;
 825
 826         spin_lock_irqsave(&fimc->slock, flags);
 827         if (!fimc_m2m_pending(fimc)) {
 828                 spin_unlock_irqrestore(&fimc->slock, flags);
 829                 return 0;
 830         }
 831         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
 832         set_bit(ST_M2M_SUSPENDING, &fimc->state);
 833         spin_unlock_irqrestore(&fimc->slock, flags);
 834
 835         timeout = wait_event_timeout(fimc->irq_queue,
 836                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
 837                              FIMC_SHUTDOWN_TIMEOUT);
 838
 839         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
 840         return timeout == 0 ? -EAGAIN : 0;
 841 }
 842
 843 static int fimc_m2m_resume(struct fimc_dev *fimc)
 844 {
 845         struct fimc_ctx *ctx;
 846         unsigned long flags;
 847
 848         spin_lock_irqsave(&fimc->slock, flags);
 849         /* Clear for full H/W setup in first run after resume */
 850         ctx = fimc->m2m.ctx;
 851         fimc->m2m.ctx = NULL;
 852         spin_unlock_irqrestore(&fimc->slock, flags);
 853
 854         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
 855                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 856
 857         return 0;
 858 }
 859 #endif /* CONFIG_PM */
 860
 861 static const struct of_device_id fimc_of_match[];
 862
 863 static int fimc_parse_dt(struct fimc_dev *fimc, u32 *clk_freq)
 864 {
 865         struct device *dev = &fimc->pdev->dev;
 866         struct device_node *node = dev->of_node;
 867         const struct of_device_id *of_id;
 868         struct fimc_variant *v;
 869         struct fimc_pix_limit *lim;
 870         u32 args[FIMC_PIX_LIMITS_MAX];
 871         int ret;
 872
 873         if (of_property_read_bool(node, "samsung,lcd-wb"))
 874                 return -ENODEV;
 875
 876         v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL);
 877         if (!v)
 878                 return -ENOMEM;
 879
 880         of_id = of_match_node(fimc_of_match, node);
 881         if (!of_id)
 882                 return -EINVAL;
 883         fimc->drv_data = of_id->data;
 884         ret = of_property_read_u32_array(node, "samsung,pix-limits",
 885                                          args, FIMC_PIX_LIMITS_MAX);
 886         if (ret < 0)
 887                 return ret;
 888
 889         lim = (struct fimc_pix_limit *)&v[1];
 890
 891         lim->scaler_en_w = args[0];
 892         lim->scaler_dis_w = args[1];
 893         lim->out_rot_en_w = args[2];
 894         lim->out_rot_dis_w = args[3];
 895         v->pix_limit = lim;
 896
 897         ret = of_property_read_u32_array(node, "samsung,min-pix-sizes",
 898                                                                 args, 2);
 899         v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0];
 900         v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1];
 901         ret = of_property_read_u32_array(node, "samsung,min-pix-alignment",
 902                                                                 args, 2);
 903         v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0];
 904         v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1];
 905
 906         ret = of_property_read_u32(node, "samsung,rotators", &args[1]);
 907         v->has_inp_rot = ret ? 1 : args[1] & 0x01;
 908         v->has_out_rot = ret ? 1 : args[1] & 0x10;
 909         v->has_mainscaler_ext = of_property_read_bool(node,
 910                                         "samsung,mainscaler-ext");
 911
 912         v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb");
 913         v->has_cam_if = of_property_read_bool(node, "samsung,cam-if");
 914         of_property_read_u32(node, "clock-frequency", clk_freq);
 915         fimc->id = of_alias_get_id(node, "fimc");
 916
 917         fimc->variant = v;
 918         return 0;
 919 }
 920
 921 static int fimc_probe(struct platform_device *pdev)
 922 {
 923         struct device *dev = &pdev->dev;
 924         u32 lclk_freq = 0;
 925         struct fimc_dev *fimc;
 926         int ret = 0;
 927         int irq;
 928
 929         fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
 930         if (!fimc)
 931                 return -ENOMEM;
 932
 933         fimc->pdev = pdev;
 934
 935         if (dev->of_node) {
 936                 ret = fimc_parse_dt(fimc, &lclk_freq);
 937                 if (ret < 0)
 938                         return ret;
 939         } else {
 940                 fimc->drv_data = fimc_get_drvdata(pdev);
 941                 fimc->id = pdev->id;
 942         }
 943         if (!fimc->drv_data || fimc->id >= fimc->drv_data->num_entities ||
 944             fimc->id < 0) {
 945                 dev_err(dev, "Invalid driver data or device id (%d)\n",
 946                         fimc->id);
 947                 return -EINVAL;
 948         }
 949         if (!dev->of_node)
 950                 fimc->variant = fimc->drv_data->variant[fimc->id];
 951
 952         init_waitqueue_head(&fimc->irq_queue);
 953         spin_lock_init(&fimc->slock);
 954         mutex_init(&fimc->lock);
 955
 956         if (fimc->variant->has_isp_wb) {
 957                 fimc->sysreg = fimc_get_sysreg_regmap(dev->of_node);
 958                 if (IS_ERR(fimc->sysreg))
 959                         return PTR_ERR(fimc->sysreg);
 960         }
 961
 962         fimc->regs = devm_platform_ioremap_resource(pdev, 0);
 963         if (IS_ERR(fimc->regs))
 964                 return PTR_ERR(fimc->regs);
 965
 966         irq = platform_get_irq(pdev, 0);
 967         if (irq < 0)
 968                 return irq;
 969
 970         ret = fimc_clk_get(fimc);
 971         if (ret)
 972                 return ret;
 973
 974         if (lclk_freq == 0)
 975                 lclk_freq = fimc->drv_data->lclk_frequency;
 976
 977         ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq);
 978         if (ret < 0)
 979                 return ret;
 980
 981         ret = clk_enable(fimc->clock[CLK_BUS]);
 982         if (ret < 0)
 983                 return ret;
 984
 985         ret = devm_request_irq(dev, irq, fimc_irq_handler,
 986                                0, dev_name(dev), fimc);
 987         if (ret < 0) {
 988                 dev_err(dev, "failed to install irq (%d)\n", ret);
 989                 goto err_sclk;
 990         }
 991
 992         ret = fimc_initialize_capture_subdev(fimc);
 993         if (ret < 0)
 994                 goto err_sclk;
 995
 996         platform_set_drvdata(pdev, fimc);
 997         pm_runtime_enable(dev);
 998
 999         if (!pm_runtime_enabled(dev)) {
1000                 ret = clk_enable(fimc->clock[CLK_GATE]);
1001                 if (ret < 0)
1002                         goto err_sd;
1003         }
1004
1005         vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1006
1007         dev_dbg(dev, "FIMC.%d registered successfully\n", fimc->id);
1008         return 0;
1009
1010 err_sd:
1011         fimc_unregister_capture_subdev(fimc);
1012 err_sclk:
1013         clk_disable(fimc->clock[CLK_BUS]);
1014         fimc_clk_put(fimc);
1015         return ret;
1016 }
1017
1018 #ifdef CONFIG_PM
1019 static int fimc_runtime_resume(struct device *dev)
1020 {
1021         struct fimc_dev *fimc = dev_get_drvdata(dev);
1022
1023         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1024
1025         /* Enable clocks and perform basic initialization */
1026         clk_enable(fimc->clock[CLK_GATE]);
1027         fimc_hw_reset(fimc);
1028
1029         /* Resume the capture or mem-to-mem device */
1030         if (fimc_capture_busy(fimc))
1031                 return fimc_capture_resume(fimc);
1032
1033         return fimc_m2m_resume(fimc);
1034 }
1035
1036 static int fimc_runtime_suspend(struct device *dev)
1037 {
1038         struct fimc_dev *fimc = dev_get_drvdata(dev);
1039         int ret = 0;
1040
1041         if (fimc_capture_busy(fimc))
1042                 ret = fimc_capture_suspend(fimc);
1043         else
1044                 ret = fimc_m2m_suspend(fimc);
1045         if (!ret)
1046                 clk_disable(fimc->clock[CLK_GATE]);
1047
1048         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1049         return ret;
1050 }
1051 #endif
1052
1053 #ifdef CONFIG_PM_SLEEP
1054 static int fimc_resume(struct device *dev)
1055 {
1056         struct fimc_dev *fimc = dev_get_drvdata(dev);
1057         unsigned long flags;
1058
1059         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1060
1061         /* Do not resume if the device was idle before system suspend */
1062         spin_lock_irqsave(&fimc->slock, flags);
1063         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1064             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1065                 spin_unlock_irqrestore(&fimc->slock, flags);
1066                 return 0;
1067         }
1068         fimc_hw_reset(fimc);
1069         spin_unlock_irqrestore(&fimc->slock, flags);
1070
1071         if (fimc_capture_busy(fimc))
1072                 return fimc_capture_resume(fimc);
1073
1074         return fimc_m2m_resume(fimc);
1075 }
1076
1077 static int fimc_suspend(struct device *dev)
1078 {
1079         struct fimc_dev *fimc = dev_get_drvdata(dev);
1080
1081         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1082
1083         if (test_and_set_bit(ST_LPM, &fimc->state))
1084                 return 0;
1085         if (fimc_capture_busy(fimc))
1086                 return fimc_capture_suspend(fimc);
1087
1088         return fimc_m2m_suspend(fimc);
1089 }
1090 #endif /* CONFIG_PM_SLEEP */
1091
1092 static void fimc_remove(struct platform_device *pdev)
1093 {
1094         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1095
1096         pm_runtime_disable(&pdev->dev);
1097         if (!pm_runtime_status_suspended(&pdev->dev))
1098                 clk_disable(fimc->clock[CLK_GATE]);
1099         pm_runtime_set_suspended(&pdev->dev);
1100
1101         fimc_unregister_capture_subdev(fimc);
1102         vb2_dma_contig_clear_max_seg_size(&pdev->dev);
1103
1104         clk_disable(fimc->clock[CLK_BUS]);
1105         fimc_clk_put(fimc);
1106
1107         dev_info(&pdev->dev, "driver unloaded\n");
1108 }
1109
1110 /* S5PV210, S5PC110 */
1111 static const struct fimc_drvdata fimc_drvdata_s5pv210 = {
1112         .num_entities   = 3,
1113         .lclk_frequency = 166000000UL,
1114         .out_buf_count  = 4,
1115         .dma_pix_hoff   = 1,
1116 };
1117
1118 /* EXYNOS4210, S5PV310, S5PC210 */
1119 static const struct fimc_drvdata fimc_drvdata_exynos4210 = {
1120         .num_entities   = 4,
1121         .lclk_frequency = 166000000UL,
1122         .dma_pix_hoff   = 1,
1123         .cistatus2      = 1,
1124         .alpha_color    = 1,
1125         .out_buf_count  = 32,
1126 };
1127
1128 /* EXYNOS4212, EXYNOS4412 */
1129 static const struct fimc_drvdata fimc_drvdata_exynos4x12 = {
1130         .num_entities   = 4,
1131         .lclk_frequency = 166000000UL,
1132         .dma_pix_hoff   = 1,
1133         .cistatus2      = 1,
1134         .alpha_color    = 1,
1135         .out_buf_count  = 32,
1136 };
1137
1138 static const struct of_device_id fimc_of_match[] = {
1139         {
1140                 .compatible = "samsung,s5pv210-fimc",
1141                 .data = &fimc_drvdata_s5pv210,
1142         }, {
1143                 .compatible = "samsung,exynos4210-fimc",
1144                 .data = &fimc_drvdata_exynos4210,
1145         }, {
1146                 .compatible = "samsung,exynos4212-fimc",
1147                 .data = &fimc_drvdata_exynos4x12,
1148         },
1149         { /* sentinel */ },
1150 };
1151
1152 static const struct dev_pm_ops fimc_pm_ops = {
1153         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1154         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1155 };
1156
1157 static struct platform_driver fimc_driver = {
1158         .probe          = fimc_probe,
1159         .remove_new     = fimc_remove,
1160         .driver = {
1161                 .of_match_table = fimc_of_match,
1162                 .name           = FIMC_DRIVER_NAME,
1163                 .pm             = &fimc_pm_ops,
1164         }
1165 };
1166
1167 int __init fimc_register_driver(void)
1168 {
1169         return platform_driver_register(&fimc_driver);
1170 }
1171
1172 void fimc_unregister_driver(void)
1173 {
1174         platform_driver_unregister(&fimc_driver);
1175 }