2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include "s5p_mfc_cmd.h"
19 #include "s5p_mfc_common.h"
20 #include "s5p_mfc_debug.h"
21 #include "s5p_mfc_intr.h"
22 #include "s5p_mfc_opr.h"
23 #include "s5p_mfc_pm.h"
24 #include "s5p_mfc_ctrl.h"
26 /* Allocate memory for firmware */
27 int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
29 struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf;
32 fw_buf->size = dev->variant->buf_size->fw;
35 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
39 err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);
41 mfc_err("Allocating bitprocessor buffer failed\n");
49 int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
51 struct firmware *fw_blob;
54 /* Firmare has to be present as a separate file or compiled
61 for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
62 if (!dev->variant->fw_name[i])
64 err = reject_firmware((const struct firmware **)&fw_blob,
65 dev->variant->fw_name[i], dev->v4l2_dev.dev);
67 dev->fw_ver = (enum s5p_mfc_fw_ver) i;
73 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
76 if (fw_blob->size > dev->fw_buf.size) {
77 mfc_err("MFC firmware is too big to be loaded\n");
78 release_firmware(fw_blob);
81 if (!dev->fw_buf.virt) {
82 mfc_err("MFC firmware is not allocated\n");
83 release_firmware(fw_blob);
86 memcpy(dev->fw_buf.virt, fw_blob->data, fw_blob->size);
88 dev->fw_get_done = true;
89 release_firmware(fw_blob);
94 /* Release firmware memory */
95 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
97 /* Before calling this function one has to make sure
98 * that MFC is no longer processing */
99 s5p_mfc_release_priv_buf(dev, &dev->fw_buf);
100 dev->fw_get_done = false;
104 static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
107 unsigned long timeout;
110 mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
111 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
112 /* Check bus status */
114 if (time_after(jiffies, timeout)) {
115 mfc_err("Timeout while resetting MFC.\n");
118 status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
119 } while ((status & 0x2) == 0);
123 /* Reset the device */
124 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
126 unsigned int mc_status;
127 unsigned long timeout;
132 if (IS_MFCV6_PLUS(dev)) {
133 /* Zero Initialization of MFC registers */
134 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
135 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
136 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
138 for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
139 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
141 /* check bus reset control before reset */
143 if (s5p_mfc_bus_reset(dev))
146 * set RISC_ON to 0 during power_on & wake_up.
147 * V6 needs RISC_ON set to 0 during reset also.
149 if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev)))
150 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
152 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
153 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
157 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
158 /* All reset except for MC */
159 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
162 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
163 /* Check MC status */
165 if (time_after(jiffies, timeout)) {
166 mfc_err("Timeout while resetting MFC\n");
170 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
172 } while (mc_status & 0x3);
174 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
175 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
182 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
184 if (IS_MFCV6_PLUS(dev)) {
185 mfc_write(dev, dev->dma_base[BANK_L_CTX],
186 S5P_FIMV_RISC_BASE_ADDRESS_V6);
187 mfc_debug(2, "Base Address : %pad\n",
188 &dev->dma_base[BANK_L_CTX]);
190 mfc_write(dev, dev->dma_base[BANK_L_CTX],
191 S5P_FIMV_MC_DRAMBASE_ADR_A);
192 mfc_write(dev, dev->dma_base[BANK_R_CTX],
193 S5P_FIMV_MC_DRAMBASE_ADR_B);
194 mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
195 &dev->dma_base[BANK_L_CTX],
196 &dev->dma_base[BANK_R_CTX]);
200 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
202 if (IS_MFCV6_PLUS(dev)) {
203 /* Zero initialization should be done before RESET.
204 * Nothing to do here. */
206 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
207 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
208 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
209 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
213 /* Initialize hardware */
214 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
220 if (!dev->fw_buf.virt) {
221 mfc_err("Firmware memory is not allocated.\n");
226 mfc_debug(2, "MFC reset..\n");
229 ret = s5p_mfc_reset(dev);
231 mfc_err("Failed to reset MFC - timeout\n");
234 mfc_debug(2, "Done MFC reset..\n");
235 /* 1. Set DRAM base Addr */
236 s5p_mfc_init_memctrl(dev);
237 /* 2. Initialize registers of channel I/F */
238 s5p_mfc_clear_cmds(dev);
239 /* 3. Release reset signal to the RISC */
240 s5p_mfc_clean_dev_int_flags(dev);
241 if (IS_MFCV6_PLUS(dev)) {
243 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
246 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
247 mfc_debug(2, "Will now wait for completion of firmware transfer\n");
248 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
249 mfc_err("Failed to load firmware\n");
254 s5p_mfc_clean_dev_int_flags(dev);
255 /* 4. Initialize firmware */
256 ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
258 mfc_err("Failed to send command to MFC - timeout\n");
263 mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
264 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
265 mfc_err("Failed to init hardware\n");
271 if (dev->int_err != 0 || dev->int_type !=
272 S5P_MFC_R2H_CMD_SYS_INIT_RET) {
274 mfc_err("Failed to init firmware - error: %d int: %d\n",
275 dev->int_err, dev->int_type);
280 if (IS_MFCV6_PLUS(dev))
281 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
283 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
285 mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
286 (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
293 /* Deinitialize hardware */
294 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
299 s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);
304 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
310 s5p_mfc_clean_dev_int_flags(dev);
311 ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
313 mfc_err("Failed to send command to MFC - timeout\n");
316 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
317 mfc_err("Failed to sleep\n");
322 if (dev->int_err != 0 || dev->int_type !=
323 S5P_MFC_R2H_CMD_SLEEP_RET) {
325 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
333 static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
337 /* Release reset signal to the RISC */
339 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
341 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
342 mfc_err("Failed to reset MFCV8\n");
345 mfc_debug(2, "Write command to wakeup MFCV8\n");
346 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
348 mfc_err("Failed to send command to MFCV8 - timeout\n");
352 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
353 mfc_err("Failed to wakeup MFC\n");
359 static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
363 /* Send MFC wakeup command */
364 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
366 mfc_err("Failed to send command to MFC - timeout\n");
370 /* Release reset signal to the RISC */
371 if (IS_MFCV6_PLUS(dev)) {
373 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
375 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
378 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
379 mfc_err("Failed to wakeup MFC\n");
385 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
391 mfc_debug(2, "MFC reset..\n");
394 ret = s5p_mfc_reset(dev);
396 mfc_err("Failed to reset MFC - timeout\n");
400 mfc_debug(2, "Done MFC reset..\n");
401 /* 1. Set DRAM base Addr */
402 s5p_mfc_init_memctrl(dev);
403 /* 2. Initialize registers of channel I/F */
404 s5p_mfc_clear_cmds(dev);
405 s5p_mfc_clean_dev_int_flags(dev);
406 /* 3. Send MFC wakeup command and wait for completion*/
408 ret = s5p_mfc_v8_wait_wakeup(dev);
410 ret = s5p_mfc_wait_wakeup(dev);
417 if (dev->int_err != 0 || dev->int_type !=
418 S5P_MFC_R2H_CMD_WAKEUP_RET) {
420 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
428 int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
432 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
434 mfc_err("Failed allocating instance buffer\n");
438 if (ctx->type == MFCINST_DECODER) {
439 ret = s5p_mfc_hw_call(dev->mfc_ops,
440 alloc_dec_temp_buffers, ctx);
442 mfc_err("Failed allocating temporary buffers\n");
443 goto err_free_inst_buf;
447 set_work_bit_irqsave(ctx);
448 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
449 if (s5p_mfc_wait_for_done_ctx(ctx,
450 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
451 /* Error or timeout */
452 mfc_err("Error getting instance from hardware\n");
454 goto err_free_desc_buf;
457 mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
461 if (ctx->type == MFCINST_DECODER)
462 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
464 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
469 void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
471 ctx->state = MFCINST_RETURN_INST;
472 set_work_bit_irqsave(ctx);
473 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
474 /* Wait until instance is returned or timeout occurred */
475 if (s5p_mfc_wait_for_done_ctx(ctx,
476 S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
477 mfc_err("Err returning instance\n");
480 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
481 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
482 if (ctx->type == MFCINST_DECODER)
483 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
485 ctx->inst_no = MFC_NO_INSTANCE_SET;
486 ctx->state = MFCINST_FREE;