2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
25 #include <linux/of_device.h>
26 #include <linux/of_reserved_mem.h>
27 #include <media/videobuf2-v4l2.h>
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_ctrl.h"
30 #include "s5p_mfc_debug.h"
31 #include "s5p_mfc_dec.h"
32 #include "s5p_mfc_enc.h"
33 #include "s5p_mfc_intr.h"
34 #include "s5p_mfc_iommu.h"
35 #include "s5p_mfc_opr.h"
36 #include "s5p_mfc_cmd.h"
37 #include "s5p_mfc_pm.h"
39 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
40 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
43 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
46 static char *mfc_mem_size;
47 module_param_named(mem, mfc_mem_size, charp, 0644);
48 MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
50 /* Helper functions for interrupt processing */
52 /* Remove from hw execution round robin */
53 void clear_work_bit(struct s5p_mfc_ctx *ctx)
55 struct s5p_mfc_dev *dev = ctx->dev;
57 spin_lock(&dev->condlock);
58 __clear_bit(ctx->num, &dev->ctx_work_bits);
59 spin_unlock(&dev->condlock);
62 /* Add to hw execution round robin */
63 void set_work_bit(struct s5p_mfc_ctx *ctx)
65 struct s5p_mfc_dev *dev = ctx->dev;
67 spin_lock(&dev->condlock);
68 __set_bit(ctx->num, &dev->ctx_work_bits);
69 spin_unlock(&dev->condlock);
72 /* Remove from hw execution round robin */
73 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
75 struct s5p_mfc_dev *dev = ctx->dev;
78 spin_lock_irqsave(&dev->condlock, flags);
79 __clear_bit(ctx->num, &dev->ctx_work_bits);
80 spin_unlock_irqrestore(&dev->condlock, flags);
83 /* Add to hw execution round robin */
84 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
86 struct s5p_mfc_dev *dev = ctx->dev;
89 spin_lock_irqsave(&dev->condlock, flags);
90 __set_bit(ctx->num, &dev->ctx_work_bits);
91 spin_unlock_irqrestore(&dev->condlock, flags);
94 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
99 spin_lock_irqsave(&dev->condlock, flags);
102 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
103 if (ctx == dev->curr_ctx) {
104 if (!test_bit(ctx, &dev->ctx_work_bits))
108 } while (!test_bit(ctx, &dev->ctx_work_bits));
109 spin_unlock_irqrestore(&dev->condlock, flags);
114 /* Wake up context wait_queue */
115 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
119 ctx->int_type = reason;
121 wake_up(&ctx->queue);
124 /* Wake up device wait_queue */
125 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
129 dev->int_type = reason;
131 wake_up(&dev->queue);
134 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
136 struct s5p_mfc_buf *b;
139 while (!list_empty(lh)) {
140 b = list_entry(lh->next, struct s5p_mfc_buf, list);
141 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
142 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
143 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
148 static void s5p_mfc_watchdog(unsigned long arg)
150 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
152 if (test_bit(0, &dev->hw_lock))
153 atomic_inc(&dev->watchdog_cnt);
154 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
155 /* This means that hw is busy and no interrupts were
156 * generated by hw for the Nth time of running this
157 * watchdog timer. This usually means a serious hw
158 * error. Now it is time to kill all instances and
160 mfc_err("Time out during waiting for HW\n");
161 schedule_work(&dev->watchdog_work);
163 dev->watchdog_timer.expires = jiffies +
164 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
165 add_timer(&dev->watchdog_timer);
168 static void s5p_mfc_watchdog_worker(struct work_struct *work)
170 struct s5p_mfc_dev *dev;
171 struct s5p_mfc_ctx *ctx;
176 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
178 mfc_err("Driver timeout error handling\n");
179 /* Lock the mutex that protects open and release.
180 * This is necessary as they may load and unload firmware. */
181 mutex_locked = mutex_trylock(&dev->mfc_mutex);
183 mfc_err("Error: some instance may be closing/opening\n");
184 spin_lock_irqsave(&dev->irqlock, flags);
188 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
192 ctx->state = MFCINST_ERROR;
193 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
194 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
196 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
198 clear_bit(0, &dev->hw_lock);
199 spin_unlock_irqrestore(&dev->irqlock, flags);
202 s5p_mfc_deinit_hw(dev);
204 /* Double check if there is at least one instance running.
205 * If no instance is in memory than no firmware should be present */
206 if (dev->num_inst > 0) {
207 ret = s5p_mfc_load_firmware(dev);
209 mfc_err("Failed to reload FW\n");
213 ret = s5p_mfc_init_hw(dev);
216 mfc_err("Failed to reinit FW\n");
220 mutex_unlock(&dev->mfc_mutex);
223 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
225 struct s5p_mfc_buf *dst_buf;
226 struct s5p_mfc_dev *dev = ctx->dev;
228 ctx->state = MFCINST_FINISHED;
230 while (!list_empty(&ctx->dst_queue)) {
231 dst_buf = list_entry(ctx->dst_queue.next,
232 struct s5p_mfc_buf, list);
233 mfc_debug(2, "Cleaning up buffer: %d\n",
234 dst_buf->b->vb2_buf.index);
235 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
236 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
237 list_del(&dst_buf->list);
238 dst_buf->flags |= MFC_BUF_FLAG_EOS;
239 ctx->dst_queue_cnt--;
240 dst_buf->b->sequence = (ctx->sequence++);
242 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
243 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
244 dst_buf->b->field = V4L2_FIELD_NONE;
246 dst_buf->b->field = V4L2_FIELD_INTERLACED;
247 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
249 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
250 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
254 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
256 struct s5p_mfc_dev *dev = ctx->dev;
257 struct s5p_mfc_buf *dst_buf, *src_buf;
259 unsigned int frame_type;
261 /* Make sure we actually have a new frame before continuing. */
262 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
263 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
265 dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
267 /* Copy timestamp / timecode from decoded src to dst and set
268 appropriate flags. */
269 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
270 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
271 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
273 if (addr == dec_y_addr) {
274 dst_buf->b->timecode = src_buf->b->timecode;
275 dst_buf->b->vb2_buf.timestamp =
276 src_buf->b->vb2_buf.timestamp;
278 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
281 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
282 switch (frame_type) {
283 case S5P_FIMV_DECODE_FRAME_I_FRAME:
285 V4L2_BUF_FLAG_KEYFRAME;
287 case S5P_FIMV_DECODE_FRAME_P_FRAME:
289 V4L2_BUF_FLAG_PFRAME;
291 case S5P_FIMV_DECODE_FRAME_B_FRAME:
293 V4L2_BUF_FLAG_BFRAME;
296 /* Don't know how to handle
297 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
298 mfc_debug(2, "Unexpected frame type: %d\n",
306 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
308 struct s5p_mfc_dev *dev = ctx->dev;
309 struct s5p_mfc_buf *dst_buf;
311 unsigned int frame_type;
313 dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
314 if (IS_MFCV6_PLUS(dev))
315 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
316 get_disp_frame_type, ctx);
318 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
319 get_dec_frame_type, dev);
321 /* If frame is same as previous then skip and do not dequeue */
322 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
323 if (!ctx->after_packed_pb)
325 ctx->after_packed_pb = 0;
329 /* The MFC returns address of the buffer, now we have to
330 * check which videobuf does it correspond to */
331 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
332 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
334 /* Check if this is the buffer we're looking for */
335 if (addr == dspl_y_addr) {
336 list_del(&dst_buf->list);
337 ctx->dst_queue_cnt--;
338 dst_buf->b->sequence = ctx->sequence;
339 if (s5p_mfc_hw_call(dev->mfc_ops,
340 get_pic_type_top, ctx) ==
341 s5p_mfc_hw_call(dev->mfc_ops,
342 get_pic_type_bot, ctx))
343 dst_buf->b->field = V4L2_FIELD_NONE;
346 V4L2_FIELD_INTERLACED;
347 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
349 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
351 clear_bit(dst_buf->b->vb2_buf.index,
354 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
355 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
362 /* Handle frame decoding interrupt */
363 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
364 unsigned int reason, unsigned int err)
366 struct s5p_mfc_dev *dev = ctx->dev;
367 unsigned int dst_frame_status;
368 unsigned int dec_frame_status;
369 struct s5p_mfc_buf *src_buf;
370 unsigned int res_change;
372 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
373 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
374 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
375 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
376 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
377 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
378 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
379 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
380 if (ctx->state == MFCINST_RES_CHANGE_INIT)
381 ctx->state = MFCINST_RES_CHANGE_FLUSH;
382 if (res_change == S5P_FIMV_RES_INCREASE ||
383 res_change == S5P_FIMV_RES_DECREASE) {
384 ctx->state = MFCINST_RES_CHANGE_INIT;
385 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
386 wake_up_ctx(ctx, reason, err);
387 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
389 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
392 if (ctx->dpb_flush_flag)
393 ctx->dpb_flush_flag = 0;
395 /* All frames remaining in the buffer have been extracted */
396 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
397 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
398 static const struct v4l2_event ev_src_ch = {
399 .type = V4L2_EVENT_SOURCE_CHANGE,
400 .u.src_change.changes =
401 V4L2_EVENT_SRC_CH_RESOLUTION,
404 s5p_mfc_handle_frame_all_extracted(ctx);
405 ctx->state = MFCINST_RES_CHANGE_END;
406 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
408 goto leave_handle_frame;
410 s5p_mfc_handle_frame_all_extracted(ctx);
414 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
415 s5p_mfc_handle_frame_copy_time(ctx);
417 /* A frame has been decoded and is in the buffer */
418 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
419 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
420 s5p_mfc_handle_frame_new(ctx, err);
422 mfc_debug(2, "No frame decode\n");
424 /* Mark source buffer as complete */
425 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
426 && !list_empty(&ctx->src_queue)) {
427 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
429 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
430 get_consumed_stream, dev);
431 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
432 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
433 ctx->consumed_stream + STUFF_BYTE <
434 src_buf->b->vb2_buf.planes[0].bytesused) {
435 /* Run MFC again on the same buffer */
436 mfc_debug(2, "Running again the same buffer\n");
437 ctx->after_packed_pb = 1;
439 mfc_debug(2, "MFC needs next buffer\n");
440 ctx->consumed_stream = 0;
441 if (src_buf->flags & MFC_BUF_FLAG_EOS)
442 ctx->state = MFCINST_FINISHING;
443 list_del(&src_buf->list);
444 ctx->src_queue_cnt--;
445 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
446 vb2_buffer_done(&src_buf->b->vb2_buf,
447 VB2_BUF_STATE_ERROR);
449 vb2_buffer_done(&src_buf->b->vb2_buf,
454 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
455 || ctx->dst_queue_cnt < ctx->pb_count)
457 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
458 wake_up_ctx(ctx, reason, err);
459 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
461 /* if suspending, wake up device and do not try_run again*/
462 if (test_bit(0, &dev->enter_suspend))
463 wake_up_dev(dev, reason, err);
465 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
468 /* Error handling for interrupt */
469 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
470 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
472 mfc_err("Interrupt Error: %08x\n", err);
475 /* Error recovery is dependent on the state of context */
476 switch (ctx->state) {
477 case MFCINST_RES_CHANGE_INIT:
478 case MFCINST_RES_CHANGE_FLUSH:
479 case MFCINST_RES_CHANGE_END:
480 case MFCINST_FINISHING:
481 case MFCINST_FINISHED:
482 case MFCINST_RUNNING:
483 /* It is highly probable that an error occurred
484 * while decoding a frame */
486 ctx->state = MFCINST_ERROR;
487 /* Mark all dst buffers as having an error */
488 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
489 /* Mark all src buffers as having an error */
490 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
491 wake_up_ctx(ctx, reason, err);
495 ctx->state = MFCINST_ERROR;
496 wake_up_ctx(ctx, reason, err);
500 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
501 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
503 wake_up_dev(dev, reason, err);
506 /* Header parsing interrupt handling */
507 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
508 unsigned int reason, unsigned int err)
510 struct s5p_mfc_dev *dev;
515 if (ctx->c_ops->post_seq_start) {
516 if (ctx->c_ops->post_seq_start(ctx))
517 mfc_err("post_seq_start() failed\n");
519 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
521 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
524 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
526 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
528 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
530 if (ctx->img_width == 0 || ctx->img_height == 0)
531 ctx->state = MFCINST_ERROR;
533 ctx->state = MFCINST_HEAD_PARSED;
535 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
536 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
537 !list_empty(&ctx->src_queue)) {
538 struct s5p_mfc_buf *src_buf;
539 src_buf = list_entry(ctx->src_queue.next,
540 struct s5p_mfc_buf, list);
541 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
543 src_buf->b->vb2_buf.planes[0].bytesused)
544 ctx->head_processed = 0;
546 ctx->head_processed = 1;
548 ctx->head_processed = 1;
551 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
553 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
555 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
556 wake_up_ctx(ctx, reason, err);
559 /* Header parsing interrupt handling */
560 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
561 unsigned int reason, unsigned int err)
563 struct s5p_mfc_buf *src_buf;
564 struct s5p_mfc_dev *dev;
569 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
570 ctx->int_type = reason;
575 ctx->state = MFCINST_RUNNING;
576 if (!ctx->dpb_flush_flag && ctx->head_processed) {
577 if (!list_empty(&ctx->src_queue)) {
578 src_buf = list_entry(ctx->src_queue.next,
579 struct s5p_mfc_buf, list);
580 list_del(&src_buf->list);
581 ctx->src_queue_cnt--;
582 vb2_buffer_done(&src_buf->b->vb2_buf,
586 ctx->dpb_flush_flag = 0;
588 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
592 wake_up(&ctx->queue);
593 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
595 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
599 wake_up(&ctx->queue);
603 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
605 struct s5p_mfc_dev *dev = ctx->dev;
606 struct s5p_mfc_buf *mb_entry;
608 mfc_debug(2, "Stream completed\n");
610 ctx->state = MFCINST_FINISHED;
612 if (!list_empty(&ctx->dst_queue)) {
613 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
615 list_del(&mb_entry->list);
616 ctx->dst_queue_cnt--;
617 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
618 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
623 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
626 wake_up(&ctx->queue);
627 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
630 /* Interrupt processing */
631 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
633 struct s5p_mfc_dev *dev = priv;
634 struct s5p_mfc_ctx *ctx;
639 /* Reset the timeout watchdog */
640 atomic_set(&dev->watchdog_cnt, 0);
641 spin_lock(&dev->irqlock);
642 ctx = dev->ctx[dev->curr_ctx];
643 /* Get the reason of interrupt and the error code */
644 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
645 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
646 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
648 case S5P_MFC_R2H_CMD_ERR_RET:
649 /* An error has occurred */
650 if (ctx->state == MFCINST_RUNNING &&
651 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
653 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
654 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
655 err == S5P_FIMV_ERR_TIMEOUT))
656 s5p_mfc_handle_frame(ctx, reason, err);
658 s5p_mfc_handle_error(dev, ctx, reason, err);
659 clear_bit(0, &dev->enter_suspend);
662 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
663 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
664 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
665 if (ctx->c_ops->post_frame_start) {
666 if (ctx->c_ops->post_frame_start(ctx))
667 mfc_err("post_frame_start() failed\n");
669 if (ctx->state == MFCINST_FINISHING &&
670 list_empty(&ctx->ref_queue)) {
671 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
672 s5p_mfc_handle_stream_complete(ctx);
675 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
676 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
678 wake_up_ctx(ctx, reason, err);
679 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
681 s5p_mfc_handle_frame(ctx, reason, err);
685 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
686 s5p_mfc_handle_seq_done(ctx, reason, err);
689 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
690 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
691 ctx->state = MFCINST_GOT_INST;
694 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
695 ctx->inst_no = MFC_NO_INSTANCE_SET;
696 ctx->state = MFCINST_FREE;
699 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
700 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
701 case S5P_MFC_R2H_CMD_SLEEP_RET:
702 case S5P_MFC_R2H_CMD_WAKEUP_RET:
705 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
706 clear_bit(0, &dev->hw_lock);
707 clear_bit(0, &dev->enter_suspend);
708 wake_up_dev(dev, reason, err);
711 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
712 s5p_mfc_handle_init_buffers(ctx, reason, err);
715 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
716 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
717 ctx->int_type = reason;
719 s5p_mfc_handle_stream_complete(ctx);
722 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
723 ctx->state = MFCINST_RUNNING;
727 mfc_debug(2, "Unknown int reason\n");
728 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
730 spin_unlock(&dev->irqlock);
734 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
735 ctx->int_type = reason;
738 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
739 mfc_err("Failed to unlock hw\n");
743 wake_up(&ctx->queue);
745 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
746 spin_unlock(&dev->irqlock);
747 mfc_debug(2, "Exit via irq_cleanup_hw\n");
751 /* Open an MFC node */
752 static int s5p_mfc_open(struct file *file)
754 struct video_device *vdev = video_devdata(file);
755 struct s5p_mfc_dev *dev = video_drvdata(file);
756 struct s5p_mfc_ctx *ctx = NULL;
761 if (mutex_lock_interruptible(&dev->mfc_mutex))
763 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
764 /* Allocate memory for context */
765 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
770 init_waitqueue_head(&ctx->queue);
771 v4l2_fh_init(&ctx->fh, vdev);
772 file->private_data = &ctx->fh;
773 v4l2_fh_add(&ctx->fh);
775 INIT_LIST_HEAD(&ctx->src_queue);
776 INIT_LIST_HEAD(&ctx->dst_queue);
777 ctx->src_queue_cnt = 0;
778 ctx->dst_queue_cnt = 0;
779 /* Get context number */
781 while (dev->ctx[ctx->num]) {
783 if (ctx->num >= MFC_NUM_CONTEXTS) {
784 mfc_debug(2, "Too many open contexts\n");
789 /* Mark context as idle */
790 clear_work_bit_irqsave(ctx);
791 dev->ctx[ctx->num] = ctx;
792 if (vdev == dev->vfd_dec) {
793 ctx->type = MFCINST_DECODER;
794 ctx->c_ops = get_dec_codec_ops();
795 s5p_mfc_dec_init(ctx);
796 /* Setup ctrl handler */
797 ret = s5p_mfc_dec_ctrls_setup(ctx);
799 mfc_err("Failed to setup mfc controls\n");
800 goto err_ctrls_setup;
802 } else if (vdev == dev->vfd_enc) {
803 ctx->type = MFCINST_ENCODER;
804 ctx->c_ops = get_enc_codec_ops();
805 /* only for encoder */
806 INIT_LIST_HEAD(&ctx->ref_queue);
807 ctx->ref_queue_cnt = 0;
808 s5p_mfc_enc_init(ctx);
809 /* Setup ctrl handler */
810 ret = s5p_mfc_enc_ctrls_setup(ctx);
812 mfc_err("Failed to setup mfc controls\n");
813 goto err_ctrls_setup;
819 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
820 ctx->inst_no = MFC_NO_INSTANCE_SET;
821 /* Load firmware if this is the first instance */
822 if (dev->num_inst == 1) {
823 dev->watchdog_timer.expires = jiffies +
824 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
825 add_timer(&dev->watchdog_timer);
826 ret = s5p_mfc_power_on();
828 mfc_err("power on failed\n");
832 ret = s5p_mfc_load_firmware(dev);
838 ret = s5p_mfc_init_hw(dev);
843 /* Init videobuf2 queue for CAPTURE */
845 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
846 q->drv_priv = &ctx->fh;
847 q->lock = &dev->mfc_mutex;
848 if (vdev == dev->vfd_dec) {
849 q->io_modes = VB2_MMAP;
850 q->ops = get_dec_queue_ops();
851 } else if (vdev == dev->vfd_enc) {
852 q->io_modes = VB2_MMAP | VB2_USERPTR;
853 q->ops = get_enc_queue_ops();
859 * We'll do mostly sequential access, so sacrifice TLB efficiency for
862 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
863 q->mem_ops = &vb2_dma_contig_memops;
864 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
865 ret = vb2_queue_init(q);
867 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
870 /* Init videobuf2 queue for OUTPUT */
872 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
873 q->drv_priv = &ctx->fh;
874 q->lock = &dev->mfc_mutex;
875 if (vdev == dev->vfd_dec) {
876 q->io_modes = VB2_MMAP;
877 q->ops = get_dec_queue_ops();
878 } else if (vdev == dev->vfd_enc) {
879 q->io_modes = VB2_MMAP | VB2_USERPTR;
880 q->ops = get_enc_queue_ops();
885 /* One way to indicate end-of-stream for MFC is to set the
886 * bytesused == 0. However by default videobuf2 handles bytesused
887 * equal to 0 as a special case and changes its value to the size
888 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
889 * will keep the value of bytesused intact.
891 q->allow_zero_bytesused = 1;
894 * We'll do mostly sequential access, so sacrifice TLB efficiency for
897 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
898 q->mem_ops = &vb2_dma_contig_memops;
899 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
900 ret = vb2_queue_init(q);
902 mfc_err("Failed to initialize videobuf2 queue(output)\n");
905 mutex_unlock(&dev->mfc_mutex);
908 /* Deinit when failure occurred */
910 if (dev->num_inst == 1)
911 s5p_mfc_deinit_hw(dev);
915 if (dev->num_inst == 1) {
916 if (s5p_mfc_power_off() < 0)
917 mfc_err("power off failed\n");
918 del_timer_sync(&dev->watchdog_timer);
921 s5p_mfc_dec_ctrls_delete(ctx);
923 dev->ctx[ctx->num] = NULL;
925 v4l2_fh_del(&ctx->fh);
926 v4l2_fh_exit(&ctx->fh);
930 mutex_unlock(&dev->mfc_mutex);
935 /* Release MFC context */
936 static int s5p_mfc_release(struct file *file)
938 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
939 struct s5p_mfc_dev *dev = ctx->dev;
941 /* if dev is null, do cleanup that doesn't need dev */
944 mutex_lock(&dev->mfc_mutex);
945 vb2_queue_release(&ctx->vq_src);
946 vb2_queue_release(&ctx->vq_dst);
950 /* Mark context as idle */
951 clear_work_bit_irqsave(ctx);
953 * If instance was initialised and not yet freed,
954 * return instance and free resources
956 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
957 mfc_debug(2, "Has to free instance\n");
958 s5p_mfc_close_mfc_inst(dev, ctx);
960 /* hardware locking scheme */
961 if (dev->curr_ctx == ctx->num)
962 clear_bit(0, &dev->hw_lock);
964 if (dev->num_inst == 0) {
965 mfc_debug(2, "Last instance\n");
966 s5p_mfc_deinit_hw(dev);
967 del_timer_sync(&dev->watchdog_timer);
969 if (s5p_mfc_power_off() < 0)
970 mfc_err("Power off failed\n");
972 mfc_debug(2, "Shutting down clock\n");
977 dev->ctx[ctx->num] = NULL;
978 s5p_mfc_dec_ctrls_delete(ctx);
979 v4l2_fh_del(&ctx->fh);
980 /* vdev is gone if dev is null */
982 v4l2_fh_exit(&ctx->fh);
986 mutex_unlock(&dev->mfc_mutex);
992 static unsigned int s5p_mfc_poll(struct file *file,
993 struct poll_table_struct *wait)
995 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
996 struct s5p_mfc_dev *dev = ctx->dev;
997 struct vb2_queue *src_q, *dst_q;
998 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1000 unsigned long flags;
1002 mutex_lock(&dev->mfc_mutex);
1003 src_q = &ctx->vq_src;
1004 dst_q = &ctx->vq_dst;
1006 * There has to be at least one buffer queued on each queued_list, which
1007 * means either in driver already or waiting for driver to claim it
1008 * and start processing.
1010 if ((!src_q->streaming || list_empty(&src_q->queued_list))
1011 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1015 mutex_unlock(&dev->mfc_mutex);
1016 poll_wait(file, &ctx->fh.wait, wait);
1017 poll_wait(file, &src_q->done_wq, wait);
1018 poll_wait(file, &dst_q->done_wq, wait);
1019 mutex_lock(&dev->mfc_mutex);
1020 if (v4l2_event_pending(&ctx->fh))
1022 spin_lock_irqsave(&src_q->done_lock, flags);
1023 if (!list_empty(&src_q->done_list))
1024 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1026 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1027 || src_vb->state == VB2_BUF_STATE_ERROR))
1028 rc |= POLLOUT | POLLWRNORM;
1029 spin_unlock_irqrestore(&src_q->done_lock, flags);
1030 spin_lock_irqsave(&dst_q->done_lock, flags);
1031 if (!list_empty(&dst_q->done_list))
1032 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1034 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1035 || dst_vb->state == VB2_BUF_STATE_ERROR))
1036 rc |= POLLIN | POLLRDNORM;
1037 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1039 mutex_unlock(&dev->mfc_mutex);
1044 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1046 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1047 struct s5p_mfc_dev *dev = ctx->dev;
1048 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1051 if (mutex_lock_interruptible(&dev->mfc_mutex))
1052 return -ERESTARTSYS;
1053 if (offset < DST_QUEUE_OFF_BASE) {
1054 mfc_debug(2, "mmaping source\n");
1055 ret = vb2_mmap(&ctx->vq_src, vma);
1056 } else { /* capture */
1057 mfc_debug(2, "mmaping destination\n");
1058 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1059 ret = vb2_mmap(&ctx->vq_dst, vma);
1061 mutex_unlock(&dev->mfc_mutex);
1066 static const struct v4l2_file_operations s5p_mfc_fops = {
1067 .owner = THIS_MODULE,
1068 .open = s5p_mfc_open,
1069 .release = s5p_mfc_release,
1070 .poll = s5p_mfc_poll,
1071 .unlocked_ioctl = video_ioctl2,
1072 .mmap = s5p_mfc_mmap,
1075 /* DMA memory related helper functions */
1076 static void s5p_mfc_memdev_release(struct device *dev)
1078 of_reserved_mem_device_release(dev);
1081 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1082 const char *name, unsigned int idx)
1084 struct device *child;
1087 child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1091 device_initialize(child);
1092 dev_set_name(child, "%s:%s", dev_name(dev), name);
1093 child->parent = dev;
1094 child->bus = dev->bus;
1095 child->coherent_dma_mask = dev->coherent_dma_mask;
1096 child->dma_mask = dev->dma_mask;
1097 child->release = s5p_mfc_memdev_release;
1099 if (device_add(child) == 0) {
1100 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1111 static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1113 struct device *dev = &mfc_dev->plat_dev->dev;
1115 dma_addr_t bank2_dma_addr;
1116 unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1120 * Create and initialize virtual devices for accessing
1121 * reserved memory regions.
1123 mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1125 if (!mfc_dev->mem_dev[BANK_L_CTX])
1127 mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1129 if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1130 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1134 /* Allocate memory for firmware and initialize both banks addresses */
1135 ret = s5p_mfc_alloc_firmware(mfc_dev);
1137 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1138 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1142 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1144 bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1145 align_size, &bank2_dma_addr, GFP_KERNEL);
1147 mfc_err("Allocating bank2 base failed\n");
1148 s5p_mfc_release_firmware(mfc_dev);
1149 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1150 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1154 /* Valid buffers passed to MFC encoder with LAST_FRAME command
1155 * should not have address of bank2 - MFC will treat it as a null frame.
1156 * To avoid such situation we set bank2 address below the pool address.
1158 mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1160 dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1163 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1165 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1171 static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1173 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1174 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1175 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1176 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1179 static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1181 struct device *dev = &mfc_dev->plat_dev->dev;
1182 unsigned long mem_size = SZ_4M;
1183 unsigned int bitmap_size;
1185 if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1189 mem_size = memparse(mfc_mem_size, NULL);
1191 bitmap_size = BITS_TO_LONGS(mem_size >> PAGE_SHIFT) * sizeof(long);
1193 mfc_dev->mem_bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1194 if (!mfc_dev->mem_bitmap)
1197 mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1198 &mfc_dev->mem_base, GFP_KERNEL);
1199 if (!mfc_dev->mem_virt) {
1200 kfree(mfc_dev->mem_bitmap);
1201 dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1202 (mem_size / SZ_1M));
1205 mfc_dev->mem_size = mem_size;
1206 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1207 mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1210 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1211 * as used (to keep required base alignment) and adjust base address
1213 if (mfc_dev->mem_base == (dma_addr_t)0) {
1214 unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1216 bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1217 mfc_dev->dma_base[BANK_L_CTX] += offset;
1218 mfc_dev->dma_base[BANK_R_CTX] += offset;
1221 /* Firmware allocation cannot fail in this case */
1222 s5p_mfc_alloc_firmware(mfc_dev);
1224 mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1225 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1227 dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1228 (mem_size / SZ_1M));
1233 static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1235 struct device *dev = &mfc_dev->plat_dev->dev;
1237 dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1239 kfree(mfc_dev->mem_bitmap);
1240 vb2_dma_contig_clear_max_seg_size(dev);
1243 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1245 struct device *dev = &mfc_dev->plat_dev->dev;
1247 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1248 return s5p_mfc_configure_common_memory(mfc_dev);
1250 return s5p_mfc_configure_2port_memory(mfc_dev);
1253 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1255 struct device *dev = &mfc_dev->plat_dev->dev;
1257 s5p_mfc_release_firmware(mfc_dev);
1258 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1259 s5p_mfc_unconfigure_common_memory(mfc_dev);
1261 s5p_mfc_unconfigure_2port_memory(mfc_dev);
1264 /* MFC probe function */
1265 static int s5p_mfc_probe(struct platform_device *pdev)
1267 struct s5p_mfc_dev *dev;
1268 struct video_device *vfd;
1269 struct resource *res;
1272 pr_debug("%s++\n", __func__);
1273 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1275 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1279 spin_lock_init(&dev->irqlock);
1280 spin_lock_init(&dev->condlock);
1281 dev->plat_dev = pdev;
1282 if (!dev->plat_dev) {
1283 mfc_err("No platform data specified\n");
1287 dev->variant = of_device_get_match_data(&pdev->dev);
1288 if (!dev->variant) {
1289 dev_err(&pdev->dev, "Failed to get device MFC hardware variant information\n");
1293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1295 if (IS_ERR(dev->regs_base))
1296 return PTR_ERR(dev->regs_base);
1298 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1300 dev_err(&pdev->dev, "failed to get irq resource\n");
1303 dev->irq = res->start;
1304 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1305 0, pdev->name, dev);
1307 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1311 ret = s5p_mfc_configure_dma_memory(dev);
1313 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1317 ret = s5p_mfc_init_pm(dev);
1319 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1324 * Load fails if fs isn't mounted. Try loading anyway.
1325 * _open() will load it, it it fails now. Ignore failure.
1327 s5p_mfc_load_firmware(dev);
1329 mutex_init(&dev->mfc_mutex);
1330 init_waitqueue_head(&dev->queue);
1332 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1333 atomic_set(&dev->watchdog_cnt, 0);
1334 init_timer(&dev->watchdog_timer);
1335 dev->watchdog_timer.data = (unsigned long)dev;
1336 dev->watchdog_timer.function = s5p_mfc_watchdog;
1338 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1340 goto err_v4l2_dev_reg;
1343 vfd = video_device_alloc();
1345 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1349 vfd->fops = &s5p_mfc_fops;
1350 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1351 vfd->release = video_device_release;
1352 vfd->lock = &dev->mfc_mutex;
1353 vfd->v4l2_dev = &dev->v4l2_dev;
1354 vfd->vfl_dir = VFL_DIR_M2M;
1355 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1357 video_set_drvdata(vfd, dev);
1360 vfd = video_device_alloc();
1362 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1366 vfd->fops = &s5p_mfc_fops;
1367 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1368 vfd->release = video_device_release;
1369 vfd->lock = &dev->mfc_mutex;
1370 vfd->v4l2_dev = &dev->v4l2_dev;
1371 vfd->vfl_dir = VFL_DIR_M2M;
1372 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1374 video_set_drvdata(vfd, dev);
1375 platform_set_drvdata(pdev, dev);
1377 /* Initialize HW ops and commands based on MFC version */
1378 s5p_mfc_init_hw_ops(dev);
1379 s5p_mfc_init_hw_cmds(dev);
1380 s5p_mfc_init_regs(dev);
1382 /* Register decoder and encoder */
1383 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1385 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1388 v4l2_info(&dev->v4l2_dev,
1389 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1391 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1393 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1396 v4l2_info(&dev->v4l2_dev,
1397 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1399 pr_debug("%s--\n", __func__);
1402 /* Deinit MFC if probe had failed */
1404 video_unregister_device(dev->vfd_dec);
1406 video_device_release(dev->vfd_enc);
1408 video_device_release(dev->vfd_dec);
1410 v4l2_device_unregister(&dev->v4l2_dev);
1412 s5p_mfc_final_pm(dev);
1414 s5p_mfc_unconfigure_dma_memory(dev);
1416 pr_debug("%s-- with error\n", __func__);
1421 /* Remove the driver */
1422 static int s5p_mfc_remove(struct platform_device *pdev)
1424 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1425 struct s5p_mfc_ctx *ctx;
1428 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1431 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1432 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1433 * after s5p_mfc_remove() is run during unbind.
1435 mutex_lock(&dev->mfc_mutex);
1436 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1440 /* clear ctx->dev */
1443 mutex_unlock(&dev->mfc_mutex);
1445 del_timer_sync(&dev->watchdog_timer);
1446 flush_work(&dev->watchdog_work);
1448 video_unregister_device(dev->vfd_enc);
1449 video_unregister_device(dev->vfd_dec);
1450 video_device_release(dev->vfd_enc);
1451 video_device_release(dev->vfd_dec);
1452 v4l2_device_unregister(&dev->v4l2_dev);
1453 s5p_mfc_unconfigure_dma_memory(dev);
1455 s5p_mfc_final_pm(dev);
1459 #ifdef CONFIG_PM_SLEEP
1461 static int s5p_mfc_suspend(struct device *dev)
1463 struct platform_device *pdev = to_platform_device(dev);
1464 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1467 if (m_dev->num_inst == 0)
1470 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1471 mfc_err("Error: going to suspend for a second time\n");
1475 /* Check if we're processing then wait if it necessary. */
1476 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1477 /* Try and lock the HW */
1478 /* Wait on the interrupt waitqueue */
1479 ret = wait_event_interruptible_timeout(m_dev->queue,
1480 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1482 mfc_err("Waiting for hardware to finish timed out\n");
1483 clear_bit(0, &m_dev->enter_suspend);
1488 ret = s5p_mfc_sleep(m_dev);
1490 clear_bit(0, &m_dev->enter_suspend);
1491 clear_bit(0, &m_dev->hw_lock);
1496 static int s5p_mfc_resume(struct device *dev)
1498 struct platform_device *pdev = to_platform_device(dev);
1499 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1501 if (m_dev->num_inst == 0)
1503 return s5p_mfc_wakeup(m_dev);
1507 /* Power management */
1508 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1509 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1512 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1513 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1514 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1515 .dsc = DESC_BUF_SIZE,
1516 .shm = SHARED_BUF_SIZE,
1519 static struct s5p_mfc_buf_size buf_size_v5 = {
1521 .cpb = MAX_CPB_SIZE,
1522 .priv = &mfc_buf_size_v5,
1525 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1526 .version = MFC_VERSION,
1527 .version_bit = MFC_V5_BIT,
1528 .port_num = MFC_NUM_PORTS,
1529 .buf_size = &buf_size_v5,
1530 .fw_name[0] = "/*(DEBLOBBED)*/",
1531 .clk_names = {"mfc", "sclk_mfc"},
1533 .use_clock_gating = true,
1536 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1537 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1538 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1539 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1540 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1541 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1544 static struct s5p_mfc_buf_size buf_size_v6 = {
1545 .fw = MAX_FW_SIZE_V6,
1546 .cpb = MAX_CPB_SIZE_V6,
1547 .priv = &mfc_buf_size_v6,
1550 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1551 .version = MFC_VERSION_V6,
1552 .version_bit = MFC_V6_BIT,
1553 .port_num = MFC_NUM_PORTS_V6,
1554 .buf_size = &buf_size_v6,
1555 .fw_name[0] = "/*(DEBLOBBED)*/",
1557 * v6-v2 firmware contains bug fixes and interface change
1558 * for init buffer command
1560 .fw_name[1] = "/*(DEBLOBBED)*/",
1561 .clk_names = {"mfc"},
1565 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1566 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1567 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1568 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1569 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1570 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1573 static struct s5p_mfc_buf_size buf_size_v7 = {
1574 .fw = MAX_FW_SIZE_V7,
1575 .cpb = MAX_CPB_SIZE_V7,
1576 .priv = &mfc_buf_size_v7,
1579 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1580 .version = MFC_VERSION_V7,
1581 .version_bit = MFC_V7_BIT,
1582 .port_num = MFC_NUM_PORTS_V7,
1583 .buf_size = &buf_size_v7,
1584 .fw_name[0] = "/*(DEBLOBBED)*/",
1585 .clk_names = {"mfc"},
1589 static struct s5p_mfc_variant mfc_drvdata_v7_3250 = {
1590 .version = MFC_VERSION_V7,
1591 .version_bit = MFC_V7_BIT,
1592 .port_num = MFC_NUM_PORTS_V7,
1593 .buf_size = &buf_size_v7,
1594 .fw_name[0] = "/*(DEBLOBBED)*/",
1595 .clk_names = {"mfc", "sclk_mfc"},
1599 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1600 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1601 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1602 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1603 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1604 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1607 static struct s5p_mfc_buf_size buf_size_v8 = {
1608 .fw = MAX_FW_SIZE_V8,
1609 .cpb = MAX_CPB_SIZE_V8,
1610 .priv = &mfc_buf_size_v8,
1613 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1614 .version = MFC_VERSION_V8,
1615 .version_bit = MFC_V8_BIT,
1616 .port_num = MFC_NUM_PORTS_V8,
1617 .buf_size = &buf_size_v8,
1618 .fw_name[0] = "/*(DEBLOBBED)*/",
1619 .clk_names = {"mfc"},
1623 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1624 .version = MFC_VERSION_V8,
1625 .version_bit = MFC_V8_BIT,
1626 .port_num = MFC_NUM_PORTS_V8,
1627 .buf_size = &buf_size_v8,
1628 .fw_name[0] = "/*(DEBLOBBED)*/",
1629 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1633 static const struct of_device_id exynos_mfc_match[] = {
1635 .compatible = "samsung,mfc-v5",
1636 .data = &mfc_drvdata_v5,
1638 .compatible = "samsung,mfc-v6",
1639 .data = &mfc_drvdata_v6,
1641 .compatible = "samsung,mfc-v7",
1642 .data = &mfc_drvdata_v7,
1644 .compatible = "samsung,exynos3250-mfc",
1645 .data = &mfc_drvdata_v7_3250,
1647 .compatible = "samsung,mfc-v8",
1648 .data = &mfc_drvdata_v8,
1650 .compatible = "samsung,exynos5433-mfc",
1651 .data = &mfc_drvdata_v8_5433,
1655 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1657 static struct platform_driver s5p_mfc_driver = {
1658 .probe = s5p_mfc_probe,
1659 .remove = s5p_mfc_remove,
1661 .name = S5P_MFC_NAME,
1662 .pm = &s5p_mfc_pm_ops,
1663 .of_match_table = exynos_mfc_match,
1667 module_platform_driver(s5p_mfc_driver);
1669 MODULE_LICENSE("GPL");
1670 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1671 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");