1 // SPDX-License-Identifier: GPL-2.0
3 * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface
4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
7 * Copyright (C) 2008 Magnus Damm
9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
10 * Copyright (C) 2006, Sascha Hauer, Pengutronix
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_graph.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/time.h>
31 #include <linux/videodev2.h>
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-dev.h>
37 #include <media/v4l2-device.h>
38 #include <media/v4l2-event.h>
39 #include <media/v4l2-fwnode.h>
40 #include <media/v4l2-image-sizes.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-mediabus.h>
43 #include <media/videobuf2-dma-contig.h>
45 #include <media/drv-intf/renesas-ceu.h>
47 #define DRIVER_NAME "renesas-ceu"
49 /* CEU registers offsets and masks. */
50 #define CEU_CAPSR 0x00 /* Capture start register */
51 #define CEU_CAPCR 0x04 /* Capture control register */
52 #define CEU_CAMCR 0x08 /* Capture interface control register */
53 #define CEU_CAMOR 0x10 /* Capture interface offset register */
54 #define CEU_CAPWR 0x14 /* Capture interface width register */
55 #define CEU_CAIFR 0x18 /* Capture interface input format register */
56 #define CEU_CRCNTR 0x28 /* CEU register control register */
57 #define CEU_CRCMPR 0x2c /* CEU register forcible control register */
58 #define CEU_CFLCR 0x30 /* Capture filter control register */
59 #define CEU_CFSZR 0x34 /* Capture filter size clip register */
60 #define CEU_CDWDR 0x38 /* Capture destination width register */
61 #define CEU_CDAYR 0x3c /* Capture data address Y register */
62 #define CEU_CDACR 0x40 /* Capture data address C register */
63 #define CEU_CFWCR 0x5c /* Firewall operation control register */
64 #define CEU_CDOCR 0x64 /* Capture data output control register */
65 #define CEU_CEIER 0x70 /* Capture event interrupt enable register */
66 #define CEU_CETCR 0x74 /* Capture event flag clear register */
67 #define CEU_CSTSR 0x7c /* Capture status register */
68 #define CEU_CSRTR 0x80 /* Capture software reset register */
70 /* Data synchronous fetch mode. */
71 #define CEU_CAMCR_JPEG BIT(4)
73 /* Input components ordering: CEU_CAMCR.DTARY field. */
74 #define CEU_CAMCR_DTARY_8_UYVY (0x00 << 8)
75 #define CEU_CAMCR_DTARY_8_VYUY (0x01 << 8)
76 #define CEU_CAMCR_DTARY_8_YUYV (0x02 << 8)
77 #define CEU_CAMCR_DTARY_8_YVYU (0x03 << 8)
78 /* TODO: input components ordering for 16 bits input. */
80 /* Bus transfer MTU. */
81 #define CEU_CAPCR_BUS_WIDTH256 (0x3 << 20)
83 /* Bus width configuration. */
84 #define CEU_CAMCR_DTIF_16BITS BIT(12)
86 /* No downsampling to planar YUV420 in image fetch mode. */
87 #define CEU_CDOCR_NO_DOWSAMPLE BIT(4)
89 /* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */
90 #define CEU_CDOCR_SWAP_ENDIANNESS (7)
92 /* Capture reset and enable bits. */
93 #define CEU_CAPSR_CPKIL BIT(16)
94 #define CEU_CAPSR_CE BIT(0)
96 /* CEU operating flag bit. */
97 #define CEU_CAPCR_CTNCP BIT(16)
98 #define CEU_CSTRST_CPTON BIT(0)
100 /* Platform specific IRQ source flags. */
101 #define CEU_CETCR_ALL_IRQS_RZ 0x397f313
102 #define CEU_CETCR_ALL_IRQS_SH4 0x3d7f313
104 /* Prohibited register access interrupt bit. */
105 #define CEU_CETCR_IGRW BIT(4)
106 /* One-frame capture end interrupt. */
107 #define CEU_CEIER_CPE BIT(0)
109 #define CEU_CEIER_VBP BIT(20)
110 #define CEU_CEIER_MASK (CEU_CEIER_CPE | CEU_CEIER_VBP)
112 #define CEU_MAX_WIDTH 2560
113 #define CEU_MAX_HEIGHT 1920
114 #define CEU_MAX_BPL 8188
115 #define CEU_W_MAX(w) ((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH)
116 #define CEU_H_MAX(h) ((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT)
119 * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce
121 * @mbus_code: bus format code
122 * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr)
123 * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components
125 * @swapped: does Cr appear before Cb?
126 * @bps: number of bits sent over bus for each sample
127 * @bpp: number of bits per pixels unit
129 struct ceu_mbus_fmt {
139 * ceu_buffer - Link vb2 buffer to the list of available buffers.
142 struct vb2_v4l2_buffer vb;
143 struct list_head queue;
146 static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf)
148 return container_of(vbuf, struct ceu_buffer, vb);
152 * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice.
155 struct v4l2_async_subdev asd;
156 struct v4l2_subdev *v4l2_sd;
158 /* per-subdevice mbus configuration options */
159 unsigned int mbus_flags;
160 struct ceu_mbus_fmt mbus_fmt;
163 static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_subdev *asd)
165 return container_of(asd, struct ceu_subdev, asd);
169 * ceu_device - CEU device instance
173 struct video_device vdev;
174 struct v4l2_device v4l2_dev;
176 /* subdevices descriptors */
177 struct ceu_subdev **subdevs;
178 /* the subdevice currently in use */
179 struct ceu_subdev *sd;
180 unsigned int sd_index;
183 /* platform specific mask with all IRQ sources flagged */
186 /* currently configured field and pixel format */
187 enum v4l2_field field;
188 struct v4l2_pix_format_mplane v4l2_pix;
190 /* async subdev notification helpers */
191 struct v4l2_async_notifier notifier;
193 /* vb2 queue, capture buffer list and active buffer pointer */
194 struct vb2_queue vb2_vq;
195 struct list_head capture;
196 struct vb2_v4l2_buffer *active;
197 unsigned int sequence;
199 /* mlock - lock access to interface reset and vb2 queue */
202 /* lock - lock access to capture buffer queue and active buffer */
205 /* base - CEU memory base address */
209 static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev)
211 return container_of(v4l2_dev, struct ceu_device, v4l2_dev);
214 /* --- CEU memory output formats --- */
217 * ceu_fmt - describe a memory output format supported by CEU interface.
219 * @fourcc: memory layout fourcc format code
220 * @bpp: number of bits for each pixel stored in memory
228 * ceu_format_list - List of supported memory output formats
230 * If sensor provides any YUYV bus format, all the following planar memory
231 * formats are available thanks to CEU re-ordering and sub-sampling
234 static const struct ceu_fmt ceu_fmt_list[] = {
236 .fourcc = V4L2_PIX_FMT_NV16,
240 .fourcc = V4L2_PIX_FMT_NV61,
244 .fourcc = V4L2_PIX_FMT_NV12,
248 .fourcc = V4L2_PIX_FMT_NV21,
252 .fourcc = V4L2_PIX_FMT_YUYV,
256 .fourcc = V4L2_PIX_FMT_UYVY,
260 .fourcc = V4L2_PIX_FMT_YVYU,
264 .fourcc = V4L2_PIX_FMT_VYUY,
269 static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc)
271 const struct ceu_fmt *fmt = &ceu_fmt_list[0];
274 for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++)
275 if (fmt->fourcc == fourcc)
281 static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix)
283 switch (pix->pixelformat) {
284 case V4L2_PIX_FMT_YUYV:
285 case V4L2_PIX_FMT_UYVY:
286 case V4L2_PIX_FMT_YVYU:
287 case V4L2_PIX_FMT_VYUY:
289 case V4L2_PIX_FMT_NV16:
290 case V4L2_PIX_FMT_NV61:
291 case V4L2_PIX_FMT_NV12:
292 case V4L2_PIX_FMT_NV21:
299 /* --- CEU HW operations --- */
301 static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data)
303 iowrite32(data, priv->base + reg_offs);
306 static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs)
308 return ioread32(priv->base + reg_offs);
312 * ceu_soft_reset() - Software reset the CEU interface.
313 * @ceu_device: CEU device.
315 * Returns 0 for success, -EIO for error.
317 static int ceu_soft_reset(struct ceu_device *ceudev)
321 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL);
323 for (i = 0; i < 100; i++) {
324 if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON))
330 dev_err(ceudev->dev, "soft reset time out\n");
334 for (i = 0; i < 100; i++) {
335 if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL))
340 /* If we get here, CEU has not reset properly. */
344 /* --- CEU Capture Operations --- */
347 * ceu_hw_config() - Configure CEU interface registers.
349 static int ceu_hw_config(struct ceu_device *ceudev)
351 u32 camcr, cdocr, cfzsr, cdwdr, capwr;
352 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
353 struct ceu_subdev *ceu_sd = ceudev->sd;
354 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
355 unsigned int mbus_flags = ceu_sd->mbus_flags;
357 /* Start configuring CEU registers */
358 ceu_write(ceudev, CEU_CAIFR, 0);
359 ceu_write(ceudev, CEU_CFWCR, 0);
360 ceu_write(ceudev, CEU_CRCNTR, 0);
361 ceu_write(ceudev, CEU_CRCMPR, 0);
363 /* Set the frame capture period for both image capture and data sync. */
364 capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8;
367 * Swap input data endianness by default.
368 * In data fetch mode bytes are received in chunks of 8 bytes.
369 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first)
370 * The data is however by default written to memory in reverse order:
371 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte)
373 * Use CEU_CDOCR[2:0] to swap data ordering.
375 cdocr = CEU_CDOCR_SWAP_ENDIANNESS;
378 * Configure CAMCR and CDOCR:
379 * match input components ordering with memory output format and
380 * handle downsampling to YUV420.
382 * If the memory output planar format is 'swapped' (Cr before Cb) and
383 * input format is not, use the swapped version of CAMCR.DTARY.
385 * If the memory output planar format is not 'swapped' (Cb before Cr)
386 * and input format is, use the swapped version of CAMCR.DTARY.
388 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0).
389 * If output is planar YUV422 set CDOCR[4] = 1
391 * No downsample for data fetch sync mode.
393 switch (pix->pixelformat) {
394 /* Data fetch sync mode */
395 case V4L2_PIX_FMT_YUYV:
396 case V4L2_PIX_FMT_YVYU:
397 case V4L2_PIX_FMT_UYVY:
398 case V4L2_PIX_FMT_VYUY:
399 camcr = CEU_CAMCR_JPEG;
400 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
401 cfzsr = (pix->height << 16) | pix->width;
402 cdwdr = pix->plane_fmt[0].bytesperline;
405 /* Non-swapped planar image capture mode. */
406 case V4L2_PIX_FMT_NV16:
407 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
409 case V4L2_PIX_FMT_NV12:
410 if (mbus_fmt->swapped)
411 camcr = mbus_fmt->fmt_order_swap;
413 camcr = mbus_fmt->fmt_order;
415 cfzsr = (pix->height << 16) | pix->width;
419 /* Swapped planar image capture mode. */
420 case V4L2_PIX_FMT_NV61:
421 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
423 case V4L2_PIX_FMT_NV21:
424 if (mbus_fmt->swapped)
425 camcr = mbus_fmt->fmt_order;
427 camcr = mbus_fmt->fmt_order_swap;
429 cfzsr = (pix->height << 16) | pix->width;
437 camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0;
438 camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0;
440 /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */
441 ceu_write(ceudev, CEU_CAMCR, camcr);
442 ceu_write(ceudev, CEU_CDOCR, cdocr);
443 ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256);
446 * TODO: make CAMOR offsets configurable.
447 * CAMOR wants to know the number of blanks between a VS/HS signal
448 * and valid data. This value should actually come from the sensor...
450 ceu_write(ceudev, CEU_CAMOR, 0);
452 /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */
453 ceu_write(ceudev, CEU_CAPWR, capwr);
454 ceu_write(ceudev, CEU_CFSZR, cfzsr);
455 ceu_write(ceudev, CEU_CDWDR, cdwdr);
461 * ceu_capture() - Trigger start of a capture sequence.
463 * Program the CEU DMA registers with addresses where to transfer image data.
465 static int ceu_capture(struct ceu_device *ceudev)
467 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
468 dma_addr_t phys_addr_top;
471 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0);
472 ceu_write(ceudev, CEU_CDAYR, phys_addr_top);
474 /* Ignore CbCr plane for non multi-planar image formats. */
475 if (ceu_fmt_mplane(pix)) {
477 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf,
479 ceu_write(ceudev, CEU_CDACR, phys_addr_top);
483 * Trigger new capture start: once for each frame, as we work in
484 * one-frame capture mode.
486 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE);
491 static irqreturn_t ceu_irq(int irq, void *data)
493 struct ceu_device *ceudev = data;
494 struct vb2_v4l2_buffer *vbuf;
495 struct ceu_buffer *buf;
498 /* Clean interrupt status. */
499 status = ceu_read(ceudev, CEU_CETCR);
500 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
502 /* Unexpected interrupt. */
503 if (!(status & CEU_CEIER_MASK))
506 spin_lock(&ceudev->lock);
508 /* Stale interrupt from a released buffer, ignore it. */
509 vbuf = ceudev->active;
511 spin_unlock(&ceudev->lock);
516 * When a VBP interrupt occurs, no capture end interrupt will occur
517 * and the image of that frame is not captured correctly.
519 if (status & CEU_CEIER_VBP) {
520 dev_err(ceudev->dev, "VBP interrupt: abort capture\n");
524 /* Prepare to return the 'previous' buffer. */
525 vbuf->vb2_buf.timestamp = ktime_get_ns();
526 vbuf->sequence = ceudev->sequence++;
527 vbuf->field = ceudev->field;
529 /* Prepare a new 'active' buffer and trigger a new capture. */
530 if (!list_empty(&ceudev->capture)) {
531 buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
533 list_del(&buf->queue);
534 ceudev->active = &buf->vb;
539 /* Return the 'previous' buffer. */
540 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
542 spin_unlock(&ceudev->lock);
547 /* Return the 'previous' buffer and all queued ones. */
548 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR);
550 list_for_each_entry(buf, &ceudev->capture, queue)
551 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
553 spin_unlock(&ceudev->lock);
558 /* --- CEU Videobuf2 operations --- */
560 static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane,
561 unsigned int bpl, unsigned int szimage)
563 memset(plane, 0, sizeof(*plane));
565 plane->sizeimage = szimage;
566 if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL)
567 plane->bytesperline = bpl;
571 * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format'
572 * information according to the currently configured
574 * @ceu_device: CEU device.
575 * @ceu_fmt: Active image format.
576 * @pix: Pixel format information (store line width and image sizes)
578 static void ceu_calc_plane_sizes(struct ceu_device *ceudev,
579 const struct ceu_fmt *ceu_fmt,
580 struct v4l2_pix_format_mplane *pix)
582 unsigned int bpl, szimage;
584 switch (pix->pixelformat) {
585 case V4L2_PIX_FMT_YUYV:
586 case V4L2_PIX_FMT_UYVY:
587 case V4L2_PIX_FMT_YVYU:
588 case V4L2_PIX_FMT_VYUY:
590 bpl = pix->width * ceu_fmt->bpp / 8;
591 szimage = pix->height * bpl;
592 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
595 case V4L2_PIX_FMT_NV12:
596 case V4L2_PIX_FMT_NV21:
599 szimage = pix->height * pix->width;
600 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
601 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2);
604 case V4L2_PIX_FMT_NV16:
605 case V4L2_PIX_FMT_NV61:
609 szimage = pix->height * pix->width;
610 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
611 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage);
617 * ceu_vb2_setup() - is called to check whether the driver can accept the
618 * requested number of buffers and to fill in plane sizes
619 * for the current frame format, if required.
621 static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count,
622 unsigned int *num_planes, unsigned int sizes[],
623 struct device *alloc_devs[])
625 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
626 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
629 /* num_planes is set: just check plane sizes. */
631 for (i = 0; i < pix->num_planes; i++)
632 if (sizes[i] < pix->plane_fmt[i].sizeimage)
638 /* num_planes not set: called from REQBUFS, just set plane sizes. */
639 *num_planes = pix->num_planes;
640 for (i = 0; i < pix->num_planes; i++)
641 sizes[i] = pix->plane_fmt[i].sizeimage;
646 static void ceu_vb2_queue(struct vb2_buffer *vb)
648 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
649 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
650 struct ceu_buffer *buf = vb2_to_ceu(vbuf);
651 unsigned long irqflags;
653 spin_lock_irqsave(&ceudev->lock, irqflags);
654 list_add_tail(&buf->queue, &ceudev->capture);
655 spin_unlock_irqrestore(&ceudev->lock, irqflags);
658 static int ceu_vb2_prepare(struct vb2_buffer *vb)
660 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
661 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
664 for (i = 0; i < pix->num_planes; i++) {
665 if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
667 "Plane size too small (%lu < %u)\n",
668 vb2_plane_size(vb, i),
669 pix->plane_fmt[i].sizeimage);
673 vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
679 static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count)
681 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
682 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
683 struct ceu_buffer *buf;
684 unsigned long irqflags;
687 /* Program the CEU interface according to the CEU image format. */
688 ret = ceu_hw_config(ceudev);
690 goto error_return_bufs;
692 ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1);
693 if (ret && ret != -ENOIOCTLCMD) {
695 "Subdevice failed to start streaming: %d\n", ret);
696 goto error_return_bufs;
699 spin_lock_irqsave(&ceudev->lock, irqflags);
700 ceudev->sequence = 0;
702 /* Grab the first available buffer and trigger the first capture. */
703 buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
706 spin_unlock_irqrestore(&ceudev->lock, irqflags);
708 "No buffer available for capture.\n");
709 goto error_stop_sensor;
712 list_del(&buf->queue);
713 ceudev->active = &buf->vb;
715 /* Clean and program interrupts for first capture. */
716 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
717 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
721 spin_unlock_irqrestore(&ceudev->lock, irqflags);
726 v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
729 spin_lock_irqsave(&ceudev->lock, irqflags);
730 list_for_each_entry(buf, &ceudev->capture, queue)
731 vb2_buffer_done(&ceudev->active->vb2_buf,
732 VB2_BUF_STATE_QUEUED);
733 ceudev->active = NULL;
734 spin_unlock_irqrestore(&ceudev->lock, irqflags);
739 static void ceu_stop_streaming(struct vb2_queue *vq)
741 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
742 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
743 struct ceu_buffer *buf;
744 unsigned long irqflags;
746 /* Clean and disable interrupt sources. */
747 ceu_write(ceudev, CEU_CETCR,
748 ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask);
749 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
751 v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
753 spin_lock_irqsave(&ceudev->lock, irqflags);
754 if (ceudev->active) {
755 vb2_buffer_done(&ceudev->active->vb2_buf,
756 VB2_BUF_STATE_ERROR);
757 ceudev->active = NULL;
760 /* Release all queued buffers. */
761 list_for_each_entry(buf, &ceudev->capture, queue)
762 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
763 INIT_LIST_HEAD(&ceudev->capture);
765 spin_unlock_irqrestore(&ceudev->lock, irqflags);
767 ceu_soft_reset(ceudev);
770 static const struct vb2_ops ceu_vb2_ops = {
771 .queue_setup = ceu_vb2_setup,
772 .buf_queue = ceu_vb2_queue,
773 .buf_prepare = ceu_vb2_prepare,
774 .wait_prepare = vb2_ops_wait_prepare,
775 .wait_finish = vb2_ops_wait_finish,
776 .start_streaming = ceu_start_streaming,
777 .stop_streaming = ceu_stop_streaming,
780 /* --- CEU image formats handling --- */
783 * __ceu_try_fmt() - test format on CEU and sensor
784 * @ceudev: The CEU device.
785 * @v4l2_fmt: format to test.
786 * @sd_mbus_code: the media bus code accepted by the subdevice; output param.
788 * Returns 0 for success, < 0 for errors.
790 static int __ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt,
793 struct ceu_subdev *ceu_sd = ceudev->sd;
794 struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
795 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
796 struct v4l2_subdev_pad_config pad_cfg;
797 struct v4l2_subdev_state pad_state = {
800 const struct ceu_fmt *ceu_fmt;
806 * Set format on sensor sub device: bus format used to produce memory
807 * format is selected depending on YUV component ordering or
808 * at initialization time.
810 struct v4l2_subdev_format sd_format = {
811 .which = V4L2_SUBDEV_FORMAT_TRY,
814 mbus_code_old = ceu_sd->mbus_fmt.mbus_code;
816 switch (pix->pixelformat) {
817 case V4L2_PIX_FMT_YUYV:
818 mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
820 case V4L2_PIX_FMT_UYVY:
821 mbus_code = MEDIA_BUS_FMT_UYVY8_2X8;
823 case V4L2_PIX_FMT_YVYU:
824 mbus_code = MEDIA_BUS_FMT_YVYU8_2X8;
826 case V4L2_PIX_FMT_VYUY:
827 mbus_code = MEDIA_BUS_FMT_VYUY8_2X8;
829 case V4L2_PIX_FMT_NV16:
830 case V4L2_PIX_FMT_NV61:
831 case V4L2_PIX_FMT_NV12:
832 case V4L2_PIX_FMT_NV21:
833 mbus_code = ceu_sd->mbus_fmt.mbus_code;
837 pix->pixelformat = V4L2_PIX_FMT_NV16;
838 mbus_code = ceu_sd->mbus_fmt.mbus_code;
842 ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat);
844 /* CFSZR requires height and width to be 4-pixel aligned. */
845 v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4,
846 &pix->height, 4, CEU_MAX_HEIGHT, 4, 0);
848 v4l2_fill_mbus_format_mplane(&sd_format.format, pix);
851 * Try with the mbus_code matching YUYV components ordering first,
852 * if that one fails, fallback to default selected at initialization
855 sd_format.format.code = mbus_code;
856 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_state, &sd_format);
858 if (ret == -EINVAL) {
860 sd_format.format.code = mbus_code_old;
861 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt,
862 &pad_state, &sd_format);
869 /* Apply size returned by sensor as the CEU can't scale. */
870 v4l2_fill_pix_format_mplane(pix, &sd_format.format);
872 /* Calculate per-plane sizes based on image format. */
873 ceu_calc_plane_sizes(ceudev, ceu_fmt, pix);
875 /* Report to caller the configured mbus format. */
876 *sd_mbus_code = sd_format.format.code;
882 * ceu_try_fmt() - Wrapper for __ceu_try_fmt; discard configured mbus_fmt
884 static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
888 return __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code);
892 * ceu_set_fmt() - Apply the supplied format to both sensor and CEU
894 static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
896 struct ceu_subdev *ceu_sd = ceudev->sd;
897 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
902 * Set format on sensor sub device: bus format used to produce memory
903 * format is selected at initialization time.
905 struct v4l2_subdev_format format = {
906 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
909 ret = __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code);
913 format.format.code = mbus_code;
914 v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp);
915 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &format);
919 ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp;
920 ceudev->field = V4L2_FIELD_NONE;
926 * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA
929 static int ceu_set_default_fmt(struct ceu_device *ceudev)
933 struct v4l2_format v4l2_fmt = {
934 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
937 .height = VGA_HEIGHT,
938 .field = V4L2_FIELD_NONE,
939 .pixelformat = V4L2_PIX_FMT_NV16,
943 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
944 .bytesperline = VGA_WIDTH * 2,
947 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
948 .bytesperline = VGA_WIDTH * 2,
954 ret = ceu_try_fmt(ceudev, &v4l2_fmt);
958 ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp;
959 ceudev->field = V4L2_FIELD_NONE;
965 * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize
966 * CEU media bus format used to produce memory formats.
968 * Find out if sensor can produce a permutation of 8-bits YUYV bus format.
969 * From a single 8-bits YUYV bus format the CEU can produce several memory
971 * - NV[12|21|16|61] through image fetch mode;
972 * - YUYV422 if sensor provides YUYV422
974 * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY
975 * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode
977 static int ceu_init_mbus_fmt(struct ceu_device *ceudev)
979 struct ceu_subdev *ceu_sd = ceudev->sd;
980 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
981 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
982 bool yuyv_bus_fmt = false;
984 struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = {
985 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
989 /* Find out if sensor can produce any permutation of 8-bits YUYV422. */
990 while (!yuyv_bus_fmt &&
991 !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code,
992 NULL, &sd_mbus_fmt)) {
993 switch (sd_mbus_fmt.code) {
994 case MEDIA_BUS_FMT_YUYV8_2X8:
995 case MEDIA_BUS_FMT_YVYU8_2X8:
996 case MEDIA_BUS_FMT_UYVY8_2X8:
997 case MEDIA_BUS_FMT_VYUY8_2X8:
1002 * Only support 8-bits YUYV bus formats at the moment;
1004 * TODO: add support for binary formats (data sync
1010 sd_mbus_fmt.index++;
1017 * Save the first encountered YUYV format as "mbus_fmt" and use it
1018 * to output all planar YUV422 and YUV420 (NV*) formats to memory as
1019 * well as for data synch fetch mode (YUYV - YVYU etc. ).
1021 mbus_fmt->mbus_code = sd_mbus_fmt.code;
1024 /* Annotate the selected bus format components ordering. */
1025 switch (sd_mbus_fmt.code) {
1026 case MEDIA_BUS_FMT_YUYV8_2X8:
1027 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YUYV;
1028 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YVYU;
1029 mbus_fmt->swapped = false;
1033 case MEDIA_BUS_FMT_YVYU8_2X8:
1034 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YVYU;
1035 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YUYV;
1036 mbus_fmt->swapped = true;
1040 case MEDIA_BUS_FMT_UYVY8_2X8:
1041 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_UYVY;
1042 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_VYUY;
1043 mbus_fmt->swapped = false;
1047 case MEDIA_BUS_FMT_VYUY8_2X8:
1048 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_VYUY;
1049 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_UYVY;
1050 mbus_fmt->swapped = true;
1058 /* --- Runtime PM Handlers --- */
1061 * ceu_runtime_resume() - soft-reset the interface and turn sensor power on.
1063 static int __maybe_unused ceu_runtime_resume(struct device *dev)
1065 struct ceu_device *ceudev = dev_get_drvdata(dev);
1066 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1068 v4l2_subdev_call(v4l2_sd, core, s_power, 1);
1070 ceu_soft_reset(ceudev);
1076 * ceu_runtime_suspend() - disable capture and interrupts and soft-reset.
1077 * Turn sensor power off.
1079 static int __maybe_unused ceu_runtime_suspend(struct device *dev)
1081 struct ceu_device *ceudev = dev_get_drvdata(dev);
1082 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1084 v4l2_subdev_call(v4l2_sd, core, s_power, 0);
1086 ceu_write(ceudev, CEU_CEIER, 0);
1087 ceu_soft_reset(ceudev);
1092 /* --- File Operations --- */
1094 static int ceu_open(struct file *file)
1096 struct ceu_device *ceudev = video_drvdata(file);
1099 ret = v4l2_fh_open(file);
1103 mutex_lock(&ceudev->mlock);
1104 /* Causes soft-reset and sensor power on on first open */
1105 ret = pm_runtime_resume_and_get(ceudev->dev);
1106 mutex_unlock(&ceudev->mlock);
1111 static int ceu_release(struct file *file)
1113 struct ceu_device *ceudev = video_drvdata(file);
1115 vb2_fop_release(file);
1117 mutex_lock(&ceudev->mlock);
1118 /* Causes soft-reset and sensor power down on last close */
1119 pm_runtime_put(ceudev->dev);
1120 mutex_unlock(&ceudev->mlock);
1125 static const struct v4l2_file_operations ceu_fops = {
1126 .owner = THIS_MODULE,
1128 .release = ceu_release,
1129 .unlocked_ioctl = video_ioctl2,
1130 .mmap = vb2_fop_mmap,
1131 .poll = vb2_fop_poll,
1134 /* --- Video Device IOCTLs --- */
1136 static int ceu_querycap(struct file *file, void *priv,
1137 struct v4l2_capability *cap)
1139 struct ceu_device *ceudev = video_drvdata(file);
1141 strscpy(cap->card, "Renesas CEU", sizeof(cap->card));
1142 strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
1143 snprintf(cap->bus_info, sizeof(cap->bus_info),
1144 "platform:renesas-ceu-%s", dev_name(ceudev->dev));
1149 static int ceu_enum_fmt_vid_cap(struct file *file, void *priv,
1150 struct v4l2_fmtdesc *f)
1152 const struct ceu_fmt *fmt;
1154 if (f->index >= ARRAY_SIZE(ceu_fmt_list))
1157 fmt = &ceu_fmt_list[f->index];
1158 f->pixelformat = fmt->fourcc;
1163 static int ceu_try_fmt_vid_cap(struct file *file, void *priv,
1164 struct v4l2_format *f)
1166 struct ceu_device *ceudev = video_drvdata(file);
1168 return ceu_try_fmt(ceudev, f);
1171 static int ceu_s_fmt_vid_cap(struct file *file, void *priv,
1172 struct v4l2_format *f)
1174 struct ceu_device *ceudev = video_drvdata(file);
1176 if (vb2_is_streaming(&ceudev->vb2_vq))
1179 return ceu_set_fmt(ceudev, f);
1182 static int ceu_g_fmt_vid_cap(struct file *file, void *priv,
1183 struct v4l2_format *f)
1185 struct ceu_device *ceudev = video_drvdata(file);
1187 f->fmt.pix_mp = ceudev->v4l2_pix;
1192 static int ceu_enum_input(struct file *file, void *priv,
1193 struct v4l2_input *inp)
1195 struct ceu_device *ceudev = video_drvdata(file);
1196 struct ceu_subdev *ceusd;
1198 if (inp->index >= ceudev->num_sd)
1201 ceusd = ceudev->subdevs[inp->index];
1203 inp->type = V4L2_INPUT_TYPE_CAMERA;
1205 snprintf(inp->name, sizeof(inp->name), "Camera%u: %s",
1206 inp->index, ceusd->v4l2_sd->name);
1211 static int ceu_g_input(struct file *file, void *priv, unsigned int *i)
1213 struct ceu_device *ceudev = video_drvdata(file);
1215 *i = ceudev->sd_index;
1220 static int ceu_s_input(struct file *file, void *priv, unsigned int i)
1222 struct ceu_device *ceudev = video_drvdata(file);
1223 struct ceu_subdev *ceu_sd_old;
1226 if (i >= ceudev->num_sd)
1229 if (vb2_is_streaming(&ceudev->vb2_vq))
1232 if (i == ceudev->sd_index)
1235 ceu_sd_old = ceudev->sd;
1236 ceudev->sd = ceudev->subdevs[i];
1239 * Make sure we can generate output image formats and apply
1242 ret = ceu_init_mbus_fmt(ceudev);
1244 ceudev->sd = ceu_sd_old;
1248 ret = ceu_set_default_fmt(ceudev);
1250 ceudev->sd = ceu_sd_old;
1254 /* Now that we're sure we can use the sensor, power off the old one. */
1255 v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0);
1256 v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1);
1258 ceudev->sd_index = i;
1263 static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1265 struct ceu_device *ceudev = video_drvdata(file);
1267 return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1270 static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1272 struct ceu_device *ceudev = video_drvdata(file);
1274 return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1277 static int ceu_enum_framesizes(struct file *file, void *fh,
1278 struct v4l2_frmsizeenum *fsize)
1280 struct ceu_device *ceudev = video_drvdata(file);
1281 struct ceu_subdev *ceu_sd = ceudev->sd;
1282 const struct ceu_fmt *ceu_fmt;
1283 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1286 struct v4l2_subdev_frame_size_enum fse = {
1287 .code = ceu_sd->mbus_fmt.mbus_code,
1288 .index = fsize->index,
1289 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1292 /* Just check if user supplied pixel format is supported. */
1293 ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format);
1297 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size,
1302 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1303 fsize->discrete.width = CEU_W_MAX(fse.max_width);
1304 fsize->discrete.height = CEU_H_MAX(fse.max_height);
1309 static int ceu_enum_frameintervals(struct file *file, void *fh,
1310 struct v4l2_frmivalenum *fival)
1312 struct ceu_device *ceudev = video_drvdata(file);
1313 struct ceu_subdev *ceu_sd = ceudev->sd;
1314 const struct ceu_fmt *ceu_fmt;
1315 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1318 struct v4l2_subdev_frame_interval_enum fie = {
1319 .code = ceu_sd->mbus_fmt.mbus_code,
1320 .index = fival->index,
1321 .width = fival->width,
1322 .height = fival->height,
1323 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1326 /* Just check if user supplied pixel format is supported. */
1327 ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format);
1331 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL,
1336 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1337 fival->discrete = fie.interval;
1342 static const struct v4l2_ioctl_ops ceu_ioctl_ops = {
1343 .vidioc_querycap = ceu_querycap,
1345 .vidioc_enum_fmt_vid_cap = ceu_enum_fmt_vid_cap,
1346 .vidioc_try_fmt_vid_cap_mplane = ceu_try_fmt_vid_cap,
1347 .vidioc_s_fmt_vid_cap_mplane = ceu_s_fmt_vid_cap,
1348 .vidioc_g_fmt_vid_cap_mplane = ceu_g_fmt_vid_cap,
1350 .vidioc_enum_input = ceu_enum_input,
1351 .vidioc_g_input = ceu_g_input,
1352 .vidioc_s_input = ceu_s_input,
1354 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1355 .vidioc_querybuf = vb2_ioctl_querybuf,
1356 .vidioc_qbuf = vb2_ioctl_qbuf,
1357 .vidioc_expbuf = vb2_ioctl_expbuf,
1358 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1359 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1360 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1361 .vidioc_streamon = vb2_ioctl_streamon,
1362 .vidioc_streamoff = vb2_ioctl_streamoff,
1364 .vidioc_g_parm = ceu_g_parm,
1365 .vidioc_s_parm = ceu_s_parm,
1366 .vidioc_enum_framesizes = ceu_enum_framesizes,
1367 .vidioc_enum_frameintervals = ceu_enum_frameintervals,
1369 .vidioc_log_status = v4l2_ctrl_log_status,
1370 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1371 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1375 * ceu_vdev_release() - release CEU video device memory when last reference
1376 * to this driver is closed
1378 static void ceu_vdev_release(struct video_device *vdev)
1380 struct ceu_device *ceudev = video_get_drvdata(vdev);
1385 static int ceu_notify_bound(struct v4l2_async_notifier *notifier,
1386 struct v4l2_subdev *v4l2_sd,
1387 struct v4l2_async_subdev *asd)
1389 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1390 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1391 struct ceu_subdev *ceu_sd = to_ceu_subdev(asd);
1393 ceu_sd->v4l2_sd = v4l2_sd;
1399 static int ceu_notify_complete(struct v4l2_async_notifier *notifier)
1401 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1402 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1403 struct video_device *vdev = &ceudev->vdev;
1404 struct vb2_queue *q = &ceudev->vb2_vq;
1405 struct v4l2_subdev *v4l2_sd;
1408 /* Initialize vb2 queue. */
1409 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1410 q->io_modes = VB2_MMAP | VB2_DMABUF;
1411 q->drv_priv = ceudev;
1412 q->ops = &ceu_vb2_ops;
1413 q->mem_ops = &vb2_dma_contig_memops;
1414 q->buf_struct_size = sizeof(struct ceu_buffer);
1415 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1416 q->min_buffers_needed = 2;
1417 q->lock = &ceudev->mlock;
1418 q->dev = ceudev->v4l2_dev.dev;
1420 ret = vb2_queue_init(q);
1425 * Make sure at least one sensor is primary and use it to initialize
1429 ceudev->sd = ceudev->subdevs[0];
1430 ceudev->sd_index = 0;
1433 v4l2_sd = ceudev->sd->v4l2_sd;
1435 ret = ceu_init_mbus_fmt(ceudev);
1439 ret = ceu_set_default_fmt(ceudev);
1443 /* Register the video device. */
1444 strscpy(vdev->name, DRIVER_NAME, sizeof(vdev->name));
1445 vdev->v4l2_dev = v4l2_dev;
1446 vdev->lock = &ceudev->mlock;
1447 vdev->queue = &ceudev->vb2_vq;
1448 vdev->ctrl_handler = v4l2_sd->ctrl_handler;
1449 vdev->fops = &ceu_fops;
1450 vdev->ioctl_ops = &ceu_ioctl_ops;
1451 vdev->release = ceu_vdev_release;
1452 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1454 video_set_drvdata(vdev, ceudev);
1456 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1458 v4l2_err(vdev->v4l2_dev,
1459 "video_register_device failed: %d\n", ret);
1466 static const struct v4l2_async_notifier_operations ceu_notify_ops = {
1467 .bound = ceu_notify_bound,
1468 .complete = ceu_notify_complete,
1472 * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in
1473 * ceu device. Both DT and platform data parsing use
1476 * Returns 0 for success, -ENOMEM for failure.
1478 static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd)
1480 /* Reserve memory for 'n_sd' ceu_subdev descriptors. */
1481 ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd,
1482 sizeof(*ceudev->subdevs), GFP_KERNEL);
1483 if (!ceudev->subdevs)
1487 ceudev->sd_index = 0;
1494 * ceu_parse_platform_data() - Initialize async_subdevices using platform
1495 * device provided data.
1497 static int ceu_parse_platform_data(struct ceu_device *ceudev,
1498 const struct ceu_platform_data *pdata)
1500 const struct ceu_async_subdev *async_sd;
1501 struct ceu_subdev *ceu_sd;
1505 if (pdata->num_subdevs == 0)
1508 ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs);
1512 for (i = 0; i < pdata->num_subdevs; i++) {
1514 /* Setup the ceu subdevice and the async subdevice. */
1515 async_sd = &pdata->subdevs[i];
1516 ceu_sd = v4l2_async_nf_add_i2c(&ceudev->notifier,
1517 async_sd->i2c_adapter_id,
1518 async_sd->i2c_address,
1520 if (IS_ERR(ceu_sd)) {
1521 v4l2_async_nf_cleanup(&ceudev->notifier);
1522 return PTR_ERR(ceu_sd);
1524 ceu_sd->mbus_flags = async_sd->flags;
1525 ceudev->subdevs[i] = ceu_sd;
1528 return pdata->num_subdevs;
1532 * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph.
1534 static int ceu_parse_dt(struct ceu_device *ceudev)
1536 struct device_node *of = ceudev->dev->of_node;
1537 struct device_node *ep;
1538 struct ceu_subdev *ceu_sd;
1543 num_ep = of_graph_get_endpoint_count(of);
1547 ret = ceu_init_async_subdevs(ceudev, num_ep);
1551 for (i = 0; i < num_ep; i++) {
1552 struct v4l2_fwnode_endpoint fw_ep = {
1553 .bus_type = V4L2_MBUS_PARALLEL,
1556 .flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1557 V4L2_MBUS_VSYNC_ACTIVE_HIGH,
1563 ep = of_graph_get_endpoint_by_regs(of, 0, i);
1565 dev_err(ceudev->dev,
1566 "No subdevice connected on endpoint %u.\n", i);
1571 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
1573 dev_err(ceudev->dev,
1574 "Unable to parse endpoint #%u: %d.\n", i, ret);
1578 /* Setup the ceu subdevice and the async subdevice. */
1579 ceu_sd = v4l2_async_nf_add_fwnode_remote(&ceudev->notifier,
1580 of_fwnode_handle(ep),
1582 if (IS_ERR(ceu_sd)) {
1583 ret = PTR_ERR(ceu_sd);
1586 ceu_sd->mbus_flags = fw_ep.bus.parallel.flags;
1587 ceudev->subdevs[i] = ceu_sd;
1595 v4l2_async_nf_cleanup(&ceudev->notifier);
1601 * struct ceu_data - Platform specific CEU data
1602 * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs
1603 * between SH4 and RZ platforms.
1609 static const struct ceu_data ceu_data_sh4 = {
1610 .irq_mask = CEU_CETCR_ALL_IRQS_SH4,
1613 #if IS_ENABLED(CONFIG_OF)
1614 static const struct ceu_data ceu_data_rz = {
1615 .irq_mask = CEU_CETCR_ALL_IRQS_RZ,
1618 static const struct of_device_id ceu_of_match[] = {
1619 { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz },
1620 { .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz },
1623 MODULE_DEVICE_TABLE(of, ceu_of_match);
1626 static int ceu_probe(struct platform_device *pdev)
1628 struct device *dev = &pdev->dev;
1629 const struct ceu_data *ceu_data;
1630 struct ceu_device *ceudev;
1635 ceudev = kzalloc(sizeof(*ceudev), GFP_KERNEL);
1639 platform_set_drvdata(pdev, ceudev);
1642 INIT_LIST_HEAD(&ceudev->capture);
1643 spin_lock_init(&ceudev->lock);
1644 mutex_init(&ceudev->mlock);
1646 ceudev->base = devm_platform_ioremap_resource(pdev, 0);
1647 if (IS_ERR(ceudev->base)) {
1648 ret = PTR_ERR(ceudev->base);
1649 goto error_free_ceudev;
1652 ret = platform_get_irq(pdev, 0);
1654 goto error_free_ceudev;
1657 ret = devm_request_irq(dev, irq, ceu_irq,
1658 0, dev_name(dev), ceudev);
1660 dev_err(&pdev->dev, "Unable to request CEU interrupt.\n");
1661 goto error_free_ceudev;
1664 pm_runtime_enable(dev);
1666 ret = v4l2_device_register(dev, &ceudev->v4l2_dev);
1668 goto error_pm_disable;
1670 v4l2_async_nf_init(&ceudev->notifier);
1672 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
1673 ceu_data = of_device_get_match_data(dev);
1674 num_subdevs = ceu_parse_dt(ceudev);
1675 } else if (dev->platform_data) {
1676 /* Assume SH4 if booting with platform data. */
1677 ceu_data = &ceu_data_sh4;
1678 num_subdevs = ceu_parse_platform_data(ceudev,
1679 dev->platform_data);
1681 num_subdevs = -EINVAL;
1684 if (num_subdevs < 0) {
1686 goto error_v4l2_unregister;
1688 ceudev->irq_mask = ceu_data->irq_mask;
1690 ceudev->notifier.v4l2_dev = &ceudev->v4l2_dev;
1691 ceudev->notifier.ops = &ceu_notify_ops;
1692 ret = v4l2_async_nf_register(&ceudev->v4l2_dev, &ceudev->notifier);
1696 dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev));
1701 v4l2_async_nf_cleanup(&ceudev->notifier);
1702 error_v4l2_unregister:
1703 v4l2_device_unregister(&ceudev->v4l2_dev);
1705 pm_runtime_disable(dev);
1712 static int ceu_remove(struct platform_device *pdev)
1714 struct ceu_device *ceudev = platform_get_drvdata(pdev);
1716 pm_runtime_disable(ceudev->dev);
1718 v4l2_async_nf_unregister(&ceudev->notifier);
1720 v4l2_async_nf_cleanup(&ceudev->notifier);
1722 v4l2_device_unregister(&ceudev->v4l2_dev);
1724 video_unregister_device(&ceudev->vdev);
1729 static const struct dev_pm_ops ceu_pm_ops = {
1730 SET_RUNTIME_PM_OPS(ceu_runtime_suspend,
1735 static struct platform_driver ceu_driver = {
1737 .name = DRIVER_NAME,
1739 .of_match_table = of_match_ptr(ceu_of_match),
1742 .remove = ceu_remove,
1745 module_platform_driver(ceu_driver);
1747 MODULE_DESCRIPTION("Renesas CEU camera driver");
1748 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>");
1749 MODULE_LICENSE("GPL v2");