1 // SPDX-License-Identifier: GPL-2.0
3 * Author: Mikhail Ulyanov
4 * Copyright (C) 2014-2015 Cogent Embedded, Inc. <source@cogentembedded.com>
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
7 * This is based on the drivers/media/platform/samsung/s5p-jpeg driver by
8 * Andrzej Pietrasiewicz and Jacek Anaszewski.
9 * Some portions of code inspired by VSP1 driver by Laurent Pinchart.
11 * TODO in order of priority:
14 * 3) V4L2_CID_JPEG_ACTIVE_MARKER
17 #include <asm/unaligned.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/string.h>
29 #include <linux/videodev2.h>
30 #include <media/jpeg.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fh.h>
35 #include <media/v4l2-mem2mem.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/videobuf2-v4l2.h>
38 #include <media/videobuf2-dma-contig.h>
41 #define DRV_NAME "rcar_jpu"
44 * Align JPEG header end to cache line to make sure we will not have any issues
45 * with cache; additionally to requirement (33.3.27 R01UH0501EJ0100 Rev.1.00)
47 #define JPU_JPEG_HDR_SIZE (ALIGN(0x258, L1_CACHE_BYTES))
48 #define JPU_JPEG_MAX_BYTES_PER_PIXEL 2 /* 16 bit precision format */
49 #define JPU_JPEG_MIN_SIZE 25 /* SOI + SOF + EOI */
50 #define JPU_JPEG_QTBL_SIZE 0x40
51 #define JPU_JPEG_HDCTBL_SIZE 0x1c
52 #define JPU_JPEG_HACTBL_SIZE 0xb2
53 #define JPU_JPEG_HEIGHT_OFFSET 0x91
54 #define JPU_JPEG_WIDTH_OFFSET 0x93
55 #define JPU_JPEG_SUBS_OFFSET 0x97
56 #define JPU_JPEG_QTBL_LUM_OFFSET 0x07
57 #define JPU_JPEG_QTBL_CHR_OFFSET 0x4c
58 #define JPU_JPEG_HDCTBL_LUM_OFFSET 0xa4
59 #define JPU_JPEG_HACTBL_LUM_OFFSET 0xc5
60 #define JPU_JPEG_HDCTBL_CHR_OFFSET 0x17c
61 #define JPU_JPEG_HACTBL_CHR_OFFSET 0x19d
62 #define JPU_JPEG_PADDING_OFFSET 0x24f
63 #define JPU_JPEG_LUM 0x00
64 #define JPU_JPEG_CHR 0x01
65 #define JPU_JPEG_DC 0x00
66 #define JPU_JPEG_AC 0x10
68 #define JPU_JPEG_422 0x21
69 #define JPU_JPEG_420 0x22
71 #define JPU_JPEG_DEFAULT_422_PIX_FMT V4L2_PIX_FMT_NV16M
72 #define JPU_JPEG_DEFAULT_420_PIX_FMT V4L2_PIX_FMT_NV12M
74 #define JPU_RESET_TIMEOUT 100 /* ms */
75 #define JPU_JOB_TIMEOUT 300 /* ms */
76 #define JPU_MAX_QUALITY 4
77 #define JPU_WIDTH_MIN 16
78 #define JPU_HEIGHT_MIN 16
79 #define JPU_WIDTH_MAX 4096
80 #define JPU_HEIGHT_MAX 4096
81 #define JPU_MEMALIGN 8
83 /* Flags that indicate a format can be used for capture/output */
84 #define JPU_FMT_TYPE_OUTPUT 0
85 #define JPU_FMT_TYPE_CAPTURE 1
86 #define JPU_ENC_CAPTURE (1 << 0)
87 #define JPU_ENC_OUTPUT (1 << 1)
88 #define JPU_DEC_CAPTURE (1 << 2)
89 #define JPU_DEC_OUTPUT (1 << 3)
92 * JPEG registers and bits
95 /* JPEG code mode register */
97 #define JCMOD_PCTR (1 << 7)
98 #define JCMOD_MSKIP_ENABLE (1 << 5)
99 #define JCMOD_DSP_ENC (0 << 3)
100 #define JCMOD_DSP_DEC (1 << 3)
101 #define JCMOD_REDU (7 << 0)
102 #define JCMOD_REDU_422 (1 << 0)
103 #define JCMOD_REDU_420 (2 << 0)
105 /* JPEG code command register */
107 #define JCCMD_SRST (1 << 12)
108 #define JCCMD_JEND (1 << 2)
109 #define JCCMD_JSRT (1 << 0)
111 /* JPEG code quantization table number register */
113 #define JCQTN_SHIFT(t) (((t) - 1) << 1)
115 /* JPEG code Huffman table number register */
117 #define JCHTN_AC_SHIFT(t) (((t) << 1) - 1)
118 #define JCHTN_DC_SHIFT(t) (((t) - 1) << 1)
120 #define JCVSZU 0x1c /* JPEG code vertical size upper register */
121 #define JCVSZD 0x20 /* JPEG code vertical size lower register */
122 #define JCHSZU 0x24 /* JPEG code horizontal size upper register */
123 #define JCHSZD 0x28 /* JPEG code horizontal size lower register */
124 #define JCSZ_MASK 0xff /* JPEG code h/v size register contains only 1 byte*/
126 #define JCDTCU 0x2c /* JPEG code data count upper register */
127 #define JCDTCM 0x30 /* JPEG code data count middle register */
128 #define JCDTCD 0x34 /* JPEG code data count lower register */
130 /* JPEG interrupt enable register */
132 #define JINTE_ERR (7 << 5) /* INT5 + INT6 + INT7 */
133 #define JINTE_TRANSF_COMPL (1 << 10)
135 /* JPEG interrupt status register */
137 #define JINTS_MASK 0x7c68
138 #define JINTS_ERR (1 << 5)
139 #define JINTS_PROCESS_COMPL (1 << 6)
140 #define JINTS_TRANSF_COMPL (1 << 10)
142 #define JCDERR 0x40 /* JPEG code decode error register */
143 #define JCDERR_MASK 0xf /* JPEG code decode error register mask*/
145 /* JPEG interface encoding */
147 #define JIFECNT_INFT_422 0
148 #define JIFECNT_INFT_420 1
149 #define JIFECNT_SWAP_WB (3 << 4) /* to JPU */
151 #define JIFESYA1 0x74 /* encode source Y address register 1 */
152 #define JIFESCA1 0x78 /* encode source C address register 1 */
153 #define JIFESYA2 0x7c /* encode source Y address register 2 */
154 #define JIFESCA2 0x80 /* encode source C address register 2 */
155 #define JIFESMW 0x84 /* encode source memory width register */
156 #define JIFESVSZ 0x88 /* encode source vertical size register */
157 #define JIFESHSZ 0x8c /* encode source horizontal size register */
158 #define JIFEDA1 0x90 /* encode destination address register 1 */
159 #define JIFEDA2 0x94 /* encode destination address register 2 */
161 /* JPEG decoding control register */
163 #define JIFDCNT_SWAP_WB (3 << 1) /* from JPU */
165 #define JIFDSA1 0xa4 /* decode source address register 1 */
166 #define JIFDDMW 0xb0 /* decode destination memory width register */
167 #define JIFDDVSZ 0xb4 /* decode destination vert. size register */
168 #define JIFDDHSZ 0xb8 /* decode destination horiz. size register */
169 #define JIFDDYA1 0xbc /* decode destination Y address register 1 */
170 #define JIFDDCA1 0xc0 /* decode destination C address register 1 */
172 #define JCQTBL(n) (0x10000 + (n) * 0x40) /* quantization tables regs */
173 #define JCHTBD(n) (0x10100 + (n) * 0x100) /* Huffman table DC regs */
174 #define JCHTBA(n) (0x10120 + (n) * 0x100) /* Huffman table AC regs */
177 * struct jpu - JPEG IP abstraction
178 * @mutex: the mutex protecting this structure
179 * @lock: spinlock protecting the device contexts
180 * @v4l2_dev: v4l2 device for mem2mem mode
181 * @vfd_encoder: video device node for encoder mem2mem mode
182 * @vfd_decoder: video device node for decoder mem2mem mode
183 * @m2m_dev: v4l2 mem2mem device data
184 * @curr: pointer to current context
185 * @regs: JPEG IP registers mapping
187 * @clk: JPEG IP clock
188 * @dev: JPEG IP struct device
189 * @ref_count: reference counter
194 struct v4l2_device v4l2_dev;
195 struct video_device vfd_encoder;
196 struct video_device vfd_decoder;
197 struct v4l2_m2m_dev *m2m_dev;
198 struct jpu_ctx *curr;
208 * struct jpu_buffer - driver's specific video buffer
210 * @compr_quality: destination image quality in compression mode
211 * @subsampling: source image subsampling in decompression mode
214 struct v4l2_m2m_buffer buf;
215 unsigned short compr_quality;
216 unsigned char subsampling;
220 * struct jpu_fmt - driver's internal format data
221 * @fourcc: the fourcc code, 0 if not applicable
222 * @colorspace: the colorspace specifier
223 * @bpp: number of bits per pixel per plane
224 * @h_align: horizontal alignment order (align to 2^h_align)
225 * @v_align: vertical alignment order (align to 2^v_align)
226 * @subsampling: (horizontal:4 | vertical:4) subsampling factor
227 * @num_planes: number of planes
228 * @types: types of queue this format is applicable to
242 * struct jpu_q_data - parameters of one queue
243 * @fmtinfo: driver-specific format of this queue
244 * @format: multiplanar format of this queue
245 * @sequence: sequence number
248 struct jpu_fmt *fmtinfo;
249 struct v4l2_pix_format_mplane format;
250 unsigned int sequence;
254 * struct jpu_ctx - the device context data
255 * @jpu: JPEG IP device for this context
256 * @encoder: compression (encode) operation or decompression (decode)
257 * @compr_quality: destination image quality in compression (encode) mode
258 * @out_q: source (output) queue information
259 * @cap_q: destination (capture) queue information
261 * @ctrl_handler: controls handler
266 unsigned short compr_quality;
267 struct jpu_q_data out_q;
268 struct jpu_q_data cap_q;
270 struct v4l2_ctrl_handler ctrl_handler;
274 * jpeg_buffer - description of memory containing input JPEG data
275 * @end: end position in the buffer
276 * @curr: current position in the buffer
283 static struct jpu_fmt jpu_formats[] = {
284 { V4L2_PIX_FMT_JPEG, V4L2_COLORSPACE_JPEG,
285 {0, 0}, 0, 0, 0, 1, JPU_ENC_CAPTURE | JPU_DEC_OUTPUT },
286 { V4L2_PIX_FMT_NV16M, V4L2_COLORSPACE_SRGB,
287 {8, 8}, 2, 2, JPU_JPEG_422, 2, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
288 { V4L2_PIX_FMT_NV12M, V4L2_COLORSPACE_SRGB,
289 {8, 4}, 2, 2, JPU_JPEG_420, 2, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
290 { V4L2_PIX_FMT_NV16, V4L2_COLORSPACE_SRGB,
291 {16, 0}, 2, 2, JPU_JPEG_422, 1, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
292 { V4L2_PIX_FMT_NV12, V4L2_COLORSPACE_SRGB,
293 {12, 0}, 2, 2, JPU_JPEG_420, 1, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
296 static const u8 zigzag[] = {
297 0x03, 0x02, 0x0b, 0x13, 0x0a, 0x01, 0x00, 0x09,
298 0x12, 0x1b, 0x23, 0x1a, 0x11, 0x08, 0x07, 0x06,
299 0x0f, 0x10, 0x19, 0x22, 0x2b, 0x33, 0x2a, 0x21,
300 0x18, 0x17, 0x0e, 0x05, 0x04, 0x0d, 0x16, 0x1f,
301 0x20, 0x29, 0x32, 0x3b, 0x3a, 0x31, 0x28, 0x27,
302 0x1e, 0x15, 0x0e, 0x14, 0x10, 0x26, 0x2f, 0x30,
303 0x39, 0x38, 0x37, 0x2e, 0x25, 0x1c, 0x24, 0x2b,
304 0x36, 0x3f, 0x3e, 0x35, 0x2c, 0x34, 0x3d, 0x3c
307 #define QTBL_SIZE (ALIGN(JPU_JPEG_QTBL_SIZE, \
308 sizeof(unsigned int)) / sizeof(unsigned int))
309 #define HDCTBL_SIZE (ALIGN(JPU_JPEG_HDCTBL_SIZE, \
310 sizeof(unsigned int)) / sizeof(unsigned int))
311 #define HACTBL_SIZE (ALIGN(JPU_JPEG_HACTBL_SIZE, \
312 sizeof(unsigned int)) / sizeof(unsigned int))
314 * Start of image; Quantization tables
315 * SOF0 (17 bytes payload) is Baseline DCT - Sample precision, height, width,
316 * Number of image components, (Ci:8 - Hi:4 - Vi:4 - Tq:8) * 3 - Y,Cb,Cr;
317 * Huffman tables; Padding with 0xff (33.3.27 R01UH0501EJ0100 Rev.1.00)
319 #define JPU_JPEG_HDR_BLOB { \
320 0xff, JPEG_MARKER_SOI, 0xff, JPEG_MARKER_DQT, 0x00, \
321 JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_LUM, \
322 [JPU_JPEG_QTBL_LUM_OFFSET ... \
323 JPU_JPEG_QTBL_LUM_OFFSET + JPU_JPEG_QTBL_SIZE - 1] = 0x00, \
324 0xff, JPEG_MARKER_DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_CHR, \
325 [JPU_JPEG_QTBL_CHR_OFFSET ... JPU_JPEG_QTBL_CHR_OFFSET + \
326 JPU_JPEG_QTBL_SIZE - 1] = 0x00, \
327 0xff, JPEG_MARKER_SOF0, 0x00, 0x11, 0x08, \
328 [JPU_JPEG_HEIGHT_OFFSET ... JPU_JPEG_HEIGHT_OFFSET + 1] = 0x00, \
329 [JPU_JPEG_WIDTH_OFFSET ... JPU_JPEG_WIDTH_OFFSET + 1] = 0x00, \
330 0x03, 0x01, [JPU_JPEG_SUBS_OFFSET] = 0x00, JPU_JPEG_LUM, \
331 0x02, 0x11, JPU_JPEG_CHR, 0x03, 0x11, JPU_JPEG_CHR, \
332 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, \
333 JPU_JPEG_LUM | JPU_JPEG_DC, \
334 [JPU_JPEG_HDCTBL_LUM_OFFSET ... \
335 JPU_JPEG_HDCTBL_LUM_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \
336 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, \
337 JPU_JPEG_LUM | JPU_JPEG_AC, \
338 [JPU_JPEG_HACTBL_LUM_OFFSET ... \
339 JPU_JPEG_HACTBL_LUM_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \
340 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, \
341 JPU_JPEG_CHR | JPU_JPEG_DC, \
342 [JPU_JPEG_HDCTBL_CHR_OFFSET ... \
343 JPU_JPEG_HDCTBL_CHR_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \
344 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, \
345 JPU_JPEG_CHR | JPU_JPEG_AC, \
346 [JPU_JPEG_HACTBL_CHR_OFFSET ... \
347 JPU_JPEG_HACTBL_CHR_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \
348 [JPU_JPEG_PADDING_OFFSET ... JPU_JPEG_HDR_SIZE - 1] = 0xff \
351 static unsigned char jpeg_hdrs[JPU_MAX_QUALITY][JPU_JPEG_HDR_SIZE] = {
352 [0 ... JPU_MAX_QUALITY - 1] = JPU_JPEG_HDR_BLOB
355 static const unsigned int qtbl_lum[JPU_MAX_QUALITY][QTBL_SIZE] = {
357 0x14101927, 0x322e3e44, 0x10121726, 0x26354144,
358 0x19171f26, 0x35414444, 0x27262635, 0x41444444,
359 0x32263541, 0x44444444, 0x2e354144, 0x44444444,
360 0x3e414444, 0x44444444, 0x44444444, 0x44444444
363 0x100b0b10, 0x171b1f1e, 0x0b0c0c0f, 0x1417171e,
364 0x0b0c0d10, 0x171a232f, 0x100f1017, 0x1a252f40,
365 0x1714171a, 0x27334040, 0x1b171a25, 0x33404040,
366 0x1f17232f, 0x40404040, 0x1e1e2f40, 0x40404040
369 0x0c08080c, 0x11151817, 0x0809090b, 0x0f131217,
370 0x08090a0c, 0x13141b24, 0x0c0b0c15, 0x141c2435,
371 0x110f1314, 0x1e27333b, 0x1513141c, 0x27333b3b,
372 0x18121b24, 0x333b3b3b, 0x17172435, 0x3b3b3b3b
375 0x08060608, 0x0c0e1011, 0x06060608, 0x0a0d0c0f,
376 0x06060708, 0x0d0e1218, 0x0808080e, 0x0d131823,
377 0x0c0a0d0d, 0x141a2227, 0x0e0d0e13, 0x1a222727,
378 0x100c1318, 0x22272727, 0x110f1823, 0x27272727
382 static const unsigned int qtbl_chr[JPU_MAX_QUALITY][QTBL_SIZE] = {
384 0x15192026, 0x36444444, 0x191c1826, 0x36444444,
385 0x2018202b, 0x42444444, 0x26262b35, 0x44444444,
386 0x36424444, 0x44444444, 0x44444444, 0x44444444,
387 0x44444444, 0x44444444, 0x44444444, 0x44444444
390 0x110f1115, 0x141a2630, 0x0f131211, 0x141a232b,
391 0x11121416, 0x1a1e2e35, 0x1511161c, 0x1e273540,
392 0x14141a1e, 0x27304040, 0x1a1a1e27, 0x303f4040,
393 0x26232e35, 0x40404040, 0x302b3540, 0x40404040
396 0x0d0b0d10, 0x14141d25, 0x0b0e0e0e, 0x10141a20,
397 0x0d0e0f11, 0x14172328, 0x100e1115, 0x171e2832,
398 0x14101417, 0x1e25323b, 0x1414171e, 0x25303b3b,
399 0x1d1a2328, 0x323b3b3b, 0x25202832, 0x3b3b3b3b
402 0x0908090b, 0x0e111318, 0x080a090b, 0x0e0d1116,
403 0x09090d0e, 0x0d0f171a, 0x0b0b0e0e, 0x0f141a21,
404 0x0e0e0d0f, 0x14182127, 0x110d0f14, 0x18202727,
405 0x1311171a, 0x21272727, 0x18161a21, 0x27272727
409 static const unsigned int hdctbl_lum[HDCTBL_SIZE] = {
410 0x00010501, 0x01010101, 0x01000000, 0x00000000,
411 0x00010203, 0x04050607, 0x08090a0b
414 static const unsigned int hdctbl_chr[HDCTBL_SIZE] = {
415 0x00010501, 0x01010101, 0x01000000, 0x00000000,
416 0x00010203, 0x04050607, 0x08090a0b
419 static const unsigned int hactbl_lum[HACTBL_SIZE] = {
420 0x00020103, 0x03020403, 0x05050404, 0x0000017d, 0x01020300, 0x04110512,
421 0x21314106, 0x13516107, 0x22711432, 0x8191a108, 0x2342b1c1, 0x1552d1f0,
422 0x24336272, 0x82090a16, 0x1718191a, 0x25262728, 0x292a3435, 0x36373839,
423 0x3a434445, 0x46474849, 0x4a535455, 0x56575859, 0x5a636465, 0x66676869,
424 0x6a737475, 0x76777879, 0x7a838485, 0x86878889, 0x8a929394, 0x95969798,
425 0x999aa2a3, 0xa4a5a6a7, 0xa8a9aab2, 0xb3b4b5b6, 0xb7b8b9ba, 0xc2c3c4c5,
426 0xc6c7c8c9, 0xcad2d3d4, 0xd5d6d7d8, 0xd9dae1e2, 0xe3e4e5e6, 0xe7e8e9ea,
427 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fa0000
430 static const unsigned int hactbl_chr[HACTBL_SIZE] = {
431 0x00020103, 0x03020403, 0x05050404, 0x0000017d, 0x01020300, 0x04110512,
432 0x21314106, 0x13516107, 0x22711432, 0x8191a108, 0x2342b1c1, 0x1552d1f0,
433 0x24336272, 0x82090a16, 0x1718191a, 0x25262728, 0x292a3435, 0x36373839,
434 0x3a434445, 0x46474849, 0x4a535455, 0x56575859, 0x5a636465, 0x66676869,
435 0x6a737475, 0x76777879, 0x7a838485, 0x86878889, 0x8a929394, 0x95969798,
436 0x999aa2a3, 0xa4a5a6a7, 0xa8a9aab2, 0xb3b4b5b6, 0xb7b8b9ba, 0xc2c3c4c5,
437 0xc6c7c8c9, 0xcad2d3d4, 0xd5d6d7d8, 0xd9dae1e2, 0xe3e4e5e6, 0xe7e8e9ea,
438 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fa0000
441 static const char *error_to_text[16] = {
444 "SOF1 to SOFF detected",
445 "Subsampling not detected",
446 "SOF accuracy error",
447 "DQT accuracy error",
450 "SOF0, DQT, and DHT not detected when SOS detected",
453 "Restart interval data number error detected",
455 "Last MCU data number error",
456 "Block data number error",
460 static struct jpu_buffer *vb2_to_jpu_buffer(struct vb2_v4l2_buffer *vb)
462 struct v4l2_m2m_buffer *b =
463 container_of(vb, struct v4l2_m2m_buffer, vb);
465 return container_of(b, struct jpu_buffer, buf);
468 static u32 jpu_read(struct jpu *jpu, unsigned int reg)
470 return ioread32(jpu->regs + reg);
473 static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg)
475 iowrite32(val, jpu->regs + reg);
478 static struct jpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *c)
480 return container_of(c->handler, struct jpu_ctx, ctrl_handler);
483 static struct jpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
485 return container_of(fh, struct jpu_ctx, fh);
488 static void jpu_set_tbl(struct jpu *jpu, u32 reg, const unsigned int *tbl,
492 for (i = 0; i < len; i++)
493 jpu_write(jpu, tbl[i], reg + (i << 2));
496 static void jpu_set_qtbl(struct jpu *jpu, unsigned short quality)
498 jpu_set_tbl(jpu, JCQTBL(0), qtbl_lum[quality], QTBL_SIZE);
499 jpu_set_tbl(jpu, JCQTBL(1), qtbl_chr[quality], QTBL_SIZE);
502 static void jpu_set_htbl(struct jpu *jpu)
504 jpu_set_tbl(jpu, JCHTBD(0), hdctbl_lum, HDCTBL_SIZE);
505 jpu_set_tbl(jpu, JCHTBA(0), hactbl_lum, HACTBL_SIZE);
506 jpu_set_tbl(jpu, JCHTBD(1), hdctbl_chr, HDCTBL_SIZE);
507 jpu_set_tbl(jpu, JCHTBA(1), hactbl_chr, HACTBL_SIZE);
510 static int jpu_wait_reset(struct jpu *jpu)
512 unsigned long timeout;
514 timeout = jiffies + msecs_to_jiffies(JPU_RESET_TIMEOUT);
516 while (jpu_read(jpu, JCCMD) & JCCMD_SRST) {
517 if (time_after(jiffies, timeout)) {
518 dev_err(jpu->dev, "timed out in reset\n");
527 static int jpu_reset(struct jpu *jpu)
529 jpu_write(jpu, JCCMD_SRST, JCCMD);
530 return jpu_wait_reset(jpu);
534 * ============================================================================
535 * video ioctl operations
536 * ============================================================================
538 static void put_qtbl(u8 *p, const u8 *qtbl)
542 for (i = 0; i < ARRAY_SIZE(zigzag); i++)
543 p[i] = *(qtbl + zigzag[i]);
546 static void put_htbl(u8 *p, const u8 *htbl, unsigned int len)
550 for (i = 0; i < len; i += 4)
551 for (j = 0; j < 4 && (i + j) < len; ++j)
552 p[i + j] = htbl[i + 3 - j];
555 static void jpu_generate_hdr(unsigned short quality, unsigned char *p)
557 put_qtbl(p + JPU_JPEG_QTBL_LUM_OFFSET, (const u8 *)qtbl_lum[quality]);
558 put_qtbl(p + JPU_JPEG_QTBL_CHR_OFFSET, (const u8 *)qtbl_chr[quality]);
560 put_htbl(p + JPU_JPEG_HDCTBL_LUM_OFFSET, (const u8 *)hdctbl_lum,
561 JPU_JPEG_HDCTBL_SIZE);
562 put_htbl(p + JPU_JPEG_HACTBL_LUM_OFFSET, (const u8 *)hactbl_lum,
563 JPU_JPEG_HACTBL_SIZE);
565 put_htbl(p + JPU_JPEG_HDCTBL_CHR_OFFSET, (const u8 *)hdctbl_chr,
566 JPU_JPEG_HDCTBL_SIZE);
567 put_htbl(p + JPU_JPEG_HACTBL_CHR_OFFSET, (const u8 *)hactbl_chr,
568 JPU_JPEG_HACTBL_SIZE);
571 static int get_byte(struct jpeg_buffer *buf)
573 if (buf->curr >= buf->end)
576 return *(u8 *)buf->curr++;
579 static int get_word_be(struct jpeg_buffer *buf, unsigned int *word)
581 if (buf->end - buf->curr < 2)
584 *word = get_unaligned_be16(buf->curr);
590 static void skip(struct jpeg_buffer *buf, unsigned long len)
592 buf->curr += min((unsigned long)(buf->end - buf->curr), len);
595 static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width,
596 unsigned int *height)
598 struct jpeg_buffer jpeg_buffer;
602 jpeg_buffer.end = buffer + size;
603 jpeg_buffer.curr = buffer;
606 * basic size check and EOI - we don't want to let JPU cross
607 * buffer bounds in any case. Hope it's stopping by EOI.
609 if (size < JPU_JPEG_MIN_SIZE ||
610 *(u8 *)(buffer + size - 1) != JPEG_MARKER_EOI)
616 /* skip preceding filler bytes */
618 c = get_byte(&jpeg_buffer);
619 while (c == 0xff || c == 0);
621 if (!soi && c == JPEG_MARKER_SOI) {
624 } else if (soi != (c != JPEG_MARKER_SOI))
628 case JPEG_MARKER_SOF0: /* SOF0: baseline JPEG */
629 skip(&jpeg_buffer, 3); /* segment length and bpp */
630 if (get_word_be(&jpeg_buffer, height) ||
631 get_word_be(&jpeg_buffer, width) ||
632 get_byte(&jpeg_buffer) != 3) /* YCbCr only */
635 skip(&jpeg_buffer, 1);
636 return get_byte(&jpeg_buffer);
637 case JPEG_MARKER_DHT:
638 case JPEG_MARKER_DQT:
639 case JPEG_MARKER_COM:
640 case JPEG_MARKER_DRI:
641 case JPEG_MARKER_APP0 ... JPEG_MARKER_APP0 + 0x0f:
642 if (get_word_be(&jpeg_buffer, &word))
644 skip(&jpeg_buffer, (long)word - 2);
656 static int jpu_querycap(struct file *file, void *priv,
657 struct v4l2_capability *cap)
659 struct jpu_ctx *ctx = fh_to_ctx(priv);
662 strscpy(cap->card, DRV_NAME " encoder", sizeof(cap->card));
664 strscpy(cap->card, DRV_NAME " decoder", sizeof(cap->card));
666 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver));
667 memset(cap->reserved, 0, sizeof(cap->reserved));
672 static struct jpu_fmt *jpu_find_format(bool encoder, u32 pixelformat,
673 unsigned int fmt_type)
675 unsigned int i, fmt_flag;
678 fmt_flag = fmt_type == JPU_FMT_TYPE_OUTPUT ? JPU_ENC_OUTPUT :
681 fmt_flag = fmt_type == JPU_FMT_TYPE_OUTPUT ? JPU_DEC_OUTPUT :
684 for (i = 0; i < ARRAY_SIZE(jpu_formats); i++) {
685 struct jpu_fmt *fmt = &jpu_formats[i];
687 if (fmt->fourcc == pixelformat && fmt->types & fmt_flag)
694 static int jpu_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
696 unsigned int i, num = 0;
698 for (i = 0; i < ARRAY_SIZE(jpu_formats); ++i) {
699 if (jpu_formats[i].types & type) {
706 if (i >= ARRAY_SIZE(jpu_formats))
709 f->pixelformat = jpu_formats[i].fourcc;
714 static int jpu_enum_fmt_cap(struct file *file, void *priv,
715 struct v4l2_fmtdesc *f)
717 struct jpu_ctx *ctx = fh_to_ctx(priv);
719 return jpu_enum_fmt(f, ctx->encoder ? JPU_ENC_CAPTURE :
723 static int jpu_enum_fmt_out(struct file *file, void *priv,
724 struct v4l2_fmtdesc *f)
726 struct jpu_ctx *ctx = fh_to_ctx(priv);
728 return jpu_enum_fmt(f, ctx->encoder ? JPU_ENC_OUTPUT : JPU_DEC_OUTPUT);
731 static struct jpu_q_data *jpu_get_q_data(struct jpu_ctx *ctx,
732 enum v4l2_buf_type type)
734 if (V4L2_TYPE_IS_OUTPUT(type))
740 static void jpu_bound_align_image(u32 *w, unsigned int w_min,
741 unsigned int w_max, unsigned int w_align,
742 u32 *h, unsigned int h_min,
743 unsigned int h_max, unsigned int h_align)
745 unsigned int width, height, w_step, h_step;
750 w_step = 1U << w_align;
751 h_step = 1U << h_align;
752 v4l_bound_align_image(w, w_min, w_max, w_align, h, h_min, h_max,
755 if (*w < width && *w + w_step < w_max)
757 if (*h < height && *h + h_step < h_max)
761 static int __jpu_try_fmt(struct jpu_ctx *ctx, struct jpu_fmt **fmtinfo,
762 struct v4l2_pix_format_mplane *pix,
763 enum v4l2_buf_type type)
766 unsigned int f_type, w, h;
768 f_type = V4L2_TYPE_IS_OUTPUT(type) ? JPU_FMT_TYPE_OUTPUT :
769 JPU_FMT_TYPE_CAPTURE;
771 fmt = jpu_find_format(ctx->encoder, pix->pixelformat, f_type);
773 unsigned int pixelformat;
775 dev_dbg(ctx->jpu->dev, "unknown format; set default format\n");
777 pixelformat = f_type == JPU_FMT_TYPE_OUTPUT ?
778 V4L2_PIX_FMT_NV16M : V4L2_PIX_FMT_JPEG;
780 pixelformat = f_type == JPU_FMT_TYPE_CAPTURE ?
781 V4L2_PIX_FMT_NV16M : V4L2_PIX_FMT_JPEG;
782 fmt = jpu_find_format(ctx->encoder, pixelformat, f_type);
785 pix->pixelformat = fmt->fourcc;
786 pix->colorspace = fmt->colorspace;
787 pix->field = V4L2_FIELD_NONE;
788 pix->num_planes = fmt->num_planes;
790 jpu_bound_align_image(&pix->width, JPU_WIDTH_MIN, JPU_WIDTH_MAX,
791 fmt->h_align, &pix->height, JPU_HEIGHT_MIN,
792 JPU_HEIGHT_MAX, fmt->v_align);
797 if (fmt->fourcc == V4L2_PIX_FMT_JPEG) {
798 /* ignore userspaces's sizeimage for encoding */
799 if (pix->plane_fmt[0].sizeimage <= 0 || ctx->encoder)
800 pix->plane_fmt[0].sizeimage = JPU_JPEG_HDR_SIZE +
801 (JPU_JPEG_MAX_BYTES_PER_PIXEL * w * h);
802 pix->plane_fmt[0].bytesperline = 0;
804 unsigned int i, bpl = 0;
806 for (i = 0; i < pix->num_planes; ++i)
807 bpl = max(bpl, pix->plane_fmt[i].bytesperline);
809 bpl = clamp_t(unsigned int, bpl, w, JPU_WIDTH_MAX);
810 bpl = round_up(bpl, JPU_MEMALIGN);
812 for (i = 0; i < pix->num_planes; ++i) {
813 pix->plane_fmt[i].bytesperline = bpl;
814 pix->plane_fmt[i].sizeimage = bpl * h * fmt->bpp[i] / 8;
824 static int jpu_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
826 struct jpu_ctx *ctx = fh_to_ctx(priv);
828 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type))
831 return __jpu_try_fmt(ctx, NULL, &f->fmt.pix_mp, f->type);
834 static int jpu_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
836 struct vb2_queue *vq;
837 struct jpu_ctx *ctx = fh_to_ctx(priv);
838 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
839 struct jpu_fmt *fmtinfo;
840 struct jpu_q_data *q_data;
843 vq = v4l2_m2m_get_vq(m2m_ctx, f->type);
847 if (vb2_is_busy(vq)) {
848 v4l2_err(&ctx->jpu->v4l2_dev, "%s queue busy\n", __func__);
852 ret = __jpu_try_fmt(ctx, &fmtinfo, &f->fmt.pix_mp, f->type);
856 q_data = jpu_get_q_data(ctx, f->type);
858 q_data->format = f->fmt.pix_mp;
859 q_data->fmtinfo = fmtinfo;
864 static int jpu_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
866 struct jpu_q_data *q_data;
867 struct jpu_ctx *ctx = fh_to_ctx(priv);
869 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type))
872 q_data = jpu_get_q_data(ctx, f->type);
873 f->fmt.pix_mp = q_data->format;
881 static int jpu_s_ctrl(struct v4l2_ctrl *ctrl)
883 struct jpu_ctx *ctx = ctrl_to_ctx(ctrl);
886 spin_lock_irqsave(&ctx->jpu->lock, flags);
887 if (ctrl->id == V4L2_CID_JPEG_COMPRESSION_QUALITY)
888 ctx->compr_quality = ctrl->val;
889 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
894 static const struct v4l2_ctrl_ops jpu_ctrl_ops = {
895 .s_ctrl = jpu_s_ctrl,
898 static int jpu_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
900 struct jpu_ctx *ctx = fh_to_ctx(priv);
901 struct jpu_q_data *src_q_data, *dst_q_data, *orig, adj, *ref;
902 enum v4l2_buf_type adj_type;
904 src_q_data = jpu_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
905 dst_q_data = jpu_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
911 adj_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
916 adj_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
919 adj.format.width = ref->format.width;
920 adj.format.height = ref->format.height;
922 __jpu_try_fmt(ctx, NULL, &adj.format, adj_type);
924 if (adj.format.width != orig->format.width ||
925 adj.format.height != orig->format.height) {
926 dev_err(ctx->jpu->dev, "src and dst formats do not match.\n");
927 /* maybe we can return -EPIPE here? */
931 return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
934 static const struct v4l2_ioctl_ops jpu_ioctl_ops = {
935 .vidioc_querycap = jpu_querycap,
937 .vidioc_enum_fmt_vid_cap = jpu_enum_fmt_cap,
938 .vidioc_enum_fmt_vid_out = jpu_enum_fmt_out,
939 .vidioc_g_fmt_vid_cap_mplane = jpu_g_fmt,
940 .vidioc_g_fmt_vid_out_mplane = jpu_g_fmt,
941 .vidioc_try_fmt_vid_cap_mplane = jpu_try_fmt,
942 .vidioc_try_fmt_vid_out_mplane = jpu_try_fmt,
943 .vidioc_s_fmt_vid_cap_mplane = jpu_s_fmt,
944 .vidioc_s_fmt_vid_out_mplane = jpu_s_fmt,
946 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
947 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
948 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
949 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
950 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
951 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
953 .vidioc_streamon = jpu_streamon,
954 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
956 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
957 .vidioc_unsubscribe_event = v4l2_event_unsubscribe
960 static int jpu_controls_create(struct jpu_ctx *ctx)
962 struct v4l2_ctrl *ctrl;
965 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 1);
967 ctrl = v4l2_ctrl_new_std(&ctx->ctrl_handler, &jpu_ctrl_ops,
968 V4L2_CID_JPEG_COMPRESSION_QUALITY,
969 0, JPU_MAX_QUALITY - 1, 1, 0);
971 if (ctx->ctrl_handler.error) {
972 ret = ctx->ctrl_handler.error;
977 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE |
978 V4L2_CTRL_FLAG_READ_ONLY;
980 ret = v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
987 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
992 * ============================================================================
994 * ============================================================================
996 static int jpu_queue_setup(struct vb2_queue *vq,
997 unsigned int *nbuffers, unsigned int *nplanes,
998 unsigned int sizes[], struct device *alloc_devs[])
1000 struct jpu_ctx *ctx = vb2_get_drv_priv(vq);
1001 struct jpu_q_data *q_data;
1004 q_data = jpu_get_q_data(ctx, vq->type);
1007 if (*nplanes != q_data->format.num_planes)
1010 for (i = 0; i < *nplanes; i++) {
1011 unsigned int q_size = q_data->format.plane_fmt[i].sizeimage;
1013 if (sizes[i] < q_size)
1019 *nplanes = q_data->format.num_planes;
1021 for (i = 0; i < *nplanes; i++)
1022 sizes[i] = q_data->format.plane_fmt[i].sizeimage;
1027 static int jpu_buf_prepare(struct vb2_buffer *vb)
1029 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1030 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1031 struct jpu_q_data *q_data;
1034 q_data = jpu_get_q_data(ctx, vb->vb2_queue->type);
1036 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1037 if (vbuf->field == V4L2_FIELD_ANY)
1038 vbuf->field = V4L2_FIELD_NONE;
1039 if (vbuf->field != V4L2_FIELD_NONE) {
1040 dev_err(ctx->jpu->dev, "%s field isn't supported\n",
1046 for (i = 0; i < q_data->format.num_planes; i++) {
1047 unsigned long size = q_data->format.plane_fmt[i].sizeimage;
1049 if (vb2_plane_size(vb, i) < size) {
1050 dev_err(ctx->jpu->dev,
1051 "%s: data will not fit into plane (%lu < %lu)\n",
1052 __func__, vb2_plane_size(vb, i), size);
1056 /* decoder capture queue */
1057 if (!ctx->encoder && V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type))
1058 vb2_set_plane_payload(vb, i, size);
1064 static void jpu_buf_queue(struct vb2_buffer *vb)
1066 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1067 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1069 if (!ctx->encoder && V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1070 struct jpu_buffer *jpu_buf = vb2_to_jpu_buffer(vbuf);
1071 struct jpu_q_data *q_data, adjust;
1072 void *buffer = vb2_plane_vaddr(vb, 0);
1073 unsigned long buf_size = vb2_get_plane_payload(vb, 0);
1074 unsigned int width, height;
1076 u8 subsampling = jpu_parse_hdr(buffer, buf_size, &width,
1079 /* check if JPEG data basic parsing was successful */
1080 if (subsampling != JPU_JPEG_422 && subsampling != JPU_JPEG_420)
1083 q_data = &ctx->out_q;
1086 adjust.format.width = width;
1087 adjust.format.height = height;
1089 __jpu_try_fmt(ctx, &adjust.fmtinfo, &adjust.format,
1090 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1092 if (adjust.format.width != q_data->format.width ||
1093 adjust.format.height != q_data->format.height)
1097 * keep subsampling in buffer to check it
1098 * for compatibility in device_run
1100 jpu_buf->subsampling = subsampling;
1103 if (ctx->fh.m2m_ctx)
1104 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1109 dev_err(ctx->jpu->dev, "incompatible or corrupted JPEG data\n");
1110 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1113 static void jpu_buf_finish(struct vb2_buffer *vb)
1115 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1116 struct jpu_buffer *jpu_buf = vb2_to_jpu_buffer(vbuf);
1117 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1118 struct jpu_q_data *q_data = &ctx->out_q;
1119 enum v4l2_buf_type type = vb->vb2_queue->type;
1122 if (vb->state == VB2_BUF_STATE_DONE)
1123 vbuf->sequence = jpu_get_q_data(ctx, type)->sequence++;
1125 if (!ctx->encoder || vb->state != VB2_BUF_STATE_DONE ||
1126 V4L2_TYPE_IS_OUTPUT(type))
1129 buffer = vb2_plane_vaddr(vb, 0);
1131 memcpy(buffer, jpeg_hdrs[jpu_buf->compr_quality], JPU_JPEG_HDR_SIZE);
1132 *(__be16 *)(buffer + JPU_JPEG_HEIGHT_OFFSET) =
1133 cpu_to_be16(q_data->format.height);
1134 *(__be16 *)(buffer + JPU_JPEG_WIDTH_OFFSET) =
1135 cpu_to_be16(q_data->format.width);
1136 *(buffer + JPU_JPEG_SUBS_OFFSET) = q_data->fmtinfo->subsampling;
1139 static int jpu_start_streaming(struct vb2_queue *vq, unsigned count)
1141 struct jpu_ctx *ctx = vb2_get_drv_priv(vq);
1142 struct jpu_q_data *q_data = jpu_get_q_data(ctx, vq->type);
1144 q_data->sequence = 0;
1148 static void jpu_stop_streaming(struct vb2_queue *vq)
1150 struct jpu_ctx *ctx = vb2_get_drv_priv(vq);
1151 struct vb2_v4l2_buffer *vb;
1152 unsigned long flags;
1155 if (V4L2_TYPE_IS_OUTPUT(vq->type))
1156 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1158 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1161 spin_lock_irqsave(&ctx->jpu->lock, flags);
1162 v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
1163 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1167 static const struct vb2_ops jpu_qops = {
1168 .queue_setup = jpu_queue_setup,
1169 .buf_prepare = jpu_buf_prepare,
1170 .buf_queue = jpu_buf_queue,
1171 .buf_finish = jpu_buf_finish,
1172 .start_streaming = jpu_start_streaming,
1173 .stop_streaming = jpu_stop_streaming,
1174 .wait_prepare = vb2_ops_wait_prepare,
1175 .wait_finish = vb2_ops_wait_finish,
1178 static int jpu_queue_init(void *priv, struct vb2_queue *src_vq,
1179 struct vb2_queue *dst_vq)
1181 struct jpu_ctx *ctx = priv;
1184 memset(src_vq, 0, sizeof(*src_vq));
1185 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1186 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1187 src_vq->drv_priv = ctx;
1188 src_vq->buf_struct_size = sizeof(struct jpu_buffer);
1189 src_vq->ops = &jpu_qops;
1190 src_vq->mem_ops = &vb2_dma_contig_memops;
1191 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1192 src_vq->lock = &ctx->jpu->mutex;
1193 src_vq->dev = ctx->jpu->v4l2_dev.dev;
1195 ret = vb2_queue_init(src_vq);
1199 memset(dst_vq, 0, sizeof(*dst_vq));
1200 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1201 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1202 dst_vq->drv_priv = ctx;
1203 dst_vq->buf_struct_size = sizeof(struct jpu_buffer);
1204 dst_vq->ops = &jpu_qops;
1205 dst_vq->mem_ops = &vb2_dma_contig_memops;
1206 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1207 dst_vq->lock = &ctx->jpu->mutex;
1208 dst_vq->dev = ctx->jpu->v4l2_dev.dev;
1210 return vb2_queue_init(dst_vq);
1214 * ============================================================================
1215 * Device file operations
1216 * ============================================================================
1218 static int jpu_open(struct file *file)
1220 struct jpu *jpu = video_drvdata(file);
1221 struct video_device *vfd = video_devdata(file);
1222 struct jpu_ctx *ctx;
1225 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1229 v4l2_fh_init(&ctx->fh, vfd);
1230 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1231 file->private_data = &ctx->fh;
1232 v4l2_fh_add(&ctx->fh);
1235 ctx->encoder = vfd == &jpu->vfd_encoder;
1237 __jpu_try_fmt(ctx, &ctx->out_q.fmtinfo, &ctx->out_q.format,
1238 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1239 __jpu_try_fmt(ctx, &ctx->cap_q.fmtinfo, &ctx->cap_q.format,
1240 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
1242 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpu->m2m_dev, ctx, jpu_queue_init);
1243 if (IS_ERR(ctx->fh.m2m_ctx)) {
1244 ret = PTR_ERR(ctx->fh.m2m_ctx);
1245 goto v4l_prepare_rollback;
1248 ret = jpu_controls_create(ctx);
1250 goto v4l_prepare_rollback;
1252 if (mutex_lock_interruptible(&jpu->mutex)) {
1254 goto v4l_prepare_rollback;
1257 if (jpu->ref_count == 0) {
1258 ret = clk_prepare_enable(jpu->clk);
1260 goto device_prepare_rollback;
1261 /* ...issue software reset */
1262 ret = jpu_reset(jpu);
1264 goto jpu_reset_rollback;
1269 mutex_unlock(&jpu->mutex);
1273 clk_disable_unprepare(jpu->clk);
1274 device_prepare_rollback:
1275 mutex_unlock(&jpu->mutex);
1276 v4l_prepare_rollback:
1277 v4l2_fh_del(&ctx->fh);
1278 v4l2_fh_exit(&ctx->fh);
1283 static int jpu_release(struct file *file)
1285 struct jpu *jpu = video_drvdata(file);
1286 struct jpu_ctx *ctx = fh_to_ctx(file->private_data);
1288 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
1289 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1290 v4l2_fh_del(&ctx->fh);
1291 v4l2_fh_exit(&ctx->fh);
1294 mutex_lock(&jpu->mutex);
1295 if (--jpu->ref_count == 0)
1296 clk_disable_unprepare(jpu->clk);
1297 mutex_unlock(&jpu->mutex);
1302 static const struct v4l2_file_operations jpu_fops = {
1303 .owner = THIS_MODULE,
1305 .release = jpu_release,
1306 .unlocked_ioctl = video_ioctl2,
1307 .poll = v4l2_m2m_fop_poll,
1308 .mmap = v4l2_m2m_fop_mmap,
1312 * ============================================================================
1314 * ============================================================================
1316 static void jpu_cleanup(struct jpu_ctx *ctx, bool reset)
1318 /* remove current buffers and finish job */
1319 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1320 unsigned long flags;
1322 spin_lock_irqsave(&ctx->jpu->lock, flags);
1324 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1325 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1327 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
1328 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);
1330 /* ...and give it a chance on next run */
1332 jpu_write(ctx->jpu, JCCMD_SRST, JCCMD);
1334 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1336 v4l2_m2m_job_finish(ctx->jpu->m2m_dev, ctx->fh.m2m_ctx);
1339 static void jpu_device_run(void *priv)
1341 struct jpu_ctx *ctx = priv;
1342 struct jpu *jpu = ctx->jpu;
1343 struct jpu_buffer *jpu_buf;
1344 struct jpu_q_data *q_data;
1345 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1346 unsigned int w, h, bpl;
1347 unsigned char num_planes, subsampling;
1348 unsigned long flags;
1350 /* ...wait until module reset completes; we have mutex locked here */
1351 if (jpu_wait_reset(jpu)) {
1352 jpu_cleanup(ctx, true);
1356 spin_lock_irqsave(&ctx->jpu->lock, flags);
1360 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1361 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1364 jpu_buf = vb2_to_jpu_buffer(dst_buf);
1365 q_data = &ctx->out_q;
1367 jpu_buf = vb2_to_jpu_buffer(src_buf);
1368 q_data = &ctx->cap_q;
1371 w = q_data->format.width;
1372 h = q_data->format.height;
1373 bpl = q_data->format.plane_fmt[0].bytesperline;
1374 num_planes = q_data->fmtinfo->num_planes;
1375 subsampling = q_data->fmtinfo->subsampling;
1378 unsigned long src_1_addr, src_2_addr, dst_addr;
1379 unsigned int redu, inft;
1381 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1383 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
1385 src_2_addr = vb2_dma_contig_plane_dma_addr(
1386 &src_buf->vb2_buf, 1);
1388 src_2_addr = src_1_addr + w * h;
1390 jpu_buf->compr_quality = ctx->compr_quality;
1392 if (subsampling == JPU_JPEG_420) {
1393 redu = JCMOD_REDU_420;
1394 inft = JIFECNT_INFT_420;
1396 redu = JCMOD_REDU_422;
1397 inft = JIFECNT_INFT_422;
1400 /* only no marker mode works for encoding */
1401 jpu_write(jpu, JCMOD_DSP_ENC | JCMOD_PCTR | redu |
1402 JCMOD_MSKIP_ENABLE, JCMOD);
1404 jpu_write(jpu, JIFECNT_SWAP_WB | inft, JIFECNT);
1405 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
1406 jpu_write(jpu, JINTE_TRANSF_COMPL, JINTE);
1408 /* Y and C components source addresses */
1409 jpu_write(jpu, src_1_addr, JIFESYA1);
1410 jpu_write(jpu, src_2_addr, JIFESCA1);
1413 jpu_write(jpu, bpl, JIFESMW);
1415 jpu_write(jpu, (w >> 8) & JCSZ_MASK, JCHSZU);
1416 jpu_write(jpu, w & JCSZ_MASK, JCHSZD);
1418 jpu_write(jpu, (h >> 8) & JCSZ_MASK, JCVSZU);
1419 jpu_write(jpu, h & JCSZ_MASK, JCVSZD);
1421 jpu_write(jpu, w, JIFESHSZ);
1422 jpu_write(jpu, h, JIFESVSZ);
1424 jpu_write(jpu, dst_addr + JPU_JPEG_HDR_SIZE, JIFEDA1);
1426 jpu_write(jpu, 0 << JCQTN_SHIFT(1) | 1 << JCQTN_SHIFT(2) |
1427 1 << JCQTN_SHIFT(3), JCQTN);
1429 jpu_write(jpu, 0 << JCHTN_AC_SHIFT(1) | 0 << JCHTN_DC_SHIFT(1) |
1430 1 << JCHTN_AC_SHIFT(2) | 1 << JCHTN_DC_SHIFT(2) |
1431 1 << JCHTN_AC_SHIFT(3) | 1 << JCHTN_DC_SHIFT(3),
1434 jpu_set_qtbl(jpu, ctx->compr_quality);
1437 unsigned long src_addr, dst_1_addr, dst_2_addr;
1439 if (jpu_buf->subsampling != subsampling) {
1440 dev_err(ctx->jpu->dev,
1441 "src and dst formats do not match.\n");
1442 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1443 jpu_cleanup(ctx, false);
1447 src_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
1449 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1450 if (q_data->fmtinfo->num_planes > 1)
1451 dst_2_addr = vb2_dma_contig_plane_dma_addr(
1452 &dst_buf->vb2_buf, 1);
1454 dst_2_addr = dst_1_addr + w * h;
1456 /* ...set up decoder operation */
1457 jpu_write(jpu, JCMOD_DSP_DEC | JCMOD_PCTR, JCMOD);
1458 jpu_write(jpu, JIFECNT_SWAP_WB, JIFECNT);
1459 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
1461 /* ...enable interrupts on transfer completion and d-g error */
1462 jpu_write(jpu, JINTE_TRANSF_COMPL | JINTE_ERR, JINTE);
1464 /* ...set source/destination addresses of encoded data */
1465 jpu_write(jpu, src_addr, JIFDSA1);
1466 jpu_write(jpu, dst_1_addr, JIFDDYA1);
1467 jpu_write(jpu, dst_2_addr, JIFDDCA1);
1469 jpu_write(jpu, bpl, JIFDDMW);
1472 /* ...start encoder/decoder operation */
1473 jpu_write(jpu, JCCMD_JSRT, JCCMD);
1475 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1478 static const struct v4l2_m2m_ops jpu_m2m_ops = {
1479 .device_run = jpu_device_run,
1483 * ============================================================================
1485 * ============================================================================
1487 static irqreturn_t jpu_irq_handler(int irq, void *dev_id)
1489 struct jpu *jpu = dev_id;
1490 struct jpu_ctx *curr_ctx;
1491 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1492 unsigned int int_status;
1494 int_status = jpu_read(jpu, JINTS);
1496 /* ...spurious interrupt */
1497 if (!((JINTS_TRANSF_COMPL | JINTS_PROCESS_COMPL | JINTS_ERR) &
1501 /* ...clear interrupts */
1502 jpu_write(jpu, ~(int_status & JINTS_MASK), JINTS);
1503 if (int_status & (JINTS_ERR | JINTS_PROCESS_COMPL))
1504 jpu_write(jpu, JCCMD_JEND, JCCMD);
1506 spin_lock(&jpu->lock);
1508 if ((int_status & JINTS_PROCESS_COMPL) &&
1509 !(int_status & JINTS_TRANSF_COMPL))
1512 curr_ctx = v4l2_m2m_get_curr_priv(jpu->m2m_dev);
1514 /* ...instance is not running */
1515 dev_err(jpu->dev, "no active context for m2m\n");
1519 src_buf = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
1520 dst_buf = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
1522 if (int_status & JINTS_TRANSF_COMPL) {
1523 if (curr_ctx->encoder) {
1524 unsigned long payload_size = jpu_read(jpu, JCDTCU) << 16
1525 | jpu_read(jpu, JCDTCM) << 8
1526 | jpu_read(jpu, JCDTCD);
1527 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
1528 payload_size + JPU_JPEG_HDR_SIZE);
1531 dst_buf->field = src_buf->field;
1532 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
1533 if (src_buf->flags & V4L2_BUF_FLAG_TIMECODE)
1534 dst_buf->timecode = src_buf->timecode;
1535 dst_buf->flags = src_buf->flags &
1536 (V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_KEYFRAME |
1537 V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME |
1538 V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
1540 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1541 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1542 } else if (int_status & JINTS_ERR) {
1543 unsigned char error = jpu_read(jpu, JCDERR) & JCDERR_MASK;
1545 dev_dbg(jpu->dev, "processing error: %#X: %s\n", error,
1546 error_to_text[error]);
1548 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
1549 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);
1554 /* ...reset JPU after completion */
1555 jpu_write(jpu, JCCMD_SRST, JCCMD);
1556 spin_unlock(&jpu->lock);
1558 v4l2_m2m_job_finish(jpu->m2m_dev, curr_ctx->fh.m2m_ctx);
1563 spin_unlock(&jpu->lock);
1568 * ============================================================================
1569 * Driver basic infrastructure
1570 * ============================================================================
1572 static const struct of_device_id jpu_dt_ids[] = {
1573 { .compatible = "renesas,jpu-r8a7790" }, /* H2 */
1574 { .compatible = "renesas,jpu-r8a7791" }, /* M2-W */
1575 { .compatible = "renesas,jpu-r8a7792" }, /* V2H */
1576 { .compatible = "renesas,jpu-r8a7793" }, /* M2-N */
1577 { .compatible = "renesas,rcar-gen2-jpu" },
1580 MODULE_DEVICE_TABLE(of, jpu_dt_ids);
1582 static int jpu_probe(struct platform_device *pdev)
1588 jpu = devm_kzalloc(&pdev->dev, sizeof(*jpu), GFP_KERNEL);
1592 mutex_init(&jpu->mutex);
1593 spin_lock_init(&jpu->lock);
1594 jpu->dev = &pdev->dev;
1596 /* memory-mapped registers */
1597 jpu->regs = devm_platform_ioremap_resource(pdev, 0);
1598 if (IS_ERR(jpu->regs))
1599 return PTR_ERR(jpu->regs);
1601 /* interrupt service routine registration */
1602 jpu->irq = ret = platform_get_irq(pdev, 0);
1606 ret = devm_request_irq(&pdev->dev, jpu->irq, jpu_irq_handler, 0,
1607 dev_name(&pdev->dev), jpu);
1609 dev_err(&pdev->dev, "cannot claim IRQ %d\n", jpu->irq);
1614 jpu->clk = devm_clk_get(&pdev->dev, NULL);
1615 if (IS_ERR(jpu->clk)) {
1616 dev_err(&pdev->dev, "cannot get clock\n");
1617 return PTR_ERR(jpu->clk);
1621 ret = v4l2_device_register(&pdev->dev, &jpu->v4l2_dev);
1623 dev_err(&pdev->dev, "Failed to register v4l2 device\n");
1627 /* mem2mem device */
1628 jpu->m2m_dev = v4l2_m2m_init(&jpu_m2m_ops);
1629 if (IS_ERR(jpu->m2m_dev)) {
1630 v4l2_err(&jpu->v4l2_dev, "Failed to init mem2mem device\n");
1631 ret = PTR_ERR(jpu->m2m_dev);
1632 goto device_register_rollback;
1635 /* fill in quantization and Huffman tables for encoder */
1636 for (i = 0; i < JPU_MAX_QUALITY; i++)
1637 jpu_generate_hdr(i, (unsigned char *)jpeg_hdrs[i]);
1639 strscpy(jpu->vfd_encoder.name, DRV_NAME, sizeof(jpu->vfd_encoder.name));
1640 jpu->vfd_encoder.fops = &jpu_fops;
1641 jpu->vfd_encoder.ioctl_ops = &jpu_ioctl_ops;
1642 jpu->vfd_encoder.minor = -1;
1643 jpu->vfd_encoder.release = video_device_release_empty;
1644 jpu->vfd_encoder.lock = &jpu->mutex;
1645 jpu->vfd_encoder.v4l2_dev = &jpu->v4l2_dev;
1646 jpu->vfd_encoder.vfl_dir = VFL_DIR_M2M;
1647 jpu->vfd_encoder.device_caps = V4L2_CAP_STREAMING |
1648 V4L2_CAP_VIDEO_M2M_MPLANE;
1650 ret = video_register_device(&jpu->vfd_encoder, VFL_TYPE_VIDEO, -1);
1652 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
1653 goto m2m_init_rollback;
1656 video_set_drvdata(&jpu->vfd_encoder, jpu);
1658 strscpy(jpu->vfd_decoder.name, DRV_NAME, sizeof(jpu->vfd_decoder.name));
1659 jpu->vfd_decoder.fops = &jpu_fops;
1660 jpu->vfd_decoder.ioctl_ops = &jpu_ioctl_ops;
1661 jpu->vfd_decoder.minor = -1;
1662 jpu->vfd_decoder.release = video_device_release_empty;
1663 jpu->vfd_decoder.lock = &jpu->mutex;
1664 jpu->vfd_decoder.v4l2_dev = &jpu->v4l2_dev;
1665 jpu->vfd_decoder.vfl_dir = VFL_DIR_M2M;
1666 jpu->vfd_decoder.device_caps = V4L2_CAP_STREAMING |
1667 V4L2_CAP_VIDEO_M2M_MPLANE;
1669 ret = video_register_device(&jpu->vfd_decoder, VFL_TYPE_VIDEO, -1);
1671 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
1672 goto enc_vdev_register_rollback;
1675 video_set_drvdata(&jpu->vfd_decoder, jpu);
1676 platform_set_drvdata(pdev, jpu);
1678 v4l2_info(&jpu->v4l2_dev, "encoder device registered as /dev/video%d\n",
1679 jpu->vfd_encoder.num);
1680 v4l2_info(&jpu->v4l2_dev, "decoder device registered as /dev/video%d\n",
1681 jpu->vfd_decoder.num);
1685 enc_vdev_register_rollback:
1686 video_unregister_device(&jpu->vfd_encoder);
1689 v4l2_m2m_release(jpu->m2m_dev);
1691 device_register_rollback:
1692 v4l2_device_unregister(&jpu->v4l2_dev);
1697 static void jpu_remove(struct platform_device *pdev)
1699 struct jpu *jpu = platform_get_drvdata(pdev);
1701 video_unregister_device(&jpu->vfd_decoder);
1702 video_unregister_device(&jpu->vfd_encoder);
1703 v4l2_m2m_release(jpu->m2m_dev);
1704 v4l2_device_unregister(&jpu->v4l2_dev);
1707 #ifdef CONFIG_PM_SLEEP
1708 static int jpu_suspend(struct device *dev)
1710 struct jpu *jpu = dev_get_drvdata(dev);
1712 if (jpu->ref_count == 0)
1715 clk_disable_unprepare(jpu->clk);
1720 static int jpu_resume(struct device *dev)
1722 struct jpu *jpu = dev_get_drvdata(dev);
1724 if (jpu->ref_count == 0)
1727 clk_prepare_enable(jpu->clk);
1733 static const struct dev_pm_ops jpu_pm_ops = {
1734 SET_SYSTEM_SLEEP_PM_OPS(jpu_suspend, jpu_resume)
1737 static struct platform_driver jpu_driver = {
1739 .remove_new = jpu_remove,
1741 .of_match_table = jpu_dt_ids,
1747 module_platform_driver(jpu_driver);
1749 MODULE_ALIAS("platform:" DRV_NAME);
1750 MODULE_AUTHOR("Mikhail Ulianov <mikhail.ulyanov@cogentembedded.com>");
1751 MODULE_DESCRIPTION("Renesas R-Car JPEG processing unit driver");
1752 MODULE_LICENSE("GPL v2");