drivers/media/platform/qcom/camss/camss.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * camss.c
   4  *
   5  * Qualcomm MSM Camera Subsystem - Core
   6  *
   7  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   8  * Copyright (C) 2015-2018 Linaro Ltd.
   9  */
  10 #include <linux/clk.h>
  11 #include <linux/interconnect.h>
  12 #include <linux/media-bus-format.h>
  13 #include <linux/media.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/slab.h>
  22 #include <linux/videodev2.h>
  23
  24 #include <media/media-device.h>
  25 #include <media/v4l2-async.h>
  26 #include <media/v4l2-device.h>
  27 #include <media/v4l2-mc.h>
  28 #include <media/v4l2-fwnode.h>
  29
  30 #include "camss.h"
  31
  32 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105
  33 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
  34
  35 static const struct camss_subdev_resources csiphy_res_8x16[] = {
  36         /* CSIPHY0 */
  37         {
  38                 .regulators = {},
  39                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
  40                 .clock_rate = { { 0 },
  41                                 { 0 },
  42                                 { 0 },
  43                                 { 100000000, 200000000 } },
  44                 .reg = { "csiphy0", "csiphy0_clk_mux" },
  45                 .interrupt = { "csiphy0" },
  46                 .ops = &csiphy_ops_2ph_1_0
  47         },
  48
  49         /* CSIPHY1 */
  50         {
  51                 .regulators = {},
  52                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
  53                 .clock_rate = { { 0 },
  54                                 { 0 },
  55                                 { 0 },
  56                                 { 100000000, 200000000 } },
  57                 .reg = { "csiphy1", "csiphy1_clk_mux" },
  58                 .interrupt = { "csiphy1" },
  59                 .ops = &csiphy_ops_2ph_1_0
  60         }
  61 };
  62
  63 static const struct camss_subdev_resources csid_res_8x16[] = {
  64         /* CSID0 */
  65         {
  66                 .regulators = { "vdda" },
  67                 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
  68                            "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
  69                 .clock_rate = { { 0 },
  70                                 { 0 },
  71                                 { 0 },
  72                                 { 0 },
  73                                 { 100000000, 200000000 },
  74                                 { 0 },
  75                                 { 0 },
  76                                 { 0 } },
  77                 .reg = { "csid0" },
  78                 .interrupt = { "csid0" },
  79                 .ops = &csid_ops_4_1,
  80         },
  81
  82         /* CSID1 */
  83         {
  84                 .regulators = { "vdda" },
  85                 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
  86                            "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
  87                 .clock_rate = { { 0 },
  88                                 { 0 },
  89                                 { 0 },
  90                                 { 0 },
  91                                 { 100000000, 200000000 },
  92                                 { 0 },
  93                                 { 0 },
  94                                 { 0 } },
  95                 .reg = { "csid1" },
  96                 .interrupt = { "csid1" },
  97                 .ops = &csid_ops_4_1,
  98         },
  99 };
 100
 101 static const struct camss_subdev_resources ispif_res_8x16 = {
 102         /* ISPIF */
 103         .clock = { "top_ahb", "ahb", "ispif_ahb",
 104                    "csi0", "csi0_pix", "csi0_rdi",
 105                    "csi1", "csi1_pix", "csi1_rdi" },
 106         .clock_for_reset = { "vfe0", "csi_vfe0" },
 107         .reg = { "ispif", "csi_clk_mux" },
 108         .interrupt = { "ispif" }
 109
 110 };
 111
 112 static const struct camss_subdev_resources vfe_res_8x16[] = {
 113         /* VFE0 */
 114         {
 115                 .regulators = {},
 116                 .clock = { "top_ahb", "vfe0", "csi_vfe0",
 117                            "vfe_ahb", "vfe_axi", "ahb" },
 118                 .clock_rate = { { 0 },
 119                                 { 50000000, 80000000, 100000000, 160000000,
 120                                   177780000, 200000000, 266670000, 320000000,
 121                                   400000000, 465000000 },
 122                                 { 0 },
 123                                 { 0 },
 124                                 { 0 },
 125                                 { 0 },
 126                                 { 0 },
 127                                 { 0 },
 128                                 { 0 } },
 129                 .reg = { "vfe0" },
 130                 .interrupt = { "vfe0" },
 131                 .line_num = 3,
 132                 .ops = &vfe_ops_4_1
 133         }
 134 };
 135
 136 static const struct camss_subdev_resources csiphy_res_8x96[] = {
 137         /* CSIPHY0 */
 138         {
 139                 .regulators = {},
 140                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
 141                 .clock_rate = { { 0 },
 142                                 { 0 },
 143                                 { 0 },
 144                                 { 100000000, 200000000, 266666667 } },
 145                 .reg = { "csiphy0", "csiphy0_clk_mux" },
 146                 .interrupt = { "csiphy0" },
 147                 .ops = &csiphy_ops_3ph_1_0
 148         },
 149
 150         /* CSIPHY1 */
 151         {
 152                 .regulators = {},
 153                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
 154                 .clock_rate = { { 0 },
 155                                 { 0 },
 156                                 { 0 },
 157                                 { 100000000, 200000000, 266666667 } },
 158                 .reg = { "csiphy1", "csiphy1_clk_mux" },
 159                 .interrupt = { "csiphy1" },
 160                 .ops = &csiphy_ops_3ph_1_0
 161         },
 162
 163         /* CSIPHY2 */
 164         {
 165                 .regulators = {},
 166                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
 167                 .clock_rate = { { 0 },
 168                                 { 0 },
 169                                 { 0 },
 170                                 { 100000000, 200000000, 266666667 } },
 171                 .reg = { "csiphy2", "csiphy2_clk_mux" },
 172                 .interrupt = { "csiphy2" },
 173                 .ops = &csiphy_ops_3ph_1_0
 174         }
 175 };
 176
 177 static const struct camss_subdev_resources csid_res_8x96[] = {
 178         /* CSID0 */
 179         {
 180                 .regulators = { "vdda" },
 181                 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
 182                            "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
 183                 .clock_rate = { { 0 },
 184                                 { 0 },
 185                                 { 0 },
 186                                 { 0 },
 187                                 { 100000000, 200000000, 266666667 },
 188                                 { 0 },
 189                                 { 0 },
 190                                 { 0 } },
 191                 .reg = { "csid0" },
 192                 .interrupt = { "csid0" },
 193                 .ops = &csid_ops_4_7,
 194         },
 195
 196         /* CSID1 */
 197         {
 198                 .regulators = { "vdda" },
 199                 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 200                            "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
 201                 .clock_rate = { { 0 },
 202                                 { 0 },
 203                                 { 0 },
 204                                 { 0 },
 205                                 { 100000000, 200000000, 266666667 },
 206                                 { 0 },
 207                                 { 0 },
 208                                 { 0 } },
 209                 .reg = { "csid1" },
 210                 .interrupt = { "csid1" },
 211                 .ops = &csid_ops_4_7,
 212         },
 213
 214         /* CSID2 */
 215         {
 216                 .regulators = { "vdda" },
 217                 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
 218                            "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
 219                 .clock_rate = { { 0 },
 220                                 { 0 },
 221                                 { 0 },
 222                                 { 0 },
 223                                 { 100000000, 200000000, 266666667 },
 224                                 { 0 },
 225                                 { 0 },
 226                                 { 0 } },
 227                 .reg = { "csid2" },
 228                 .interrupt = { "csid2" },
 229                 .ops = &csid_ops_4_7,
 230         },
 231
 232         /* CSID3 */
 233         {
 234                 .regulators = { "vdda" },
 235                 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
 236                            "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" },
 237                 .clock_rate = { { 0 },
 238                                 { 0 },
 239                                 { 0 },
 240                                 { 0 },
 241                                 { 100000000, 200000000, 266666667 },
 242                                 { 0 },
 243                                 { 0 },
 244                                 { 0 } },
 245                 .reg = { "csid3" },
 246                 .interrupt = { "csid3" },
 247                 .ops = &csid_ops_4_7,
 248         }
 249 };
 250
 251 static const struct camss_subdev_resources ispif_res_8x96 = {
 252         /* ISPIF */
 253         .clock = { "top_ahb", "ahb", "ispif_ahb",
 254                    "csi0", "csi0_pix", "csi0_rdi",
 255                    "csi1", "csi1_pix", "csi1_rdi",
 256                    "csi2", "csi2_pix", "csi2_rdi",
 257                    "csi3", "csi3_pix", "csi3_rdi" },
 258         .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
 259         .reg = { "ispif", "csi_clk_mux" },
 260         .interrupt = { "ispif" }
 261 };
 262
 263 static const struct camss_subdev_resources vfe_res_8x96[] = {
 264         /* VFE0 */
 265         {
 266                 .regulators = {},
 267                 .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb",
 268                            "vfe0_ahb", "vfe_axi", "vfe0_stream"},
 269                 .clock_rate = { { 0 },
 270                                 { 0 },
 271                                 { 75000000, 100000000, 300000000,
 272                                   320000000, 480000000, 600000000 },
 273                                 { 0 },
 274                                 { 0 },
 275                                 { 0 },
 276                                 { 0 },
 277                                 { 0 } },
 278                 .reg = { "vfe0" },
 279                 .interrupt = { "vfe0" },
 280                 .line_num = 3,
 281                 .ops = &vfe_ops_4_7
 282         },
 283
 284         /* VFE1 */
 285         {
 286                 .regulators = {},
 287                 .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb",
 288                            "vfe1_ahb", "vfe_axi", "vfe1_stream"},
 289                 .clock_rate = { { 0 },
 290                                 { 0 },
 291                                 { 75000000, 100000000, 300000000,
 292                                   320000000, 480000000, 600000000 },
 293                                 { 0 },
 294                                 { 0 },
 295                                 { 0 },
 296                                 { 0 },
 297                                 { 0 } },
 298                 .reg = { "vfe1" },
 299                 .interrupt = { "vfe1" },
 300                 .line_num = 3,
 301                 .ops = &vfe_ops_4_7
 302         }
 303 };
 304
 305 static const struct camss_subdev_resources csiphy_res_660[] = {
 306         /* CSIPHY0 */
 307         {
 308                 .regulators = {},
 309                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer",
 310                            "csi0_phy", "csiphy_ahb2crif" },
 311                 .clock_rate = { { 0 },
 312                                 { 0 },
 313                                 { 0 },
 314                                 { 100000000, 200000000, 269333333 },
 315                                 { 0 } },
 316                 .reg = { "csiphy0", "csiphy0_clk_mux" },
 317                 .interrupt = { "csiphy0" },
 318                 .ops = &csiphy_ops_3ph_1_0
 319         },
 320
 321         /* CSIPHY1 */
 322         {
 323                 .regulators = {},
 324                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer",
 325                            "csi1_phy", "csiphy_ahb2crif" },
 326                 .clock_rate = { { 0 },
 327                                 { 0 },
 328                                 { 0 },
 329                                 { 100000000, 200000000, 269333333 },
 330                                 { 0 } },
 331                 .reg = { "csiphy1", "csiphy1_clk_mux" },
 332                 .interrupt = { "csiphy1" },
 333                 .ops = &csiphy_ops_3ph_1_0
 334         },
 335
 336         /* CSIPHY2 */
 337         {
 338                 .regulators = {},
 339                 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer",
 340                            "csi2_phy", "csiphy_ahb2crif" },
 341                 .clock_rate = { { 0 },
 342                                 { 0 },
 343                                 { 0 },
 344                                 { 100000000, 200000000, 269333333 },
 345                                 { 0 } },
 346                 .reg = { "csiphy2", "csiphy2_clk_mux" },
 347                 .interrupt = { "csiphy2" },
 348                 .ops = &csiphy_ops_3ph_1_0
 349         }
 350 };
 351
 352 static const struct camss_subdev_resources csid_res_660[] = {
 353         /* CSID0 */
 354         {
 355                 .regulators = { "vdda", "vdd_sec" },
 356                 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
 357                            "csi0", "csi0_phy", "csi0_pix", "csi0_rdi",
 358                            "cphy_csid0" },
 359                 .clock_rate = { { 0 },
 360                                 { 0 },
 361                                 { 0 },
 362                                 { 0 },
 363                                 { 100000000, 200000000, 310000000,
 364                                   404000000, 465000000 },
 365                                 { 0 },
 366                                 { 0 },
 367                                 { 0 },
 368                                 { 0 } },
 369                 .reg = { "csid0" },
 370                 .interrupt = { "csid0" },
 371                 .ops = &csid_ops_4_7,
 372         },
 373
 374         /* CSID1 */
 375         {
 376                 .regulators = { "vdda", "vdd_sec" },
 377                 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
 378                            "csi1", "csi1_phy", "csi1_pix", "csi1_rdi",
 379                            "cphy_csid1" },
 380                 .clock_rate = { { 0 },
 381                                 { 0 },
 382                                 { 0 },
 383                                 { 0 },
 384                                 { 100000000, 200000000, 310000000,
 385                                   404000000, 465000000 },
 386                                 { 0 },
 387                                 { 0 },
 388                                 { 0 },
 389                                 { 0 } },
 390                 .reg = { "csid1" },
 391                 .interrupt = { "csid1" },
 392                 .ops = &csid_ops_4_7,
 393         },
 394
 395         /* CSID2 */
 396         {
 397                 .regulators = { "vdda", "vdd_sec" },
 398                 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
 399                            "csi2", "csi2_phy", "csi2_pix", "csi2_rdi",
 400                            "cphy_csid2" },
 401                 .clock_rate = { { 0 },
 402                                 { 0 },
 403                                 { 0 },
 404                                 { 0 },
 405                                 { 100000000, 200000000, 310000000,
 406                                   404000000, 465000000 },
 407                                 { 0 },
 408                                 { 0 },
 409                                 { 0 },
 410                                 { 0 } },
 411                 .reg = { "csid2" },
 412                 .interrupt = { "csid2" },
 413                 .ops = &csid_ops_4_7,
 414         },
 415
 416         /* CSID3 */
 417         {
 418                 .regulators = { "vdda", "vdd_sec" },
 419                 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
 420                            "csi3", "csi3_phy", "csi3_pix", "csi3_rdi",
 421                            "cphy_csid3" },
 422                 .clock_rate = { { 0 },
 423                                 { 0 },
 424                                 { 0 },
 425                                 { 0 },
 426                                 { 100000000, 200000000, 310000000,
 427                                   404000000, 465000000 },
 428                                 { 0 },
 429                                 { 0 },
 430                                 { 0 },
 431                                 { 0 } },
 432                 .reg = { "csid3" },
 433                 .interrupt = { "csid3" },
 434                 .ops = &csid_ops_4_7,
 435         }
 436 };
 437
 438 static const struct camss_subdev_resources ispif_res_660 = {
 439         /* ISPIF */
 440         .clock = { "top_ahb", "ahb", "ispif_ahb",
 441                    "csi0", "csi0_pix", "csi0_rdi",
 442                    "csi1", "csi1_pix", "csi1_rdi",
 443                    "csi2", "csi2_pix", "csi2_rdi",
 444                    "csi3", "csi3_pix", "csi3_rdi" },
 445         .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
 446         .reg = { "ispif", "csi_clk_mux" },
 447         .interrupt = { "ispif" }
 448 };
 449
 450 static const struct camss_subdev_resources vfe_res_660[] = {
 451         /* VFE0 */
 452         {
 453                 .regulators = {},
 454                 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0",
 455                            "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi",
 456                            "vfe0_stream"},
 457                 .clock_rate = { { 0 },
 458                                 { 0 },
 459                                 { 0 },
 460                                 { 120000000, 200000000, 256000000,
 461                                   300000000, 404000000, 480000000,
 462                                   540000000, 576000000 },
 463                                 { 0 },
 464                                 { 0 },
 465                                 { 0 },
 466                                 { 0 },
 467                                 { 0 } },
 468                 .reg = { "vfe0" },
 469                 .interrupt = { "vfe0" },
 470                 .line_num = 3,
 471                 .ops = &vfe_ops_4_8
 472         },
 473
 474         /* VFE1 */
 475         {
 476                 .regulators = {},
 477                 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1",
 478                            "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi",
 479                            "vfe1_stream"},
 480                 .clock_rate = { { 0 },
 481                                 { 0 },
 482                                 { 0 },
 483                                 { 120000000, 200000000, 256000000,
 484                                   300000000, 404000000, 480000000,
 485                                   540000000, 576000000 },
 486                                 { 0 },
 487                                 { 0 },
 488                                 { 0 },
 489                                 { 0 },
 490                                 { 0 } },
 491                 .reg = { "vfe1" },
 492                 .interrupt = { "vfe1" },
 493                 .line_num = 3,
 494                 .ops = &vfe_ops_4_8
 495         }
 496 };
 497
 498 static const struct camss_subdev_resources csiphy_res_845[] = {
 499         /* CSIPHY0 */
 500         {
 501                 .regulators = {},
 502                 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
 503                                 "cpas_ahb", "cphy_rx_src", "csiphy0",
 504                                 "csiphy0_timer_src", "csiphy0_timer" },
 505                 .clock_rate = { { 0 },
 506                                 { 0 },
 507                                 { 0 },
 508                                 { 0 },
 509                                 { 0 },
 510                                 { 0 },
 511                                 { 0 },
 512                                 { 19200000, 240000000, 269333333 } },
 513                 .reg = { "csiphy0" },
 514                 .interrupt = { "csiphy0" },
 515                 .ops = &csiphy_ops_3ph_1_0
 516         },
 517
 518         /* CSIPHY1 */
 519         {
 520                 .regulators = {},
 521                 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
 522                                 "cpas_ahb", "cphy_rx_src", "csiphy1",
 523                                 "csiphy1_timer_src", "csiphy1_timer" },
 524                 .clock_rate = { { 0 },
 525                                 { 0 },
 526                                 { 0 },
 527                                 { 0 },
 528                                 { 0 },
 529                                 { 0 },
 530                                 { 0 },
 531                                 { 19200000, 240000000, 269333333 } },
 532                 .reg = { "csiphy1" },
 533                 .interrupt = { "csiphy1" },
 534                 .ops = &csiphy_ops_3ph_1_0
 535         },
 536
 537         /* CSIPHY2 */
 538         {
 539                 .regulators = {},
 540                 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
 541                                 "cpas_ahb", "cphy_rx_src", "csiphy2",
 542                                 "csiphy2_timer_src", "csiphy2_timer" },
 543                 .clock_rate = { { 0 },
 544                                 { 0 },
 545                                 { 0 },
 546                                 { 0 },
 547                                 { 0 },
 548                                 { 0 },
 549                                 { 0 },
 550                                 { 19200000, 240000000, 269333333 } },
 551                 .reg = { "csiphy2" },
 552                 .interrupt = { "csiphy2" },
 553                 .ops = &csiphy_ops_3ph_1_0
 554         },
 555
 556         /* CSIPHY3 */
 557         {
 558                 .regulators = {},
 559                 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
 560                                 "cpas_ahb", "cphy_rx_src", "csiphy3",
 561                                 "csiphy3_timer_src", "csiphy3_timer" },
 562                 .clock_rate = { { 0 },
 563                                 { 0 },
 564                                 { 0 },
 565                                 { 0 },
 566                                 { 0 },
 567                                 { 0 },
 568                                 { 0 },
 569                                 { 19200000, 240000000, 269333333 } },
 570                 .reg = { "csiphy3" },
 571                 .interrupt = { "csiphy3" },
 572                 .ops = &csiphy_ops_3ph_1_0
 573         }
 574 };
 575
 576 static const struct camss_subdev_resources csid_res_845[] = {
 577         /* CSID0 */
 578         {
 579                 .regulators = { "vdda-phy", "vdda-pll" },
 580                 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
 581                                 "soc_ahb", "vfe0", "vfe0_src",
 582                                 "vfe0_cphy_rx", "csi0",
 583                                 "csi0_src" },
 584                 .clock_rate = { { 0 },
 585                                 { 384000000 },
 586                                 { 80000000 },
 587                                 { 0 },
 588                                 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
 589                                 { 320000000 },
 590                                 { 0 },
 591                                 { 19200000, 75000000, 384000000, 538666667 },
 592                                 { 384000000 } },
 593                 .reg = { "csid0" },
 594                 .interrupt = { "csid0" },
 595                 .ops = &csid_ops_gen2
 596         },
 597
 598         /* CSID1 */
 599         {
 600                 .regulators = { "vdda-phy", "vdda-pll" },
 601                 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
 602                                 "soc_ahb", "vfe1", "vfe1_src",
 603                                 "vfe1_cphy_rx", "csi1",
 604                                 "csi1_src" },
 605                 .clock_rate = { { 0 },
 606                                 { 384000000 },
 607                                 { 80000000 },
 608                                 { 0 },
 609                                 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
 610                                 { 320000000 },
 611                                 { 0 },
 612                                 { 19200000, 75000000, 384000000, 538666667 },
 613                                 { 384000000 } },
 614                 .reg = { "csid1" },
 615                 .interrupt = { "csid1" },
 616                 .ops = &csid_ops_gen2
 617         },
 618
 619         /* CSID2 */
 620         {
 621                 .regulators = { "vdda-phy", "vdda-pll" },
 622                 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
 623                                 "soc_ahb", "vfe_lite", "vfe_lite_src",
 624                                 "vfe_lite_cphy_rx", "csi2",
 625                                 "csi2_src" },
 626                 .clock_rate = { { 0 },
 627                                 { 384000000 },
 628                                 { 80000000 },
 629                                 { 0 },
 630                                 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
 631                                 { 320000000 },
 632                                 { 0 },
 633                                 { 19200000, 75000000, 384000000, 538666667 },
 634                                 { 384000000 } },
 635                 .reg = { "csid2" },
 636                 .interrupt = { "csid2" },
 637                 .ops = &csid_ops_gen2
 638         }
 639 };
 640
 641 static const struct camss_subdev_resources vfe_res_845[] = {
 642         /* VFE0 */
 643         {
 644                 .regulators = {},
 645                 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
 646                                 "soc_ahb", "vfe0", "vfe0_axi",
 647                                 "vfe0_src", "csi0",
 648                                 "csi0_src"},
 649                 .clock_rate = { { 0 },
 650                                 { 0 },
 651                                 { 80000000 },
 652                                 { 0 },
 653                                 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
 654                                 { 0 },
 655                                 { 320000000 },
 656                                 { 19200000, 75000000, 384000000, 538666667 },
 657                                 { 384000000 } },
 658                 .reg = { "vfe0" },
 659                 .interrupt = { "vfe0" },
 660                 .line_num = 4,
 661                 .ops = &vfe_ops_170
 662         },
 663
 664         /* VFE1 */
 665         {
 666                 .regulators = {},
 667                 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
 668                                 "soc_ahb", "vfe1", "vfe1_axi",
 669                                 "vfe1_src", "csi1",
 670                                 "csi1_src"},
 671                 .clock_rate = { { 0 },
 672                                 { 0 },
 673                                 { 80000000 },
 674                                 { 0 },
 675                                 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
 676                                 { 0 },
 677                                 { 320000000 },
 678                                 { 19200000, 75000000, 384000000, 538666667 },
 679                                 { 384000000 } },
 680                 .reg = { "vfe1" },
 681                 .interrupt = { "vfe1" },
 682                 .line_num = 4,
 683                 .ops = &vfe_ops_170
 684         },
 685
 686         /* VFE-lite */
 687         {
 688                 .regulators = {},
 689                 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
 690                                 "soc_ahb", "vfe_lite",
 691                                 "vfe_lite_src", "csi2",
 692                                 "csi2_src"},
 693                 .clock_rate = { { 0 },
 694                                 { 0 },
 695                                 { 80000000 },
 696                                 { 0 },
 697                                 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 },
 698                                 { 320000000 },
 699                                 { 19200000, 75000000, 384000000, 538666667 },
 700                                 { 384000000 } },
 701                 .reg = { "vfe_lite" },
 702                 .interrupt = { "vfe_lite" },
 703                 .line_num = 4,
 704                 .ops = &vfe_ops_170
 705         }
 706 };
 707
 708 static const struct camss_subdev_resources csiphy_res_8250[] = {
 709         /* CSIPHY0 */
 710         {
 711                 .regulators = {},
 712                 .clock = { "csiphy0", "csiphy0_timer" },
 713                 .clock_rate = { { 400000000 },
 714                                 { 300000000 } },
 715                 .reg = { "csiphy0" },
 716                 .interrupt = { "csiphy0" },
 717                 .ops = &csiphy_ops_3ph_1_0
 718         },
 719         /* CSIPHY1 */
 720         {
 721                 .regulators = {},
 722                 .clock = { "csiphy1", "csiphy1_timer" },
 723                 .clock_rate = { { 400000000 },
 724                                 { 300000000 } },
 725                 .reg = { "csiphy1" },
 726                 .interrupt = { "csiphy1" },
 727                 .ops = &csiphy_ops_3ph_1_0
 728         },
 729         /* CSIPHY2 */
 730         {
 731                 .regulators = {},
 732                 .clock = { "csiphy2", "csiphy2_timer" },
 733                 .clock_rate = { { 400000000 },
 734                                 { 300000000 } },
 735                 .reg = { "csiphy2" },
 736                 .interrupt = { "csiphy2" },
 737                 .ops = &csiphy_ops_3ph_1_0
 738         },
 739         /* CSIPHY3 */
 740         {
 741                 .regulators = {},
 742                 .clock = { "csiphy3", "csiphy3_timer" },
 743                 .clock_rate = { { 400000000 },
 744                                 { 300000000 } },
 745                 .reg = { "csiphy3" },
 746                 .interrupt = { "csiphy3" },
 747                 .ops = &csiphy_ops_3ph_1_0
 748         },
 749         /* CSIPHY4 */
 750         {
 751                 .regulators = {},
 752                 .clock = { "csiphy4", "csiphy4_timer" },
 753                 .clock_rate = { { 400000000 },
 754                                 { 300000000 } },
 755                 .reg = { "csiphy4" },
 756                 .interrupt = { "csiphy4" },
 757                 .ops = &csiphy_ops_3ph_1_0
 758         },
 759         /* CSIPHY5 */
 760         {
 761                 .regulators = {},
 762                 .clock = { "csiphy5", "csiphy5_timer" },
 763                 .clock_rate = { { 400000000 },
 764                                 { 300000000 } },
 765                 .reg = { "csiphy5" },
 766                 .interrupt = { "csiphy5" },
 767                 .ops = &csiphy_ops_3ph_1_0
 768         }
 769 };
 770
 771 static const struct camss_subdev_resources csid_res_8250[] = {
 772         /* CSID0 */
 773         {
 774                 .regulators = { "vdda-phy", "vdda-pll" },
 775                 .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" },
 776                 .clock_rate = { { 400000000 },
 777                                 { 400000000 },
 778                                 { 350000000, 475000000, 576000000, 720000000 },
 779                                 { 100000000, 200000000, 300000000, 400000000 },
 780                                 { 0 } },
 781                 .reg = { "csid0" },
 782                 .interrupt = { "csid0" },
 783                 .ops = &csid_ops_gen2
 784         },
 785         /* CSID1 */
 786         {
 787                 .regulators = { "vdda-phy", "vdda-pll" },
 788                 .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" },
 789                 .clock_rate = { { 400000000 },
 790                                 { 400000000 },
 791                                 { 350000000, 475000000, 576000000, 720000000 },
 792                                 { 100000000, 200000000, 300000000, 400000000 },
 793                                 { 0 } },
 794                 .reg = { "csid1" },
 795                 .interrupt = { "csid1" },
 796                 .ops = &csid_ops_gen2
 797         },
 798         /* CSID2 */
 799         {
 800                 .regulators = { "vdda-phy", "vdda-pll" },
 801                 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",  "vfe_lite_ahb" },
 802                 .clock_rate = { { 400000000 },
 803                                 { 400000000 },
 804                                 { 400000000, 480000000 },
 805                                 { 0 } },
 806                 .reg = { "csid2" },
 807                 .interrupt = { "csid2" },
 808                 .ops = &csid_ops_gen2
 809         },
 810         /* CSID3 */
 811         {
 812                 .regulators = { "vdda-phy", "vdda-pll" },
 813                 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",  "vfe_lite_ahb" },
 814                 .clock_rate = { { 400000000 },
 815                                 { 400000000 },
 816                                 { 400000000, 480000000 },
 817                                 { 0 } },
 818                 .reg = { "csid3" },
 819                 .interrupt = { "csid3" },
 820                 .ops = &csid_ops_gen2
 821         }
 822 };
 823
 824 static const struct camss_subdev_resources vfe_res_8250[] = {
 825         /* VFE0 */
 826         {
 827                 .regulators = {},
 828                 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
 829                            "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0",
 830                            "vfe0_axi", "cam_hf_axi" },
 831                 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
 832                                 { 19200000, 80000000 },
 833                                 { 19200000 },
 834                                 { 0 },
 835                                 { 0 },
 836                                 { 100000000, 200000000, 300000000, 400000000 },
 837                                 { 350000000, 475000000, 576000000, 720000000 },
 838                                 { 0 },
 839                                 { 0 } },
 840                 .reg = { "vfe0" },
 841                 .interrupt = { "vfe0" },
 842                 .line_num = 3,
 843                 .ops = &vfe_ops_480
 844         },
 845         /* VFE1 */
 846         {
 847                 .regulators = {},
 848                 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
 849                            "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1",
 850                            "vfe1_axi", "cam_hf_axi" },
 851                 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
 852                                 { 19200000, 80000000 },
 853                                 { 19200000 },
 854                                 { 0 },
 855                                 { 0 },
 856                                 { 100000000, 200000000, 300000000, 400000000 },
 857                                 { 350000000, 475000000, 576000000, 720000000 },
 858                                 { 0 },
 859                                 { 0 } },
 860                 .reg = { "vfe1" },
 861                 .interrupt = { "vfe1" },
 862                 .line_num = 3,
 863                 .ops = &vfe_ops_480
 864         },
 865         /* VFE2 (lite) */
 866         {
 867                 .regulators = {},
 868                 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
 869                            "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
 870                            "vfe_lite", "cam_hf_axi" },
 871                 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
 872                                 { 19200000, 80000000 },
 873                                 { 19200000 },
 874                                 { 0 },
 875                                 { 0 },
 876                                 { 0 },
 877                                 { 400000000, 480000000 },
 878                                 { 0 } },
 879                 .reg = { "vfe_lite0" },
 880                 .interrupt = { "vfe_lite0" },
 881                 .line_num = 4,
 882                 .ops = &vfe_ops_480
 883         },
 884         /* VFE3 (lite) */
 885         {
 886                 .regulators = {},
 887                 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
 888                            "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
 889                            "vfe_lite", "cam_hf_axi" },
 890                 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 },
 891                                 { 19200000, 80000000 },
 892                                 { 19200000 },
 893                                 { 0 },
 894                                 { 0 },
 895                                 { 0 },
 896                                 { 400000000, 480000000 },
 897                                 { 0 } },
 898                 .reg = { "vfe_lite1" },
 899                 .interrupt = { "vfe_lite1" },
 900                 .line_num = 4,
 901                 .ops = &vfe_ops_480
 902         },
 903 };
 904
 905 static const struct resources_icc icc_res_sm8250[] = {
 906         {
 907                 .name = "cam_ahb",
 908                 .icc_bw_tbl.avg = 38400,
 909                 .icc_bw_tbl.peak = 76800,
 910         },
 911         {
 912                 .name = "cam_hf_0_mnoc",
 913                 .icc_bw_tbl.avg = 2097152,
 914                 .icc_bw_tbl.peak = 2097152,
 915         },
 916         {
 917                 .name = "cam_sf_0_mnoc",
 918                 .icc_bw_tbl.avg = 0,
 919                 .icc_bw_tbl.peak = 2097152,
 920         },
 921         {
 922                 .name = "cam_sf_icp_mnoc",
 923                 .icc_bw_tbl.avg = 2097152,
 924                 .icc_bw_tbl.peak = 2097152,
 925         },
 926 };
 927
 928 /*
 929  * camss_add_clock_margin - Add margin to clock frequency rate
 930  * @rate: Clock frequency rate
 931  *
 932  * When making calculations with physical clock frequency values
 933  * some safety margin must be added. Add it.
 934  */
 935 inline void camss_add_clock_margin(u64 *rate)
 936 {
 937         *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
 938         *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
 939 }
 940
 941 /*
 942  * camss_enable_clocks - Enable multiple clocks
 943  * @nclocks: Number of clocks in clock array
 944  * @clock: Clock array
 945  * @dev: Device
 946  *
 947  * Return 0 on success or a negative error code otherwise
 948  */
 949 int camss_enable_clocks(int nclocks, struct camss_clock *clock,
 950                         struct device *dev)
 951 {
 952         int ret;
 953         int i;
 954
 955         for (i = 0; i < nclocks; i++) {
 956                 ret = clk_prepare_enable(clock[i].clk);
 957                 if (ret) {
 958                         dev_err(dev, "clock enable failed: %d\n", ret);
 959                         goto error;
 960                 }
 961         }
 962
 963         return 0;
 964
 965 error:
 966         for (i--; i >= 0; i--)
 967                 clk_disable_unprepare(clock[i].clk);
 968
 969         return ret;
 970 }
 971
 972 /*
 973  * camss_disable_clocks - Disable multiple clocks
 974  * @nclocks: Number of clocks in clock array
 975  * @clock: Clock array
 976  */
 977 void camss_disable_clocks(int nclocks, struct camss_clock *clock)
 978 {
 979         int i;
 980
 981         for (i = nclocks - 1; i >= 0; i--)
 982                 clk_disable_unprepare(clock[i].clk);
 983 }
 984
 985 /*
 986  * camss_find_sensor - Find a linked media entity which represents a sensor
 987  * @entity: Media entity to start searching from
 988  *
 989  * Return a pointer to sensor media entity or NULL if not found
 990  */
 991 struct media_entity *camss_find_sensor(struct media_entity *entity)
 992 {
 993         struct media_pad *pad;
 994
 995         while (1) {
 996                 pad = &entity->pads[0];
 997                 if (!(pad->flags & MEDIA_PAD_FL_SINK))
 998                         return NULL;
 999
1000                 pad = media_pad_remote_pad_first(pad);
1001                 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
1002                         return NULL;
1003
1004                 entity = pad->entity;
1005
1006                 if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
1007                         return entity;
1008         }
1009 }
1010
1011 /**
1012  * camss_get_link_freq - Get link frequency from sensor
1013  * @entity: Media entity in the current pipeline
1014  * @bpp: Number of bits per pixel for the current format
1015  * @lanes: Number of lanes in the link to the sensor
1016  *
1017  * Return link frequency on success or a negative error code otherwise
1018  */
1019 s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
1020                         unsigned int lanes)
1021 {
1022         struct media_entity *sensor;
1023         struct v4l2_subdev *subdev;
1024
1025         sensor = camss_find_sensor(entity);
1026         if (!sensor)
1027                 return -ENODEV;
1028
1029         subdev = media_entity_to_v4l2_subdev(sensor);
1030
1031         return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes);
1032 }
1033
1034 /*
1035  * camss_get_pixel_clock - Get pixel clock rate from sensor
1036  * @entity: Media entity in the current pipeline
1037  * @pixel_clock: Received pixel clock value
1038  *
1039  * Return 0 on success or a negative error code otherwise
1040  */
1041 int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock)
1042 {
1043         struct media_entity *sensor;
1044         struct v4l2_subdev *subdev;
1045         struct v4l2_ctrl *ctrl;
1046
1047         sensor = camss_find_sensor(entity);
1048         if (!sensor)
1049                 return -ENODEV;
1050
1051         subdev = media_entity_to_v4l2_subdev(sensor);
1052
1053         ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
1054
1055         if (!ctrl)
1056                 return -EINVAL;
1057
1058         *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
1059
1060         return 0;
1061 }
1062
1063 int camss_pm_domain_on(struct camss *camss, int id)
1064 {
1065         int ret = 0;
1066
1067         if (id < camss->res->vfe_num) {
1068                 struct vfe_device *vfe = &camss->vfe[id];
1069
1070                 ret = vfe->ops->pm_domain_on(vfe);
1071         }
1072
1073         return ret;
1074 }
1075
1076 void camss_pm_domain_off(struct camss *camss, int id)
1077 {
1078         if (id < camss->res->vfe_num) {
1079                 struct vfe_device *vfe = &camss->vfe[id];
1080
1081                 vfe->ops->pm_domain_off(vfe);
1082         }
1083 }
1084
1085 /*
1086  * camss_of_parse_endpoint_node - Parse port endpoint node
1087  * @dev: Device
1088  * @node: Device node to be parsed
1089  * @csd: Parsed data from port endpoint node
1090  *
1091  * Return 0 on success or a negative error code on failure
1092  */
1093 static int camss_of_parse_endpoint_node(struct device *dev,
1094                                         struct device_node *node,
1095                                         struct camss_async_subdev *csd)
1096 {
1097         struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg;
1098         struct v4l2_mbus_config_mipi_csi2 *mipi_csi2;
1099         struct v4l2_fwnode_endpoint vep = { { 0 } };
1100         unsigned int i;
1101
1102         v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep);
1103
1104         csd->interface.csiphy_id = vep.base.port;
1105
1106         mipi_csi2 = &vep.bus.mipi_csi2;
1107         lncfg->clk.pos = mipi_csi2->clock_lane;
1108         lncfg->clk.pol = mipi_csi2->lane_polarities[0];
1109         lncfg->num_data = mipi_csi2->num_data_lanes;
1110
1111         lncfg->data = devm_kcalloc(dev,
1112                                    lncfg->num_data, sizeof(*lncfg->data),
1113                                    GFP_KERNEL);
1114         if (!lncfg->data)
1115                 return -ENOMEM;
1116
1117         for (i = 0; i < lncfg->num_data; i++) {
1118                 lncfg->data[i].pos = mipi_csi2->data_lanes[i];
1119                 lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1];
1120         }
1121
1122         return 0;
1123 }
1124
1125 /*
1126  * camss_of_parse_ports - Parse ports node
1127  * @dev: Device
1128  * @notifier: v4l2_device notifier data
1129  *
1130  * Return number of "port" nodes found in "ports" node
1131  */
1132 static int camss_of_parse_ports(struct camss *camss)
1133 {
1134         struct device *dev = camss->dev;
1135         struct device_node *node = NULL;
1136         struct device_node *remote = NULL;
1137         int ret, num_subdevs = 0;
1138
1139         for_each_endpoint_of_node(dev->of_node, node) {
1140                 struct camss_async_subdev *csd;
1141
1142                 if (!of_device_is_available(node))
1143                         continue;
1144
1145                 remote = of_graph_get_remote_port_parent(node);
1146                 if (!remote) {
1147                         dev_err(dev, "Cannot get remote parent\n");
1148                         ret = -EINVAL;
1149                         goto err_cleanup;
1150                 }
1151
1152                 csd = v4l2_async_nf_add_fwnode(&camss->notifier,
1153                                                of_fwnode_handle(remote),
1154                                                struct camss_async_subdev);
1155                 of_node_put(remote);
1156                 if (IS_ERR(csd)) {
1157                         ret = PTR_ERR(csd);
1158                         goto err_cleanup;
1159                 }
1160
1161                 ret = camss_of_parse_endpoint_node(dev, node, csd);
1162                 if (ret < 0)
1163                         goto err_cleanup;
1164
1165                 num_subdevs++;
1166         }
1167
1168         return num_subdevs;
1169
1170 err_cleanup:
1171         of_node_put(node);
1172         return ret;
1173 }
1174
1175 /*
1176  * camss_init_subdevices - Initialize subdev structures and resources
1177  * @camss: CAMSS device
1178  *
1179  * Return 0 on success or a negative error code on failure
1180  */
1181 static int camss_init_subdevices(struct camss *camss)
1182 {
1183         const struct camss_resources *res = camss->res;
1184         unsigned int i;
1185         int ret;
1186
1187         for (i = 0; i < camss->res->csiphy_num; i++) {
1188                 ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i],
1189                                              &res->csiphy_res[i], i);
1190                 if (ret < 0) {
1191                         dev_err(camss->dev,
1192                                 "Failed to init csiphy%d sub-device: %d\n",
1193                                 i, ret);
1194                         return ret;
1195                 }
1196         }
1197
1198         /* note: SM8250 requires VFE to be initialized before CSID */
1199         for (i = 0; i < camss->vfe_total_num; i++) {
1200                 ret = msm_vfe_subdev_init(camss, &camss->vfe[i],
1201                                           &res->vfe_res[i], i);
1202                 if (ret < 0) {
1203                         dev_err(camss->dev,
1204                                 "Fail to init vfe%d sub-device: %d\n", i, ret);
1205                         return ret;
1206                 }
1207         }
1208
1209         for (i = 0; i < camss->res->csid_num; i++) {
1210                 ret = msm_csid_subdev_init(camss, &camss->csid[i],
1211                                            &res->csid_res[i], i);
1212                 if (ret < 0) {
1213                         dev_err(camss->dev,
1214                                 "Failed to init csid%d sub-device: %d\n",
1215                                 i, ret);
1216                         return ret;
1217                 }
1218         }
1219
1220         ret = msm_ispif_subdev_init(camss, res->ispif_res);
1221         if (ret < 0) {
1222                 dev_err(camss->dev, "Failed to init ispif sub-device: %d\n",
1223                 ret);
1224                 return ret;
1225         }
1226
1227         return 0;
1228 }
1229
1230 /*
1231  * camss_register_entities - Register subdev nodes and create links
1232  * @camss: CAMSS device
1233  *
1234  * Return 0 on success or a negative error code on failure
1235  */
1236 static int camss_register_entities(struct camss *camss)
1237 {
1238         int i, j, k;
1239         int ret;
1240
1241         for (i = 0; i < camss->res->csiphy_num; i++) {
1242                 ret = msm_csiphy_register_entity(&camss->csiphy[i],
1243                                                  &camss->v4l2_dev);
1244                 if (ret < 0) {
1245                         dev_err(camss->dev,
1246                                 "Failed to register csiphy%d entity: %d\n",
1247                                 i, ret);
1248                         goto err_reg_csiphy;
1249                 }
1250         }
1251
1252         for (i = 0; i < camss->res->csid_num; i++) {
1253                 ret = msm_csid_register_entity(&camss->csid[i],
1254                                                &camss->v4l2_dev);
1255                 if (ret < 0) {
1256                         dev_err(camss->dev,
1257                                 "Failed to register csid%d entity: %d\n",
1258                                 i, ret);
1259                         goto err_reg_csid;
1260                 }
1261         }
1262
1263         ret = msm_ispif_register_entities(camss->ispif,
1264                                           &camss->v4l2_dev);
1265         if (ret < 0) {
1266                 dev_err(camss->dev, "Failed to register ispif entities: %d\n",
1267                 ret);
1268                 goto err_reg_ispif;
1269         }
1270
1271         for (i = 0; i < camss->vfe_total_num; i++) {
1272                 ret = msm_vfe_register_entities(&camss->vfe[i],
1273                                                 &camss->v4l2_dev);
1274                 if (ret < 0) {
1275                         dev_err(camss->dev,
1276                                 "Failed to register vfe%d entities: %d\n",
1277                                 i, ret);
1278                         goto err_reg_vfe;
1279                 }
1280         }
1281
1282         for (i = 0; i < camss->res->csiphy_num; i++) {
1283                 for (j = 0; j < camss->res->csid_num; j++) {
1284                         ret = media_create_pad_link(
1285                                 &camss->csiphy[i].subdev.entity,
1286                                 MSM_CSIPHY_PAD_SRC,
1287                                 &camss->csid[j].subdev.entity,
1288                                 MSM_CSID_PAD_SINK,
1289                                 0);
1290                         if (ret < 0) {
1291                                 dev_err(camss->dev,
1292                                         "Failed to link %s->%s entities: %d\n",
1293                                         camss->csiphy[i].subdev.entity.name,
1294                                         camss->csid[j].subdev.entity.name,
1295                                         ret);
1296                                 goto err_link;
1297                         }
1298                 }
1299         }
1300
1301         if (camss->ispif) {
1302                 for (i = 0; i < camss->res->csid_num; i++) {
1303                         for (j = 0; j < camss->ispif->line_num; j++) {
1304                                 ret = media_create_pad_link(
1305                                         &camss->csid[i].subdev.entity,
1306                                         MSM_CSID_PAD_SRC,
1307                                         &camss->ispif->line[j].subdev.entity,
1308                                         MSM_ISPIF_PAD_SINK,
1309                                         0);
1310                                 if (ret < 0) {
1311                                         dev_err(camss->dev,
1312                                                 "Failed to link %s->%s entities: %d\n",
1313                                                 camss->csid[i].subdev.entity.name,
1314                                                 camss->ispif->line[j].subdev.entity.name,
1315                                                 ret);
1316                                         goto err_link;
1317                                 }
1318                         }
1319                 }
1320
1321                 for (i = 0; i < camss->ispif->line_num; i++)
1322                         for (k = 0; k < camss->res->vfe_num; k++)
1323                                 for (j = 0; j < camss->vfe[k].line_num; j++) {
1324                                         struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
1325                                         struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
1326
1327                                         ret = media_create_pad_link(&ispif->entity,
1328                                                                     MSM_ISPIF_PAD_SRC,
1329                                                                     &vfe->entity,
1330                                                                     MSM_VFE_PAD_SINK,
1331                                                                     0);
1332                                         if (ret < 0) {
1333                                                 dev_err(camss->dev,
1334                                                         "Failed to link %s->%s entities: %d\n",
1335                                                         ispif->entity.name,
1336                                                         vfe->entity.name,
1337                                                         ret);
1338                                                 goto err_link;
1339                                         }
1340                                 }
1341         } else {
1342                 for (i = 0; i < camss->res->csid_num; i++)
1343                         for (k = 0; k < camss->vfe_total_num; k++)
1344                                 for (j = 0; j < camss->vfe[k].line_num; j++) {
1345                                         struct v4l2_subdev *csid = &camss->csid[i].subdev;
1346                                         struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
1347
1348                                         ret = media_create_pad_link(&csid->entity,
1349                                                                     MSM_CSID_PAD_FIRST_SRC + j,
1350                                                                     &vfe->entity,
1351                                                                     MSM_VFE_PAD_SINK,
1352                                                                     0);
1353                                         if (ret < 0) {
1354                                                 dev_err(camss->dev,
1355                                                         "Failed to link %s->%s entities: %d\n",
1356                                                         csid->entity.name,
1357                                                         vfe->entity.name,
1358                                                         ret);
1359                                                 goto err_link;
1360                                         }
1361                                 }
1362         }
1363
1364         return 0;
1365
1366 err_link:
1367         i = camss->vfe_total_num;
1368 err_reg_vfe:
1369         for (i--; i >= 0; i--)
1370                 msm_vfe_unregister_entities(&camss->vfe[i]);
1371
1372 err_reg_ispif:
1373         msm_ispif_unregister_entities(camss->ispif);
1374
1375         i = camss->res->csid_num;
1376 err_reg_csid:
1377         for (i--; i >= 0; i--)
1378                 msm_csid_unregister_entity(&camss->csid[i]);
1379
1380         i = camss->res->csiphy_num;
1381 err_reg_csiphy:
1382         for (i--; i >= 0; i--)
1383                 msm_csiphy_unregister_entity(&camss->csiphy[i]);
1384
1385         return ret;
1386 }
1387
1388 /*
1389  * camss_unregister_entities - Unregister subdev nodes
1390  * @camss: CAMSS device
1391  *
1392  * Return 0 on success or a negative error code on failure
1393  */
1394 static void camss_unregister_entities(struct camss *camss)
1395 {
1396         unsigned int i;
1397
1398         for (i = 0; i < camss->res->csiphy_num; i++)
1399                 msm_csiphy_unregister_entity(&camss->csiphy[i]);
1400
1401         for (i = 0; i < camss->res->csid_num; i++)
1402                 msm_csid_unregister_entity(&camss->csid[i]);
1403
1404         msm_ispif_unregister_entities(camss->ispif);
1405
1406         for (i = 0; i < camss->vfe_total_num; i++)
1407                 msm_vfe_unregister_entities(&camss->vfe[i]);
1408 }
1409
1410 static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async,
1411                                        struct v4l2_subdev *subdev,
1412                                        struct v4l2_async_connection *asd)
1413 {
1414         struct camss *camss = container_of(async, struct camss, notifier);
1415         struct camss_async_subdev *csd =
1416                 container_of(asd, struct camss_async_subdev, asd);
1417         u8 id = csd->interface.csiphy_id;
1418         struct csiphy_device *csiphy = &camss->csiphy[id];
1419
1420         csiphy->cfg.csi2 = &csd->interface.csi2;
1421         subdev->host_priv = csiphy;
1422
1423         return 0;
1424 }
1425
1426 static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
1427 {
1428         struct camss *camss = container_of(async, struct camss, notifier);
1429         struct v4l2_device *v4l2_dev = &camss->v4l2_dev;
1430         struct v4l2_subdev *sd;
1431         int ret;
1432
1433         list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
1434                 if (sd->host_priv) {
1435                         struct media_entity *sensor = &sd->entity;
1436                         struct csiphy_device *csiphy =
1437                                         (struct csiphy_device *) sd->host_priv;
1438                         struct media_entity *input = &csiphy->subdev.entity;
1439                         unsigned int i;
1440
1441                         for (i = 0; i < sensor->num_pads; i++) {
1442                                 if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1443                                         break;
1444                         }
1445                         if (i == sensor->num_pads) {
1446                                 dev_err(camss->dev,
1447                                         "No source pad in external entity\n");
1448                                 return -EINVAL;
1449                         }
1450
1451                         ret = media_create_pad_link(sensor, i,
1452                                 input, MSM_CSIPHY_PAD_SINK,
1453                                 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1454                         if (ret < 0) {
1455                                 dev_err(camss->dev,
1456                                         "Failed to link %s->%s entities: %d\n",
1457                                         sensor->name, input->name, ret);
1458                                 return ret;
1459                         }
1460                 }
1461         }
1462
1463         ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
1464         if (ret < 0)
1465                 return ret;
1466
1467         return media_device_register(&camss->media_dev);
1468 }
1469
1470 static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = {
1471         .bound = camss_subdev_notifier_bound,
1472         .complete = camss_subdev_notifier_complete,
1473 };
1474
1475 static const struct media_device_ops camss_media_ops = {
1476         .link_notify = v4l2_pipeline_link_notify,
1477 };
1478
1479 static int camss_configure_pd(struct camss *camss)
1480 {
1481         struct device *dev = camss->dev;
1482         int i;
1483         int ret;
1484
1485         camss->genpd_num = of_count_phandle_with_args(dev->of_node,
1486                                                       "power-domains",
1487                                                       "#power-domain-cells");
1488         if (camss->genpd_num < 0) {
1489                 dev_err(dev, "Power domains are not defined for camss\n");
1490                 return camss->genpd_num;
1491         }
1492
1493         /*
1494          * If a platform device has just one power domain, then it is attached
1495          * at platform_probe() level, thus there shall be no need and even no
1496          * option to attach it again, this is the case for CAMSS on MSM8916.
1497          */
1498         if (camss->genpd_num == 1)
1499                 return 0;
1500
1501         camss->genpd = devm_kmalloc_array(dev, camss->genpd_num,
1502                                           sizeof(*camss->genpd), GFP_KERNEL);
1503         if (!camss->genpd)
1504                 return -ENOMEM;
1505
1506         camss->genpd_link = devm_kmalloc_array(dev, camss->genpd_num,
1507                                                sizeof(*camss->genpd_link),
1508                                                GFP_KERNEL);
1509         if (!camss->genpd_link)
1510                 return -ENOMEM;
1511
1512         /*
1513          * VFE power domains are in the beginning of the list, and while all
1514          * power domains should be attached, only if TITAN_TOP power domain is
1515          * found in the list, it should be linked over here.
1516          */
1517         for (i = 0; i < camss->genpd_num; i++) {
1518                 camss->genpd[i] = dev_pm_domain_attach_by_id(camss->dev, i);
1519                 if (IS_ERR(camss->genpd[i])) {
1520                         ret = PTR_ERR(camss->genpd[i]);
1521                         goto fail_pm;
1522                 }
1523         }
1524
1525         if (i > camss->res->vfe_num) {
1526                 camss->genpd_link[i - 1] = device_link_add(camss->dev, camss->genpd[i - 1],
1527                                                            DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
1528                                                            DL_FLAG_RPM_ACTIVE);
1529                 if (!camss->genpd_link[i - 1]) {
1530                         ret = -EINVAL;
1531                         goto fail_pm;
1532                 }
1533         }
1534
1535         return 0;
1536
1537 fail_pm:
1538         for (--i ; i >= 0; i--)
1539                 dev_pm_domain_detach(camss->genpd[i], true);
1540
1541         return ret;
1542 }
1543
1544 static int camss_icc_get(struct camss *camss)
1545 {
1546         const struct resources_icc *icc_res;
1547         int i;
1548
1549         icc_res = camss->res->icc_res;
1550
1551         for (i = 0; i < camss->res->icc_path_num; i++) {
1552                 camss->icc_path[i] = devm_of_icc_get(camss->dev,
1553                                                      icc_res[i].name);
1554                 if (IS_ERR(camss->icc_path[i]))
1555                         return PTR_ERR(camss->icc_path[i]);
1556         }
1557
1558         return 0;
1559 }
1560
1561 static void camss_genpd_cleanup(struct camss *camss)
1562 {
1563         int i;
1564
1565         if (camss->genpd_num == 1)
1566                 return;
1567
1568         if (camss->genpd_num > camss->res->vfe_num)
1569                 device_link_del(camss->genpd_link[camss->genpd_num - 1]);
1570
1571         for (i = 0; i < camss->genpd_num; i++)
1572                 dev_pm_domain_detach(camss->genpd[i], true);
1573 }
1574
1575 /*
1576  * camss_probe - Probe CAMSS platform device
1577  * @pdev: Pointer to CAMSS platform device
1578  *
1579  * Return 0 on success or a negative error code on failure
1580  */
1581 static int camss_probe(struct platform_device *pdev)
1582 {
1583         struct device *dev = &pdev->dev;
1584         struct camss *camss;
1585         int num_subdevs;
1586         int ret;
1587
1588         camss = devm_kzalloc(dev, sizeof(*camss), GFP_KERNEL);
1589         if (!camss)
1590                 return -ENOMEM;
1591
1592         camss->res = of_device_get_match_data(dev);
1593
1594         atomic_set(&camss->ref_count, 0);
1595         camss->dev = dev;
1596         platform_set_drvdata(pdev, camss);
1597
1598         camss->csiphy = devm_kcalloc(dev, camss->res->csiphy_num,
1599                                      sizeof(*camss->csiphy), GFP_KERNEL);
1600         if (!camss->csiphy)
1601                 return -ENOMEM;
1602
1603         camss->csid = devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->csid),
1604                                    GFP_KERNEL);
1605         if (!camss->csid)
1606                 return -ENOMEM;
1607
1608         if (camss->res->version == CAMSS_8x16 ||
1609             camss->res->version == CAMSS_8x96) {
1610                 camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL);
1611                 if (!camss->ispif)
1612                         return -ENOMEM;
1613         }
1614
1615         camss->vfe_total_num = camss->res->vfe_num + camss->res->vfe_lite_num;
1616         camss->vfe = devm_kcalloc(dev, camss->vfe_total_num,
1617                                   sizeof(*camss->vfe), GFP_KERNEL);
1618         if (!camss->vfe)
1619                 return -ENOMEM;
1620
1621         ret = camss_icc_get(camss);
1622         if (ret < 0)
1623                 return ret;
1624
1625         ret = camss_configure_pd(camss);
1626         if (ret < 0) {
1627                 dev_err(dev, "Failed to configure power domains: %d\n", ret);
1628                 return ret;
1629         }
1630
1631         ret = camss_init_subdevices(camss);
1632         if (ret < 0)
1633                 goto err_genpd_cleanup;
1634
1635         ret = dma_set_mask_and_coherent(dev, 0xffffffff);
1636         if (ret)
1637                 goto err_genpd_cleanup;
1638
1639         camss->media_dev.dev = camss->dev;
1640         strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem",
1641                 sizeof(camss->media_dev.model));
1642         camss->media_dev.ops = &camss_media_ops;
1643         media_device_init(&camss->media_dev);
1644
1645         camss->v4l2_dev.mdev = &camss->media_dev;
1646         ret = v4l2_device_register(camss->dev, &camss->v4l2_dev);
1647         if (ret < 0) {
1648                 dev_err(dev, "Failed to register V4L2 device: %d\n", ret);
1649                 goto err_genpd_cleanup;
1650         }
1651
1652         v4l2_async_nf_init(&camss->notifier, &camss->v4l2_dev);
1653
1654         num_subdevs = camss_of_parse_ports(camss);
1655         if (num_subdevs < 0) {
1656                 ret = num_subdevs;
1657                 goto err_v4l2_device_unregister;
1658         }
1659
1660         ret = camss_register_entities(camss);
1661         if (ret < 0)
1662                 goto err_v4l2_device_unregister;
1663
1664         if (num_subdevs) {
1665                 camss->notifier.ops = &camss_subdev_notifier_ops;
1666
1667                 ret = v4l2_async_nf_register(&camss->notifier);
1668                 if (ret) {
1669                         dev_err(dev,
1670                                 "Failed to register async subdev nodes: %d\n",
1671                                 ret);
1672                         goto err_register_subdevs;
1673                 }
1674         } else {
1675                 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
1676                 if (ret < 0) {
1677                         dev_err(dev, "Failed to register subdev nodes: %d\n",
1678                                 ret);
1679                         goto err_register_subdevs;
1680                 }
1681
1682                 ret = media_device_register(&camss->media_dev);
1683                 if (ret < 0) {
1684                         dev_err(dev, "Failed to register media device: %d\n",
1685                                 ret);
1686                         goto err_register_subdevs;
1687                 }
1688         }
1689
1690         pm_runtime_enable(dev);
1691
1692         return 0;
1693
1694 err_register_subdevs:
1695         camss_unregister_entities(camss);
1696 err_v4l2_device_unregister:
1697         v4l2_device_unregister(&camss->v4l2_dev);
1698         v4l2_async_nf_cleanup(&camss->notifier);
1699 err_genpd_cleanup:
1700         camss_genpd_cleanup(camss);
1701
1702         return ret;
1703 }
1704
1705 void camss_delete(struct camss *camss)
1706 {
1707         v4l2_device_unregister(&camss->v4l2_dev);
1708         media_device_unregister(&camss->media_dev);
1709         media_device_cleanup(&camss->media_dev);
1710
1711         pm_runtime_disable(camss->dev);
1712 }
1713
1714 /*
1715  * camss_remove - Remove CAMSS platform device
1716  * @pdev: Pointer to CAMSS platform device
1717  *
1718  * Always returns 0.
1719  */
1720 static void camss_remove(struct platform_device *pdev)
1721 {
1722         struct camss *camss = platform_get_drvdata(pdev);
1723
1724         v4l2_async_nf_unregister(&camss->notifier);
1725         v4l2_async_nf_cleanup(&camss->notifier);
1726         camss_unregister_entities(camss);
1727
1728         if (atomic_read(&camss->ref_count) == 0)
1729                 camss_delete(camss);
1730
1731         camss_genpd_cleanup(camss);
1732 }
1733
1734 static const struct camss_resources msm8916_resources = {
1735         .version = CAMSS_8x16,
1736         .csiphy_res = csiphy_res_8x16,
1737         .csid_res = csid_res_8x16,
1738         .ispif_res = &ispif_res_8x16,
1739         .vfe_res = vfe_res_8x16,
1740         .csiphy_num = ARRAY_SIZE(csiphy_res_8x16),
1741         .csid_num = ARRAY_SIZE(csid_res_8x16),
1742         .vfe_num = ARRAY_SIZE(vfe_res_8x16),
1743 };
1744
1745 static const struct camss_resources msm8996_resources = {
1746         .version = CAMSS_8x96,
1747         .csiphy_res = csiphy_res_8x96,
1748         .csid_res = csid_res_8x96,
1749         .ispif_res = &ispif_res_8x96,
1750         .vfe_res = vfe_res_8x96,
1751         .csiphy_num = ARRAY_SIZE(csiphy_res_8x96),
1752         .csid_num = ARRAY_SIZE(csid_res_8x96),
1753         .vfe_num = ARRAY_SIZE(vfe_res_8x96),
1754 };
1755
1756 static const struct camss_resources sdm660_resources = {
1757         .version = CAMSS_660,
1758         .csiphy_res = csiphy_res_660,
1759         .csid_res = csid_res_660,
1760         .ispif_res = &ispif_res_660,
1761         .vfe_res = vfe_res_660,
1762         .csiphy_num = ARRAY_SIZE(csiphy_res_660),
1763         .csid_num = ARRAY_SIZE(csid_res_660),
1764         .vfe_num = ARRAY_SIZE(vfe_res_660),
1765 };
1766
1767 static const struct camss_resources sdm845_resources = {
1768         .version = CAMSS_845,
1769         .csiphy_res = csiphy_res_845,
1770         .csid_res = csid_res_845,
1771         .vfe_res = vfe_res_845,
1772         .csiphy_num = ARRAY_SIZE(csiphy_res_845),
1773         .csid_num = ARRAY_SIZE(csid_res_845),
1774         .vfe_num = 2,
1775         .vfe_lite_num = 1,
1776 };
1777
1778 static const struct camss_resources sm8250_resources = {
1779         .version = CAMSS_8250,
1780         .csiphy_res = csiphy_res_8250,
1781         .csid_res = csid_res_8250,
1782         .vfe_res = vfe_res_8250,
1783         .icc_res = icc_res_sm8250,
1784         .icc_path_num = ARRAY_SIZE(icc_res_sm8250),
1785         .csiphy_num = ARRAY_SIZE(csiphy_res_8250),
1786         .csid_num = ARRAY_SIZE(csid_res_8250),
1787         .vfe_num = 2,
1788         .vfe_lite_num = 2,
1789 };
1790
1791 static const struct of_device_id camss_dt_match[] = {
1792         { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
1793         { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
1794         { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
1795         { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
1796         { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
1797         { }
1798 };
1799
1800 MODULE_DEVICE_TABLE(of, camss_dt_match);
1801
1802 static int __maybe_unused camss_runtime_suspend(struct device *dev)
1803 {
1804         struct camss *camss = dev_get_drvdata(dev);
1805         int i;
1806         int ret;
1807
1808         for (i = 0; i < camss->res->icc_path_num; i++) {
1809                 ret = icc_set_bw(camss->icc_path[i], 0, 0);
1810                 if (ret)
1811                         return ret;
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int __maybe_unused camss_runtime_resume(struct device *dev)
1818 {
1819         struct camss *camss = dev_get_drvdata(dev);
1820         const struct resources_icc *icc_res = camss->res->icc_res;
1821         int i;
1822         int ret;
1823
1824         for (i = 0; i < camss->res->icc_path_num; i++) {
1825                 ret = icc_set_bw(camss->icc_path[i],
1826                                  icc_res[i].icc_bw_tbl.avg,
1827                                  icc_res[i].icc_bw_tbl.peak);
1828                 if (ret)
1829                         return ret;
1830         }
1831
1832         return 0;
1833 }
1834
1835 static const struct dev_pm_ops camss_pm_ops = {
1836         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1837                                 pm_runtime_force_resume)
1838         SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL)
1839 };
1840
1841 static struct platform_driver qcom_camss_driver = {
1842         .probe = camss_probe,
1843         .remove_new = camss_remove,
1844         .driver = {
1845                 .name = "qcom-camss",
1846                 .of_match_table = camss_dt_match,
1847                 .pm = &camss_pm_ops,
1848         },
1849 };
1850
1851 module_platform_driver(qcom_camss_driver);
1852
1853 MODULE_ALIAS("platform:qcom-camss");
1854 MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver");
1855 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1856 MODULE_LICENSE("GPL v2");