1 // SPDX-License-Identifier: GPL-2.0
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v480 (SM8250)
7 * Copyright (C) 2020-2021 Linaro Ltd.
8 * Copyright (C) 2021 Jonathan Marek
11 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
16 #include "camss-vfe.h"
18 /* VFE 2/3 are lite and have a different register layout */
19 #define IS_LITE (vfe->id >= 2 ? 1 : 0)
21 #define VFE_HW_VERSION (0x00)
23 #define VFE_GLOBAL_RESET_CMD (IS_LITE ? 0x0c : 0x1c)
24 #define GLOBAL_RESET_HW_AND_REG (IS_LITE ? BIT(1) : BIT(0))
26 #define VFE_REG_UPDATE_CMD (IS_LITE ? 0x20 : 0x34)
27 static inline int reg_update_rdi(struct vfe_device *vfe, int n)
29 return IS_LITE ? BIT(n) : BIT(1 + (n));
32 #define REG_UPDATE_RDI reg_update_rdi
33 #define VFE_IRQ_CMD (IS_LITE ? 0x24 : 0x38)
34 #define IRQ_CMD_GLOBAL_CLEAR BIT(0)
36 #define VFE_IRQ_MASK(n) ((IS_LITE ? 0x28 : 0x3c) + (n) * 4)
37 #define IRQ_MASK_0_RESET_ACK (IS_LITE ? BIT(17) : BIT(0))
38 #define IRQ_MASK_0_BUS_TOP_IRQ (IS_LITE ? BIT(4) : BIT(7))
39 #define VFE_IRQ_CLEAR(n) ((IS_LITE ? 0x34 : 0x48) + (n) * 4)
40 #define VFE_IRQ_STATUS(n) ((IS_LITE ? 0x40 : 0x54) + (n) * 4)
42 #define BUS_REG_BASE (IS_LITE ? 0x1a00 : 0xaa00)
44 #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
45 #define WM_CGC_OVERRIDE_ALL (0x3FFFFFF)
47 #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xdc)
49 #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4)
50 static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n)
52 return IS_LITE ? BIT(n) : BIT(3 + (n));
55 #define BUS_IRQ_MASK_0_RDI_RUP bus_irq_mask_0_rdi_rup
56 static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n)
58 return IS_LITE ? BIT(4 + (n)) : BIT(6 + (n));
61 #define BUS_IRQ_MASK_0_COMP_DONE bus_irq_mask_0_comp_done
62 #define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4)
63 #define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4)
64 #define VFE_BUS_IRQ_CLEAR_GLOBAL (BUS_REG_BASE + 0x30)
66 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
68 #define WM_CFG_MODE (16)
69 #define MODE_QCOM_PLAIN (0)
70 #define MODE_MIPI_RAW (1)
71 #define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100)
72 #define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100)
73 #define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100)
74 #define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
75 #define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100)
76 #define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100)
77 #define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100)
78 #define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100)
79 #define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100)
80 #define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100)
82 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100)
83 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100)
84 #define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100)
85 #define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100)
87 #define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
88 #define VFE_BUS_WM_BURST_LIMIT(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
90 /* for titan 480, each bus client is hardcoded to a specific path
91 * and each bus client is part of a hardcoded "comp group"
93 #define RDI_WM(n) ((IS_LITE ? 0 : 23) + (n))
94 #define RDI_COMP_GROUP(n) ((IS_LITE ? 0 : 11) + (n))
96 #define MAX_VFE_OUTPUT_LINES 4
98 static u32 vfe_hw_version(struct vfe_device *vfe)
100 u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION);
102 u32 gen = (hw_version >> 28) & 0xF;
103 u32 rev = (hw_version >> 16) & 0xFFF;
104 u32 step = hw_version & 0xFFFF;
106 dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step);
111 static void vfe_global_reset(struct vfe_device *vfe)
113 writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0));
114 writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD);
117 static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
119 struct v4l2_pix_format_mplane *pix =
120 &line->video_out.active_fmt.fmt.pix_mp;
122 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
124 /* no clock gating at bus input */
125 writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
127 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
129 writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height,
130 vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
131 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
132 writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH,
133 vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
134 writel_relaxed(pix->plane_fmt[0].bytesperline,
135 vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
136 writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
138 /* no dropped frames, one irq per frame */
139 writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
140 writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
141 writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
142 writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
144 writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE,
145 vfe->base + VFE_BUS_WM_CFG(wm));
148 static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
150 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
151 writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
154 static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
155 struct vfe_line *line)
157 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
158 writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
161 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
163 vfe->reg_update |= REG_UPDATE_RDI(vfe, line_id);
164 writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
167 static inline void vfe_reg_update_clear(struct vfe_device *vfe,
168 enum vfe_line_id line_id)
170 vfe->reg_update &= ~REG_UPDATE_RDI(vfe, line_id);
173 static void vfe_enable_irq_common(struct vfe_device *vfe)
175 /* enable reset ack IRQ and top BUS status IRQ */
176 writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ,
177 vfe->base + VFE_IRQ_MASK(0));
180 static void vfe_enable_lines_irq(struct vfe_device *vfe)
183 u32 bus_irq_mask = 0;
185 for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) {
186 /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */
187 if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED ||
188 vfe->line[i].output.state == VFE_OUTPUT_ON) {
189 bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i)
190 | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i));
194 writel_relaxed(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0));
197 static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id);
198 static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm);
201 * vfe_isr - VFE module interrupt handler
202 * @irq: Interrupt line
205 * Return IRQ_HANDLED on success
207 static irqreturn_t vfe_isr(int irq, void *dev)
209 struct vfe_device *vfe = dev;
213 status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0));
214 writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0));
215 writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
217 if (status & IRQ_MASK_0_RESET_ACK)
218 vfe_isr_reset_ack(vfe);
220 if (status & IRQ_MASK_0_BUS_TOP_IRQ) {
221 u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0));
223 writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0));
224 writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
226 /* Loop through all WMs IRQs */
227 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) {
228 if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, i))
229 vfe_isr_reg_update(vfe, i);
231 if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)))
232 vfe_isr_wm_done(vfe, i);
240 * vfe_halt - Trigger halt on VFE module and wait to complete
243 * Return 0 on success or a negative error code otherwise
245 static int vfe_halt(struct vfe_device *vfe)
247 /* rely on vfe_disable_output() to stop the VFE */
251 static int vfe_get_output(struct vfe_line *line)
253 struct vfe_device *vfe = to_vfe(line);
254 struct vfe_output *output;
257 spin_lock_irqsave(&vfe->output_lock, flags);
259 output = &line->output;
260 if (output->state > VFE_OUTPUT_RESERVED) {
261 dev_err(vfe->camss->dev, "Output is running\n");
267 /* Correspondence between VFE line number and WM number.
268 * line 0 -> RDI 0, line 1 -> RDI1, line 2 -> RDI2, line 3 -> PIX/RDI3
269 * Note this 1:1 mapping will not work for PIX streams.
271 output->wm_idx[0] = line->id;
272 vfe->wm_output_map[line->id] = line->id;
274 output->drop_update_idx = 0;
276 spin_unlock_irqrestore(&vfe->output_lock, flags);
281 spin_unlock_irqrestore(&vfe->output_lock, flags);
282 output->state = VFE_OUTPUT_OFF;
287 static int vfe_enable_output(struct vfe_line *line)
289 struct vfe_device *vfe = to_vfe(line);
290 struct vfe_output *output = &line->output;
294 spin_lock_irqsave(&vfe->output_lock, flags);
296 vfe_reg_update_clear(vfe, line->id);
298 if (output->state > VFE_OUTPUT_RESERVED) {
299 dev_err(vfe->camss->dev, "Output is not in reserved state %d\n",
301 spin_unlock_irqrestore(&vfe->output_lock, flags);
305 WARN_ON(output->gen2.active_num);
307 output->state = VFE_OUTPUT_ON;
309 output->sequence = 0;
310 output->wait_reg_update = 0;
311 reinit_completion(&output->reg_update);
313 vfe_wm_start(vfe, output->wm_idx[0], line);
315 for (i = 0; i < 2; i++) {
316 output->buf[i] = vfe_buf_get_pending(output);
319 output->gen2.active_num++;
320 vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line);
323 vfe_reg_update(vfe, line->id);
325 spin_unlock_irqrestore(&vfe->output_lock, flags);
331 * vfe_enable - Enable streaming on VFE line
334 * Return 0 on success or a negative error code otherwise
336 static int vfe_enable(struct vfe_line *line)
338 struct vfe_device *vfe = to_vfe(line);
341 mutex_lock(&vfe->stream_lock);
343 if (!vfe->stream_count)
344 vfe_enable_irq_common(vfe);
348 vfe_enable_lines_irq(vfe);
350 mutex_unlock(&vfe->stream_lock);
352 ret = vfe_get_output(line);
354 goto error_get_output;
356 ret = vfe_enable_output(line);
358 goto error_enable_output;
360 vfe->was_streaming = 1;
365 vfe_put_output(line);
368 mutex_lock(&vfe->stream_lock);
372 mutex_unlock(&vfe->stream_lock);
378 * vfe_isr_reg_update - Process reg update interrupt
382 static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
384 struct vfe_output *output;
387 spin_lock_irqsave(&vfe->output_lock, flags);
388 vfe_reg_update_clear(vfe, line_id);
390 output = &vfe->line[line_id].output;
392 if (output->wait_reg_update) {
393 output->wait_reg_update = 0;
394 complete(&output->reg_update);
397 spin_unlock_irqrestore(&vfe->output_lock, flags);
401 * vfe_isr_wm_done - Process write master done interrupt
403 * @wm: Write master id
405 static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm)
407 struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]];
408 struct camss_buffer *ready_buf;
409 struct vfe_output *output;
412 u64 ts = ktime_get_ns();
414 spin_lock_irqsave(&vfe->output_lock, flags);
416 if (vfe->wm_output_map[wm] == VFE_LINE_NONE) {
417 dev_err_ratelimited(vfe->camss->dev,
418 "Received wm done for unmapped index\n");
421 output = &vfe->line[vfe->wm_output_map[wm]].output;
423 ready_buf = output->buf[0];
425 dev_err_ratelimited(vfe->camss->dev,
426 "Missing ready buf %d!\n", output->state);
430 ready_buf->vb.vb2_buf.timestamp = ts;
431 ready_buf->vb.sequence = output->sequence++;
434 output->buf[0] = output->buf[1];
438 output->buf[index] = vfe_buf_get_pending(output);
440 if (output->buf[index])
441 vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line);
443 output->gen2.active_num--;
445 spin_unlock_irqrestore(&vfe->output_lock, flags);
447 vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
452 spin_unlock_irqrestore(&vfe->output_lock, flags);
456 * vfe_pm_domain_off - Disable power domains specific to this VFE.
459 static void vfe_pm_domain_off(struct vfe_device *vfe)
461 struct camss *camss = vfe->camss;
463 if (vfe->id >= camss->res->vfe_num)
466 device_link_del(camss->genpd_link[vfe->id]);
470 * vfe_pm_domain_on - Enable power domains specific to this VFE.
473 static int vfe_pm_domain_on(struct vfe_device *vfe)
475 struct camss *camss = vfe->camss;
476 enum vfe_line_id id = vfe->id;
478 if (id >= camss->res->vfe_num)
481 camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id],
485 if (!camss->genpd_link[id])
492 * vfe_queue_buffer - Add empty buffer
493 * @vid: Video device structure
494 * @buf: Buffer to be enqueued
496 * Add an empty buffer - depending on the current number of buffers it will be
497 * put in pending buffer queue or directly given to the hardware to be filled.
499 * Return 0 on success or a negative error code otherwise
501 static int vfe_queue_buffer(struct camss_video *vid,
502 struct camss_buffer *buf)
504 struct vfe_line *line = container_of(vid, struct vfe_line, video_out);
505 struct vfe_device *vfe = to_vfe(line);
506 struct vfe_output *output;
509 output = &line->output;
511 spin_lock_irqsave(&vfe->output_lock, flags);
513 if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) {
514 output->buf[output->gen2.active_num++] = buf;
515 vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line);
517 vfe_buf_add_pending(output, buf);
520 spin_unlock_irqrestore(&vfe->output_lock, flags);
525 static const struct camss_video_ops vfe_video_ops_480 = {
526 .queue_buffer = vfe_queue_buffer,
527 .flush_buffers = vfe_flush_buffers,
530 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
532 vfe->video_ops = vfe_video_ops_480;
535 const struct vfe_hw_ops vfe_ops_480 = {
536 .global_reset = vfe_global_reset,
537 .hw_version = vfe_hw_version,
539 .pm_domain_off = vfe_pm_domain_off,
540 .pm_domain_on = vfe_pm_domain_on,
541 .subdev_init = vfe_subdev_init,
542 .vfe_disable = vfe_disable,
543 .vfe_enable = vfe_enable,
544 .vfe_halt = vfe_halt,
545 .vfe_wm_stop = vfe_wm_stop,