2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
26 #include <linux/moduleparam.h>
28 #include <linux/of_graph.h>
29 #include <linux/time.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dma/pxa-dma.h>
38 #include <media/v4l2-async.h>
39 #include <media/v4l2-clk.h>
40 #include <media/v4l2-common.h>
41 #include <media/v4l2-ctrls.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-event.h>
44 #include <media/v4l2-ioctl.h>
45 #include <media/v4l2-fwnode.h>
47 #include <media/videobuf2-dma-sg.h>
49 #include <linux/videodev2.h>
51 #include <linux/platform_data/media/camera-pxa.h>
53 #define PXA_CAM_VERSION "0.0.6"
54 #define PXA_CAM_DRV_NAME "pxa27x-camera"
56 #define DEFAULT_WIDTH 640
57 #define DEFAULT_HEIGHT 480
59 /* Camera Interface */
72 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
73 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
74 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
75 #define CICR0_ENB (1 << 28) /* Camera interface enable */
76 #define CICR0_DIS (1 << 27) /* Camera interface disable */
77 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
78 #define CICR0_TOM (1 << 9) /* Time-out mask */
79 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
80 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
81 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
82 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
83 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
84 #define CICR0_CDM (1 << 3) /* Disable-done mask */
85 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
86 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
87 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
89 #define CICR1_TBIT (1 << 31) /* Transparency bit */
90 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
91 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
92 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
93 #define CICR1_RGB_F (1 << 11) /* RGB format */
94 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
95 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
96 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
97 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
98 #define CICR1_DW (0x7 << 0) /* Data width mask */
100 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
102 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
104 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
105 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
107 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
110 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
112 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
114 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
115 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
117 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
119 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
120 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
121 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
122 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
123 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
124 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
125 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
126 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
128 #define CISR_FTO (1 << 15) /* FIFO time-out */
129 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
130 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
131 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
132 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
133 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
134 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
135 #define CISR_EOL (1 << 8) /* End of line */
136 #define CISR_PAR_ERR (1 << 7) /* Parity error */
137 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
138 #define CISR_CDD (1 << 5) /* Camera interface disable done */
139 #define CISR_SOF (1 << 4) /* Start of frame */
140 #define CISR_EOF (1 << 3) /* End of frame */
141 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
142 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
143 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
145 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
146 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
147 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
148 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
149 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
150 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
151 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
152 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
154 #define CICR0_SIM_MP (0 << 24)
155 #define CICR0_SIM_SP (1 << 24)
156 #define CICR0_SIM_MS (2 << 24)
157 #define CICR0_SIM_EP (3 << 24)
158 #define CICR0_SIM_ES (4 << 24)
160 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
161 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
162 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
163 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
164 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
166 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
167 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
168 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
169 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
170 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
172 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
173 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
174 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
175 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
177 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
178 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
179 CICR0_EOFM | CICR0_FOM)
181 #define sensor_call(cam, o, f, args...) \
182 v4l2_subdev_call(cam->sensor, o, f, ##args)
189 * enum pxa_mbus_packing - data packing types on the media-bus
190 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
191 * sample represents one pixel
192 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
193 * possibly incomplete byte high bits are padding
194 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
197 enum pxa_mbus_packing {
198 PXA_MBUS_PACKING_NONE,
199 PXA_MBUS_PACKING_2X8_PADHI,
200 PXA_MBUS_PACKING_EXTEND16,
204 * enum pxa_mbus_order - sample order on the media bus
205 * @PXA_MBUS_ORDER_LE: least significant sample first
206 * @PXA_MBUS_ORDER_BE: most significant sample first
208 enum pxa_mbus_order {
214 * enum pxa_mbus_layout - planes layout in memory
215 * @PXA_MBUS_LAYOUT_PACKED: color components packed
216 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
217 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
218 * chroma plane (C plane is half the size
220 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
221 * chroma plane (C plane is the same size
224 enum pxa_mbus_layout {
225 PXA_MBUS_LAYOUT_PACKED = 0,
226 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
227 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
228 PXA_MBUS_LAYOUT_PLANAR_Y_C,
232 * struct pxa_mbus_pixelfmt - Data format on the media bus
233 * @name: Name of the format
234 * @fourcc: Fourcc code, that will be obtained if the data is
235 * stored in memory in the following way:
236 * @packing: Type of sample-packing, that has to be used
237 * @order: Sample order when storing in memory
238 * @bits_per_sample: How many bits the bridge has to sample
240 struct pxa_mbus_pixelfmt {
243 enum pxa_mbus_packing packing;
244 enum pxa_mbus_order order;
245 enum pxa_mbus_layout layout;
250 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
251 * @code: mediabus pixel-code
252 * @fmt: pixel format description
254 struct pxa_mbus_lookup {
256 struct pxa_mbus_pixelfmt fmt;
259 static const struct pxa_mbus_lookup mbus_fmt[] = {
261 .code = MEDIA_BUS_FMT_YUYV8_2X8,
263 .fourcc = V4L2_PIX_FMT_YUYV,
265 .bits_per_sample = 8,
266 .packing = PXA_MBUS_PACKING_2X8_PADHI,
267 .order = PXA_MBUS_ORDER_LE,
268 .layout = PXA_MBUS_LAYOUT_PACKED,
271 .code = MEDIA_BUS_FMT_YVYU8_2X8,
273 .fourcc = V4L2_PIX_FMT_YVYU,
275 .bits_per_sample = 8,
276 .packing = PXA_MBUS_PACKING_2X8_PADHI,
277 .order = PXA_MBUS_ORDER_LE,
278 .layout = PXA_MBUS_LAYOUT_PACKED,
281 .code = MEDIA_BUS_FMT_UYVY8_2X8,
283 .fourcc = V4L2_PIX_FMT_UYVY,
285 .bits_per_sample = 8,
286 .packing = PXA_MBUS_PACKING_2X8_PADHI,
287 .order = PXA_MBUS_ORDER_LE,
288 .layout = PXA_MBUS_LAYOUT_PACKED,
291 .code = MEDIA_BUS_FMT_VYUY8_2X8,
293 .fourcc = V4L2_PIX_FMT_VYUY,
295 .bits_per_sample = 8,
296 .packing = PXA_MBUS_PACKING_2X8_PADHI,
297 .order = PXA_MBUS_ORDER_LE,
298 .layout = PXA_MBUS_LAYOUT_PACKED,
301 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
303 .fourcc = V4L2_PIX_FMT_RGB555,
305 .bits_per_sample = 8,
306 .packing = PXA_MBUS_PACKING_2X8_PADHI,
307 .order = PXA_MBUS_ORDER_LE,
308 .layout = PXA_MBUS_LAYOUT_PACKED,
311 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
313 .fourcc = V4L2_PIX_FMT_RGB555X,
315 .bits_per_sample = 8,
316 .packing = PXA_MBUS_PACKING_2X8_PADHI,
317 .order = PXA_MBUS_ORDER_BE,
318 .layout = PXA_MBUS_LAYOUT_PACKED,
321 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
323 .fourcc = V4L2_PIX_FMT_RGB565,
325 .bits_per_sample = 8,
326 .packing = PXA_MBUS_PACKING_2X8_PADHI,
327 .order = PXA_MBUS_ORDER_LE,
328 .layout = PXA_MBUS_LAYOUT_PACKED,
331 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
333 .fourcc = V4L2_PIX_FMT_RGB565X,
335 .bits_per_sample = 8,
336 .packing = PXA_MBUS_PACKING_2X8_PADHI,
337 .order = PXA_MBUS_ORDER_BE,
338 .layout = PXA_MBUS_LAYOUT_PACKED,
341 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
343 .fourcc = V4L2_PIX_FMT_SBGGR8,
344 .name = "Bayer 8 BGGR",
345 .bits_per_sample = 8,
346 .packing = PXA_MBUS_PACKING_NONE,
347 .order = PXA_MBUS_ORDER_LE,
348 .layout = PXA_MBUS_LAYOUT_PACKED,
351 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
353 .fourcc = V4L2_PIX_FMT_SGBRG8,
354 .name = "Bayer 8 GBRG",
355 .bits_per_sample = 8,
356 .packing = PXA_MBUS_PACKING_NONE,
357 .order = PXA_MBUS_ORDER_LE,
358 .layout = PXA_MBUS_LAYOUT_PACKED,
361 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
363 .fourcc = V4L2_PIX_FMT_SGRBG8,
364 .name = "Bayer 8 GRBG",
365 .bits_per_sample = 8,
366 .packing = PXA_MBUS_PACKING_NONE,
367 .order = PXA_MBUS_ORDER_LE,
368 .layout = PXA_MBUS_LAYOUT_PACKED,
371 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
373 .fourcc = V4L2_PIX_FMT_SRGGB8,
374 .name = "Bayer 8 RGGB",
375 .bits_per_sample = 8,
376 .packing = PXA_MBUS_PACKING_NONE,
377 .order = PXA_MBUS_ORDER_LE,
378 .layout = PXA_MBUS_LAYOUT_PACKED,
381 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
383 .fourcc = V4L2_PIX_FMT_SBGGR10,
384 .name = "Bayer 10 BGGR",
385 .bits_per_sample = 10,
386 .packing = PXA_MBUS_PACKING_EXTEND16,
387 .order = PXA_MBUS_ORDER_LE,
388 .layout = PXA_MBUS_LAYOUT_PACKED,
391 .code = MEDIA_BUS_FMT_Y8_1X8,
393 .fourcc = V4L2_PIX_FMT_GREY,
395 .bits_per_sample = 8,
396 .packing = PXA_MBUS_PACKING_NONE,
397 .order = PXA_MBUS_ORDER_LE,
398 .layout = PXA_MBUS_LAYOUT_PACKED,
401 .code = MEDIA_BUS_FMT_Y10_1X10,
403 .fourcc = V4L2_PIX_FMT_Y10,
404 .name = "Grey 10bit",
405 .bits_per_sample = 10,
406 .packing = PXA_MBUS_PACKING_EXTEND16,
407 .order = PXA_MBUS_ORDER_LE,
408 .layout = PXA_MBUS_LAYOUT_PACKED,
411 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
413 .fourcc = V4L2_PIX_FMT_SBGGR10,
414 .name = "Bayer 10 BGGR",
415 .bits_per_sample = 8,
416 .packing = PXA_MBUS_PACKING_2X8_PADHI,
417 .order = PXA_MBUS_ORDER_LE,
418 .layout = PXA_MBUS_LAYOUT_PACKED,
421 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
423 .fourcc = V4L2_PIX_FMT_SBGGR10,
424 .name = "Bayer 10 BGGR",
425 .bits_per_sample = 8,
426 .packing = PXA_MBUS_PACKING_2X8_PADHI,
427 .order = PXA_MBUS_ORDER_BE,
428 .layout = PXA_MBUS_LAYOUT_PACKED,
431 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
433 .fourcc = V4L2_PIX_FMT_RGB444,
435 .bits_per_sample = 8,
436 .packing = PXA_MBUS_PACKING_2X8_PADHI,
437 .order = PXA_MBUS_ORDER_BE,
438 .layout = PXA_MBUS_LAYOUT_PACKED,
441 .code = MEDIA_BUS_FMT_UYVY8_1X16,
443 .fourcc = V4L2_PIX_FMT_UYVY,
444 .name = "UYVY 16bit",
445 .bits_per_sample = 16,
446 .packing = PXA_MBUS_PACKING_EXTEND16,
447 .order = PXA_MBUS_ORDER_LE,
448 .layout = PXA_MBUS_LAYOUT_PACKED,
451 .code = MEDIA_BUS_FMT_VYUY8_1X16,
453 .fourcc = V4L2_PIX_FMT_VYUY,
454 .name = "VYUY 16bit",
455 .bits_per_sample = 16,
456 .packing = PXA_MBUS_PACKING_EXTEND16,
457 .order = PXA_MBUS_ORDER_LE,
458 .layout = PXA_MBUS_LAYOUT_PACKED,
461 .code = MEDIA_BUS_FMT_YUYV8_1X16,
463 .fourcc = V4L2_PIX_FMT_YUYV,
464 .name = "YUYV 16bit",
465 .bits_per_sample = 16,
466 .packing = PXA_MBUS_PACKING_EXTEND16,
467 .order = PXA_MBUS_ORDER_LE,
468 .layout = PXA_MBUS_LAYOUT_PACKED,
471 .code = MEDIA_BUS_FMT_YVYU8_1X16,
473 .fourcc = V4L2_PIX_FMT_YVYU,
474 .name = "YVYU 16bit",
475 .bits_per_sample = 16,
476 .packing = PXA_MBUS_PACKING_EXTEND16,
477 .order = PXA_MBUS_ORDER_LE,
478 .layout = PXA_MBUS_LAYOUT_PACKED,
481 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
483 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
484 .name = "Bayer 10 BGGR DPCM 8",
485 .bits_per_sample = 8,
486 .packing = PXA_MBUS_PACKING_NONE,
487 .order = PXA_MBUS_ORDER_LE,
488 .layout = PXA_MBUS_LAYOUT_PACKED,
491 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
493 .fourcc = V4L2_PIX_FMT_SGBRG10,
494 .name = "Bayer 10 GBRG",
495 .bits_per_sample = 10,
496 .packing = PXA_MBUS_PACKING_EXTEND16,
497 .order = PXA_MBUS_ORDER_LE,
498 .layout = PXA_MBUS_LAYOUT_PACKED,
501 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
503 .fourcc = V4L2_PIX_FMT_SGRBG10,
504 .name = "Bayer 10 GRBG",
505 .bits_per_sample = 10,
506 .packing = PXA_MBUS_PACKING_EXTEND16,
507 .order = PXA_MBUS_ORDER_LE,
508 .layout = PXA_MBUS_LAYOUT_PACKED,
511 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
513 .fourcc = V4L2_PIX_FMT_SRGGB10,
514 .name = "Bayer 10 RGGB",
515 .bits_per_sample = 10,
516 .packing = PXA_MBUS_PACKING_EXTEND16,
517 .order = PXA_MBUS_ORDER_LE,
518 .layout = PXA_MBUS_LAYOUT_PACKED,
521 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
523 .fourcc = V4L2_PIX_FMT_SBGGR12,
524 .name = "Bayer 12 BGGR",
525 .bits_per_sample = 12,
526 .packing = PXA_MBUS_PACKING_EXTEND16,
527 .order = PXA_MBUS_ORDER_LE,
528 .layout = PXA_MBUS_LAYOUT_PACKED,
531 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
533 .fourcc = V4L2_PIX_FMT_SGBRG12,
534 .name = "Bayer 12 GBRG",
535 .bits_per_sample = 12,
536 .packing = PXA_MBUS_PACKING_EXTEND16,
537 .order = PXA_MBUS_ORDER_LE,
538 .layout = PXA_MBUS_LAYOUT_PACKED,
541 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
543 .fourcc = V4L2_PIX_FMT_SGRBG12,
544 .name = "Bayer 12 GRBG",
545 .bits_per_sample = 12,
546 .packing = PXA_MBUS_PACKING_EXTEND16,
547 .order = PXA_MBUS_ORDER_LE,
548 .layout = PXA_MBUS_LAYOUT_PACKED,
551 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
553 .fourcc = V4L2_PIX_FMT_SRGGB12,
554 .name = "Bayer 12 RGGB",
555 .bits_per_sample = 12,
556 .packing = PXA_MBUS_PACKING_EXTEND16,
557 .order = PXA_MBUS_ORDER_LE,
558 .layout = PXA_MBUS_LAYOUT_PACKED,
563 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
565 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
566 return width * mf->bits_per_sample / 8;
568 switch (mf->packing) {
569 case PXA_MBUS_PACKING_NONE:
570 return width * mf->bits_per_sample / 8;
571 case PXA_MBUS_PACKING_2X8_PADHI:
572 case PXA_MBUS_PACKING_EXTEND16:
578 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
579 u32 bytes_per_line, u32 height)
581 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
582 return bytes_per_line * height;
584 switch (mf->packing) {
585 case PXA_MBUS_PACKING_2X8_PADHI:
586 return bytes_per_line * height * 2;
592 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
594 const struct pxa_mbus_lookup *lookup,
599 for (i = 0; i < n; i++)
600 if (lookup[i].code == code)
601 return &lookup[i].fmt;
606 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
609 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
612 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
615 unsigned long common_flags;
616 bool hsync = true, vsync = true, pclk, data, mode;
617 bool mipi_lanes, mipi_clock;
619 common_flags = cfg->flags & flags;
622 case V4L2_MBUS_PARALLEL:
623 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
624 V4L2_MBUS_HSYNC_ACTIVE_LOW);
625 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
626 V4L2_MBUS_VSYNC_ACTIVE_LOW);
628 case V4L2_MBUS_BT656:
629 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
630 V4L2_MBUS_PCLK_SAMPLE_FALLING);
631 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
632 V4L2_MBUS_DATA_ACTIVE_LOW);
633 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
634 return (!hsync || !vsync || !pclk || !data || !mode) ?
637 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
638 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
639 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
640 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
649 * struct soc_camera_format_xlate - match between host and sensor formats
650 * @code: code of a sensor provided format
651 * @host_fmt: host format after host translation from code
653 * Host and sensor translation structure. Used in table of host and sensor
654 * formats matchings in soc_camera_device. A host can override the generic list
655 * generation by implementing get_formats(), and use it for format checks and
658 struct soc_camera_format_xlate {
660 const struct pxa_mbus_pixelfmt *host_fmt;
666 enum pxa_camera_active_dma {
672 /* buffer for one video frame */
674 /* common v4l buffer stuff -- must be first */
675 struct vb2_v4l2_buffer vbuf;
676 struct list_head queue;
679 /* our descriptor lists for Y, U and V channels */
680 struct dma_async_tx_descriptor *descs[3];
681 dma_cookie_t cookie[3];
682 struct scatterlist *sg[3];
684 size_t plane_sizes[3];
686 enum pxa_camera_active_dma active_dma;
689 struct pxa_camera_dev {
690 struct v4l2_device v4l2_dev;
691 struct video_device vdev;
692 struct v4l2_async_notifier notifier;
693 struct vb2_queue vb2_vq;
694 struct v4l2_subdev *sensor;
695 struct soc_camera_format_xlate *user_formats;
696 const struct soc_camera_format_xlate *current_fmt;
697 struct v4l2_pix_format current_pix;
699 struct v4l2_async_subdev asd;
700 struct v4l2_async_subdev *asds[1];
703 * PXA27x is only supposed to handle one camera on its Quick Capture
704 * interface. If anyone ever builds hardware to enable more than
705 * one camera, they will have to modify this driver too
713 struct dma_chan *dma_chans[3];
715 struct pxacamera_platform_data *pdata;
716 struct resource *res;
717 unsigned long platform_flags;
721 struct v4l2_clk *mclk_clk;
722 u16 width_flags; /* max 10 bits */
724 struct list_head capture;
728 unsigned int buf_sequence;
730 struct pxa_buffer *active;
731 struct tasklet_struct task_eof;
740 static const char *pxa_cam_driver_description = "PXA_Camera";
743 * Format translation functions
745 static const struct soc_camera_format_xlate
746 *pxa_mbus_xlate_by_fourcc(struct soc_camera_format_xlate *user_formats,
751 for (i = 0; user_formats[i].code; i++)
752 if (user_formats[i].host_fmt->fourcc == fourcc)
753 return user_formats + i;
757 static struct soc_camera_format_xlate *pxa_mbus_build_fmts_xlate(
758 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
759 int (*get_formats)(struct v4l2_device *, unsigned int,
760 struct soc_camera_format_xlate *xlate))
762 unsigned int i, fmts = 0, raw_fmts = 0;
764 struct v4l2_subdev_mbus_code_enum code = {
765 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
767 struct soc_camera_format_xlate *user_formats;
769 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
775 * First pass - only count formats this host-sensor
776 * configuration can provide
778 for (i = 0; i < raw_fmts; i++) {
779 ret = get_formats(v4l2_dev, i, NULL);
786 return ERR_PTR(-ENXIO);
788 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
790 return ERR_PTR(-ENOMEM);
792 /* Second pass - actually fill data formats */
794 for (i = 0; i < raw_fmts; i++) {
795 ret = get_formats(v4l2_dev, i, user_formats + fmts);
800 user_formats[fmts].code = 0;
809 * Videobuf operations
811 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
813 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
815 return container_of(vbuf, struct pxa_buffer, vbuf);
818 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
820 return pcdev->v4l2_dev.dev;
823 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
825 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
828 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
829 enum pxa_camera_active_dma act_dma);
831 static void pxa_camera_dma_irq_y(void *data)
833 struct pxa_camera_dev *pcdev = data;
835 pxa_camera_dma_irq(pcdev, DMA_Y);
838 static void pxa_camera_dma_irq_u(void *data)
840 struct pxa_camera_dev *pcdev = data;
842 pxa_camera_dma_irq(pcdev, DMA_U);
845 static void pxa_camera_dma_irq_v(void *data)
847 struct pxa_camera_dev *pcdev = data;
849 pxa_camera_dma_irq(pcdev, DMA_V);
853 * pxa_init_dma_channel - init dma descriptors
854 * @pcdev: pxa camera device
855 * @vb: videobuffer2 buffer
856 * @dma: dma video buffer
857 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
858 * @cibr: camera Receive Buffer Register
860 * Prepares the pxa dma descriptors to transfer one camera channel.
862 * Returns 0 if success or -ENOMEM if no memory is available
864 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
865 struct pxa_buffer *buf, int channel,
866 struct scatterlist *sg, int sglen)
868 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
869 struct dma_async_tx_descriptor *tx;
871 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
872 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
874 dev_err(pcdev_to_dev(pcdev),
875 "dmaengine_prep_slave_sg failed\n");
879 tx->callback_param = pcdev;
882 tx->callback = pxa_camera_dma_irq_y;
885 tx->callback = pxa_camera_dma_irq_u;
888 tx->callback = pxa_camera_dma_irq_v;
892 buf->descs[channel] = tx;
895 dev_dbg(pcdev_to_dev(pcdev),
896 "%s (vb=%p) dma_tx=%p\n",
902 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
903 struct pxa_buffer *buf)
905 buf->active_dma = DMA_Y;
906 if (buf->nb_planes == 3)
907 buf->active_dma |= DMA_U | DMA_V;
911 * pxa_dma_start_channels - start DMA channel for active buffer
912 * @pcdev: pxa camera device
914 * Initialize DMA channels to the beginning of the active video buffer, and
915 * start these channels.
917 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
921 for (i = 0; i < pcdev->channels; i++) {
922 dev_dbg(pcdev_to_dev(pcdev),
923 "%s (channel=%d)\n", __func__, i);
924 dma_async_issue_pending(pcdev->dma_chans[i]);
928 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
932 for (i = 0; i < pcdev->channels; i++) {
933 dev_dbg(pcdev_to_dev(pcdev),
934 "%s (channel=%d)\n", __func__, i);
935 dmaengine_terminate_all(pcdev->dma_chans[i]);
939 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
940 struct pxa_buffer *buf)
944 for (i = 0; i < pcdev->channels; i++) {
945 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
946 dev_dbg(pcdev_to_dev(pcdev),
947 "%s (channel=%d) : submit vb=%p cookie=%d\n",
948 __func__, i, buf, buf->descs[i]->cookie);
953 * pxa_camera_start_capture - start video capturing
954 * @pcdev: camera device
956 * Launch capturing. DMA channels should not be active yet. They should get
957 * activated at the end of frame interrupt, to capture only whole frames, and
958 * never begin the capture of a partial frame.
960 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
964 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
965 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
966 /* Enable End-Of-Frame Interrupt */
967 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
968 cicr0 &= ~CICR0_EOFM;
969 __raw_writel(cicr0, pcdev->base + CICR0);
972 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
976 pxa_dma_stop_channels(pcdev);
978 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
979 __raw_writel(cicr0, pcdev->base + CICR0);
981 pcdev->active = NULL;
982 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
985 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
986 struct pxa_buffer *buf,
987 enum vb2_buffer_state state)
989 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
990 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
992 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
993 list_del_init(&buf->queue);
994 vb->timestamp = ktime_get_ns();
995 vbuf->sequence = pcdev->buf_sequence++;
996 vbuf->field = V4L2_FIELD_NONE;
997 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
998 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
1001 if (list_empty(&pcdev->capture)) {
1002 pxa_camera_stop_capture(pcdev);
1006 pcdev->active = list_entry(pcdev->capture.next,
1007 struct pxa_buffer, queue);
1011 * pxa_camera_check_link_miss - check missed DMA linking
1012 * @pcdev: camera device
1014 * The DMA chaining is done with DMA running. This means a tiny temporal window
1015 * remains, where a buffer is queued on the chain, while the chain is already
1016 * stopped. This means the tailed buffer would never be transferred by DMA.
1017 * This function restarts the capture for this corner case, where :
1018 * - DADR() == DADDR_STOP
1019 * - a videobuffer is queued on the pcdev->capture list
1021 * Please check the "DMA hot chaining timeslice issue" in
1022 * Documentation/video4linux/pxa_camera.txt
1024 * Context: should only be called within the dma irq handler
1026 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
1027 dma_cookie_t last_submitted,
1028 dma_cookie_t last_issued)
1030 bool is_dma_stopped = last_submitted != last_issued;
1032 dev_dbg(pcdev_to_dev(pcdev),
1033 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1034 __func__, pcdev->active, is_dma_stopped);
1036 if (pcdev->active && is_dma_stopped)
1037 pxa_camera_start_capture(pcdev);
1040 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1041 enum pxa_camera_active_dma act_dma)
1043 struct pxa_buffer *buf, *last_buf;
1044 unsigned long flags;
1045 u32 camera_status, overrun;
1047 enum dma_status last_status;
1048 dma_cookie_t last_issued;
1050 spin_lock_irqsave(&pcdev->lock, flags);
1052 camera_status = __raw_readl(pcdev->base + CISR);
1053 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1054 camera_status, act_dma);
1055 overrun = CISR_IFO_0;
1056 if (pcdev->channels == 3)
1057 overrun |= CISR_IFO_1 | CISR_IFO_2;
1060 * pcdev->active should not be NULL in DMA irq handler.
1062 * But there is one corner case : if capture was stopped due to an
1063 * overrun of channel 1, and at that same channel 2 was completed.
1065 * When handling the overrun in DMA irq for channel 1, we'll stop the
1066 * capture and restart it (and thus set pcdev->active to NULL). But the
1067 * DMA irq handler will already be pending for channel 2. So on entering
1068 * the DMA irq handler for channel 2 there will be no active buffer, yet
1074 buf = pcdev->active;
1075 WARN_ON(buf->inwork || list_empty(&buf->queue));
1078 * It's normal if the last frame creates an overrun, as there
1079 * are no more DMA descriptors to fetch from QCI fifos
1092 last_buf = list_entry(pcdev->capture.prev,
1093 struct pxa_buffer, queue);
1094 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1095 last_buf->cookie[chan],
1096 NULL, &last_issued);
1097 if (camera_status & overrun &&
1098 last_status != DMA_COMPLETE) {
1099 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1101 pxa_camera_stop_capture(pcdev);
1102 list_for_each_entry(buf, &pcdev->capture, queue)
1103 pxa_dma_add_tail_buf(pcdev, buf);
1104 pxa_camera_start_capture(pcdev);
1107 buf->active_dma &= ~act_dma;
1108 if (!buf->active_dma) {
1109 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1110 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1115 spin_unlock_irqrestore(&pcdev->lock, flags);
1118 static u32 mclk_get_divisor(struct platform_device *pdev,
1119 struct pxa_camera_dev *pcdev)
1121 unsigned long mclk = pcdev->mclk;
1123 unsigned long lcdclk;
1125 lcdclk = clk_get_rate(pcdev->clk);
1126 pcdev->ciclk = lcdclk;
1128 /* mclk <= ciclk / 4 (27.4.2) */
1129 if (mclk > lcdclk / 4) {
1131 dev_warn(&pdev->dev,
1132 "Limiting master clock to %lu\n", mclk);
1135 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1136 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1138 /* If we're not supplying MCLK, leave it at 0 */
1139 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1140 pcdev->mclk = lcdclk / (2 * (div + 1));
1142 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1148 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1151 /* We want a timeout > 1 pixel time, not ">=" */
1152 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1154 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1157 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1161 /* disable all interrupts */
1162 __raw_writel(0x3ff, pcdev->base + CICR0);
1164 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1165 cicr4 |= CICR4_PCLK_EN;
1166 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1167 cicr4 |= CICR4_MCLK_EN;
1168 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1170 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1172 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1175 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1177 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1178 /* Initialise the timeout under the assumption pclk = mclk */
1179 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1181 /* "Safe default" - 13MHz */
1182 recalculate_fifo_timeout(pcdev, 13000000);
1184 clk_prepare_enable(pcdev->clk);
1187 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1189 clk_disable_unprepare(pcdev->clk);
1192 static void pxa_camera_eof(unsigned long arg)
1194 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1196 struct pxa_buffer *buf;
1198 dev_dbg(pcdev_to_dev(pcdev),
1199 "Camera interrupt status 0x%x\n",
1200 __raw_readl(pcdev->base + CISR));
1202 /* Reset the FIFOs */
1203 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1204 __raw_writel(cifr, pcdev->base + CIFR);
1206 pcdev->active = list_first_entry(&pcdev->capture,
1207 struct pxa_buffer, queue);
1208 buf = pcdev->active;
1209 pxa_videobuf_set_actdma(pcdev, buf);
1211 pxa_dma_start_channels(pcdev);
1214 static irqreturn_t pxa_camera_irq(int irq, void *data)
1216 struct pxa_camera_dev *pcdev = data;
1217 unsigned long status, cicr0;
1219 status = __raw_readl(pcdev->base + CISR);
1220 dev_dbg(pcdev_to_dev(pcdev),
1221 "Camera interrupt status 0x%lx\n", status);
1226 __raw_writel(status, pcdev->base + CISR);
1228 if (status & CISR_EOF) {
1229 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1230 __raw_writel(cicr0, pcdev->base + CICR0);
1231 tasklet_schedule(&pcdev->task_eof);
1237 static int test_platform_param(struct pxa_camera_dev *pcdev,
1238 unsigned char buswidth, unsigned long *flags)
1241 * Platform specified synchronization and pixel clock polarities are
1242 * only a recommendation and are only used during probing. The PXA270
1243 * quick capture interface supports both.
1245 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1246 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1247 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1248 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1249 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1250 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1251 V4L2_MBUS_DATA_ACTIVE_HIGH |
1252 V4L2_MBUS_PCLK_SAMPLE_RISING |
1253 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1255 /* If requested data width is supported by the platform, use it */
1256 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1262 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1263 unsigned long flags, __u32 pixfmt)
1265 unsigned long dw, bpp;
1266 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1267 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1273 * Datawidth is now guaranteed to be equal to one of the three values.
1274 * We fix bit-per-pixel equal to data-width...
1276 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1287 * Actually it can only be 8 now,
1288 * default is just to silence compiler warnings
1295 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1296 cicr4 |= CICR4_PCLK_EN;
1297 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1298 cicr4 |= CICR4_MCLK_EN;
1299 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1301 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1303 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1306 cicr0 = __raw_readl(pcdev->base + CICR0);
1307 if (cicr0 & CICR0_ENB)
1308 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1310 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1313 case V4L2_PIX_FMT_YUV422P:
1314 pcdev->channels = 3;
1315 cicr1 |= CICR1_YCBCR_F;
1317 * Normally, pxa bus wants as input UYVY format. We allow all
1318 * reorderings of the YUV422 format, as no processing is done,
1319 * and the YUV stream is just passed through without any
1320 * transformation. Note that UYVY is the only format that
1321 * should be used if pxa framebuffer Overlay2 is used.
1324 case V4L2_PIX_FMT_UYVY:
1325 case V4L2_PIX_FMT_VYUY:
1326 case V4L2_PIX_FMT_YUYV:
1327 case V4L2_PIX_FMT_YVYU:
1328 cicr1 |= CICR1_COLOR_SP_VAL(2);
1330 case V4L2_PIX_FMT_RGB555:
1331 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1332 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1334 case V4L2_PIX_FMT_RGB565:
1335 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1340 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1341 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1342 cicr4 |= pcdev->mclk_divisor;
1344 __raw_writel(cicr1, pcdev->base + CICR1);
1345 __raw_writel(cicr2, pcdev->base + CICR2);
1346 __raw_writel(cicr3, pcdev->base + CICR3);
1347 __raw_writel(cicr4, pcdev->base + CICR4);
1349 /* CIF interrupts are not used, only DMA */
1350 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1351 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1352 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1353 __raw_writel(cicr0, pcdev->base + CICR0);
1359 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1363 for (i = 0; i < 3 && buf->descs[i]; i++) {
1364 dmaengine_desc_free(buf->descs[i]);
1366 buf->descs[i] = NULL;
1369 buf->plane_sizes[i] = 0;
1374 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1375 struct pxa_buffer *buf)
1377 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1378 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1379 int nb_channels = pcdev->channels;
1381 unsigned long size = vb2_plane_size(vb, 0);
1383 switch (nb_channels) {
1385 buf->plane_sizes[0] = size;
1388 buf->plane_sizes[0] = size / 2;
1389 buf->plane_sizes[1] = size / 4;
1390 buf->plane_sizes[2] = size / 4;
1395 buf->nb_planes = nb_channels;
1397 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1398 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1400 dev_err(pcdev_to_dev(pcdev),
1401 "sg_split failed: %d\n", ret);
1404 for (i = 0; i < nb_channels; i++) {
1405 ret = pxa_init_dma_channel(pcdev, buf, i,
1406 buf->sg[i], buf->sg_len[i]);
1408 pxa_buffer_cleanup(buf);
1412 INIT_LIST_HEAD(&buf->queue);
1417 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1419 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1420 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1422 dev_dbg(pcdev_to_dev(pcdev),
1423 "%s(vb=%p)\n", __func__, vb);
1424 pxa_buffer_cleanup(buf);
1427 static void pxac_vb2_queue(struct vb2_buffer *vb)
1429 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1430 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1432 dev_dbg(pcdev_to_dev(pcdev),
1433 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1434 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1437 list_add_tail(&buf->queue, &pcdev->capture);
1439 pxa_dma_add_tail_buf(pcdev, buf);
1443 * Please check the DMA prepared buffer structure in :
1444 * Documentation/video4linux/pxa_camera.txt
1445 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1446 * modification while DMA chain is running will work anyway.
1448 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1450 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1451 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1457 switch (pcdev->channels) {
1460 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1466 dev_dbg(pcdev_to_dev(pcdev),
1467 "%s (vb=%p) nb_channels=%d size=%lu\n",
1468 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1470 WARN_ON(!pcdev->current_fmt);
1474 * This can be useful if you want to see if we actually fill
1475 * the buffer with something
1477 for (i = 0; i < vb->num_planes; i++)
1478 memset((void *)vb2_plane_vaddr(vb, i),
1479 0xaa, vb2_get_plane_payload(vb, i));
1483 * I think, in buf_prepare you only have to protect global data,
1484 * the actual buffer is yours
1487 pxa_videobuf_set_actdma(pcdev, buf);
1492 static int pxac_vb2_init(struct vb2_buffer *vb)
1494 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1495 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1497 dev_dbg(pcdev_to_dev(pcdev),
1498 "%s(nb_channels=%d)\n",
1499 __func__, pcdev->channels);
1501 return pxa_buffer_init(pcdev, buf);
1504 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1505 unsigned int *nbufs,
1506 unsigned int *num_planes, unsigned int sizes[],
1507 struct device *alloc_devs[])
1509 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1510 int size = pcdev->current_pix.sizeimage;
1512 dev_dbg(pcdev_to_dev(pcdev),
1513 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1514 __func__, vq, *nbufs, *num_planes, size);
1516 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1517 * format, even if there are 3 planes Y, U and V, we reply there is only
1518 * one plane, containing Y, U and V data, one after the other.
1521 return sizes[0] < size ? -EINVAL : 0;
1524 switch (pcdev->channels) {
1539 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1541 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1543 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1544 __func__, count, pcdev->active);
1546 pcdev->buf_sequence = 0;
1548 pxa_camera_start_capture(pcdev);
1553 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1555 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1556 struct pxa_buffer *buf, *tmp;
1558 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1559 __func__, pcdev->active);
1560 pxa_camera_stop_capture(pcdev);
1562 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1563 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1566 static const struct vb2_ops pxac_vb2_ops = {
1567 .queue_setup = pxac_vb2_queue_setup,
1568 .buf_init = pxac_vb2_init,
1569 .buf_prepare = pxac_vb2_prepare,
1570 .buf_queue = pxac_vb2_queue,
1571 .buf_cleanup = pxac_vb2_cleanup,
1572 .start_streaming = pxac_vb2_start_streaming,
1573 .stop_streaming = pxac_vb2_stop_streaming,
1574 .wait_prepare = vb2_ops_wait_prepare,
1575 .wait_finish = vb2_ops_wait_finish,
1578 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1581 struct vb2_queue *vq = &pcdev->vb2_vq;
1583 memset(vq, 0, sizeof(*vq));
1584 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1585 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1586 vq->drv_priv = pcdev;
1587 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1588 vq->buf_struct_size = sizeof(struct pxa_buffer);
1589 vq->dev = pcdev->v4l2_dev.dev;
1591 vq->ops = &pxac_vb2_ops;
1592 vq->mem_ops = &vb2_dma_sg_memops;
1593 vq->lock = &pcdev->mlock;
1595 ret = vb2_queue_init(vq);
1596 dev_dbg(pcdev_to_dev(pcdev),
1597 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1603 * Video ioctls section
1605 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1607 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1608 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1609 unsigned long bus_flags, common_flags;
1612 ret = test_platform_param(pcdev,
1613 pcdev->current_fmt->host_fmt->bits_per_sample,
1618 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1620 common_flags = pxa_mbus_config_compatible(&cfg,
1622 if (!common_flags) {
1623 dev_warn(pcdev_to_dev(pcdev),
1624 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1625 cfg.flags, bus_flags);
1628 } else if (ret != -ENOIOCTLCMD) {
1631 common_flags = bus_flags;
1634 pcdev->channels = 1;
1636 /* Make choises, based on platform preferences */
1637 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1638 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1639 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1640 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1642 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1645 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1646 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1647 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1648 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1650 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1653 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1654 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1655 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1656 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1658 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1661 cfg.flags = common_flags;
1662 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1663 if (ret < 0 && ret != -ENOIOCTLCMD) {
1664 dev_dbg(pcdev_to_dev(pcdev),
1665 "camera s_mbus_config(0x%lx) returned %d\n",
1670 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1675 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1676 unsigned char buswidth)
1678 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1679 unsigned long bus_flags, common_flags;
1680 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1685 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1687 common_flags = pxa_mbus_config_compatible(&cfg,
1689 if (!common_flags) {
1690 dev_warn(pcdev_to_dev(pcdev),
1691 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1692 cfg.flags, bus_flags);
1695 } else if (ret == -ENOIOCTLCMD) {
1702 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1704 .fourcc = V4L2_PIX_FMT_YUV422P,
1705 .name = "Planar YUV422 16 bit",
1706 .bits_per_sample = 8,
1707 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1708 .order = PXA_MBUS_ORDER_LE,
1709 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1713 /* This will be corrected as we get more formats */
1714 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1716 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1717 (fmt->bits_per_sample == 8 &&
1718 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1719 (fmt->bits_per_sample > 8 &&
1720 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1723 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1725 struct soc_camera_format_xlate *xlate)
1727 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1728 int formats = 0, ret;
1729 struct v4l2_subdev_mbus_code_enum code = {
1730 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1733 const struct pxa_mbus_pixelfmt *fmt;
1735 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1737 /* No more formats */
1740 fmt = pxa_mbus_get_fmtdesc(code.code);
1742 dev_err(pcdev_to_dev(pcdev),
1743 "Invalid format code #%u: %d\n", idx, code.code);
1747 /* This also checks support for the requested bits-per-sample */
1748 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1752 switch (code.code) {
1753 case MEDIA_BUS_FMT_UYVY8_2X8:
1756 xlate->host_fmt = &pxa_camera_formats[0];
1757 xlate->code = code.code;
1759 dev_dbg(pcdev_to_dev(pcdev),
1760 "Providing format %s using code %d\n",
1761 pxa_camera_formats[0].name, code.code);
1764 case MEDIA_BUS_FMT_VYUY8_2X8:
1765 case MEDIA_BUS_FMT_YUYV8_2X8:
1766 case MEDIA_BUS_FMT_YVYU8_2X8:
1767 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1768 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1770 dev_dbg(pcdev_to_dev(pcdev),
1771 "Providing format %s packed\n",
1775 if (!pxa_camera_packing_supported(fmt))
1778 dev_dbg(pcdev_to_dev(pcdev),
1779 "Providing format %s in pass-through mode\n",
1784 /* Generic pass-through */
1787 xlate->host_fmt = fmt;
1788 xlate->code = code.code;
1795 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1797 struct soc_camera_format_xlate *xlate;
1799 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1800 pxa_camera_get_formats);
1802 return PTR_ERR(xlate);
1804 pcdev->user_formats = xlate;
1808 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1810 kfree(pcdev->user_formats);
1813 static int pxa_camera_check_frame(u32 width, u32 height)
1815 /* limit to pxa hardware capabilities */
1816 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1820 #ifdef CONFIG_VIDEO_ADV_DEBUG
1821 static int pxac_vidioc_g_register(struct file *file, void *priv,
1822 struct v4l2_dbg_register *reg)
1824 struct pxa_camera_dev *pcdev = video_drvdata(file);
1826 if (reg->reg > CIBR2)
1829 reg->val = __raw_readl(pcdev->base + reg->reg);
1830 reg->size = sizeof(__u32);
1834 static int pxac_vidioc_s_register(struct file *file, void *priv,
1835 const struct v4l2_dbg_register *reg)
1837 struct pxa_camera_dev *pcdev = video_drvdata(file);
1839 if (reg->reg > CIBR2)
1841 if (reg->size != sizeof(__u32))
1843 __raw_writel(reg->val, pcdev->base + reg->reg);
1848 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1849 struct v4l2_fmtdesc *f)
1851 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1852 const struct pxa_mbus_pixelfmt *format;
1855 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1856 if (f->index >= idx)
1859 format = pcdev->user_formats[f->index].host_fmt;
1860 f->pixelformat = format->fourcc;
1864 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1865 struct v4l2_format *f)
1867 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1868 struct v4l2_pix_format *pix = &f->fmt.pix;
1870 pix->width = pcdev->current_pix.width;
1871 pix->height = pcdev->current_pix.height;
1872 pix->bytesperline = pcdev->current_pix.bytesperline;
1873 pix->sizeimage = pcdev->current_pix.sizeimage;
1874 pix->field = pcdev->current_pix.field;
1875 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1876 pix->colorspace = pcdev->current_pix.colorspace;
1877 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1878 pcdev->current_fmt->host_fmt->fourcc);
1882 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1883 struct v4l2_format *f)
1885 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1886 const struct soc_camera_format_xlate *xlate;
1887 struct v4l2_pix_format *pix = &f->fmt.pix;
1888 struct v4l2_subdev_pad_config pad_cfg;
1889 struct v4l2_subdev_format format = {
1890 .which = V4L2_SUBDEV_FORMAT_TRY,
1892 struct v4l2_mbus_framefmt *mf = &format.format;
1893 __u32 pixfmt = pix->pixelformat;
1896 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1898 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1903 * Limit to pxa hardware capabilities. YUV422P planar format requires
1904 * images size to be a multiple of 16 bytes. If not, zeros will be
1905 * inserted between Y and U planes, and U and V planes, which violates
1906 * the YUV422P standard.
1908 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1909 &pix->height, 32, 2048, 0,
1910 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1912 v4l2_fill_mbus_format(mf, pix, xlate->code);
1913 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1917 v4l2_fill_pix_format(pix, mf);
1919 /* Only progressive video supported so far */
1920 switch (mf->field) {
1921 case V4L2_FIELD_ANY:
1922 case V4L2_FIELD_NONE:
1923 pix->field = V4L2_FIELD_NONE;
1926 /* TODO: support interlaced at least in pass-through mode */
1927 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1932 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1936 pix->bytesperline = ret;
1937 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1942 pix->sizeimage = ret;
1946 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1947 struct v4l2_format *f)
1949 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1950 const struct soc_camera_format_xlate *xlate;
1951 struct v4l2_pix_format *pix = &f->fmt.pix;
1952 struct v4l2_subdev_format format = {
1953 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1955 unsigned long flags;
1958 dev_dbg(pcdev_to_dev(pcdev),
1959 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1960 pix->width, pix->height, pix->pixelformat);
1962 spin_lock_irqsave(&pcdev->lock, flags);
1963 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1964 spin_unlock_irqrestore(&pcdev->lock, flags);
1969 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1973 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1975 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1976 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1978 dev_warn(pcdev_to_dev(pcdev),
1979 "Failed to configure for format %x\n",
1981 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1982 dev_warn(pcdev_to_dev(pcdev),
1983 "Camera driver produced an unsupported frame %dx%d\n",
1984 pix->width, pix->height);
1988 pcdev->current_fmt = xlate;
1989 pcdev->current_pix = *pix;
1991 ret = pxa_camera_set_bus_param(pcdev);
1995 static int pxac_vidioc_querycap(struct file *file, void *priv,
1996 struct v4l2_capability *cap)
1998 strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1999 strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
2000 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
2001 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
2002 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
2007 static int pxac_vidioc_enum_input(struct file *file, void *priv,
2008 struct v4l2_input *i)
2013 i->type = V4L2_INPUT_TYPE_CAMERA;
2014 strlcpy(i->name, "Camera", sizeof(i->name));
2019 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
2026 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
2034 static int pxac_fops_camera_open(struct file *filp)
2036 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2039 mutex_lock(&pcdev->mlock);
2040 ret = v4l2_fh_open(filp);
2044 ret = sensor_call(pcdev, core, s_power, 1);
2046 v4l2_fh_release(filp);
2048 mutex_unlock(&pcdev->mlock);
2052 static int pxac_fops_camera_release(struct file *filp)
2054 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2057 ret = vb2_fop_release(filp);
2061 mutex_lock(&pcdev->mlock);
2062 ret = sensor_call(pcdev, core, s_power, 0);
2063 mutex_unlock(&pcdev->mlock);
2068 static const struct v4l2_file_operations pxa_camera_fops = {
2069 .owner = THIS_MODULE,
2070 .open = pxac_fops_camera_open,
2071 .release = pxac_fops_camera_release,
2072 .read = vb2_fop_read,
2073 .poll = vb2_fop_poll,
2074 .mmap = vb2_fop_mmap,
2075 .unlocked_ioctl = video_ioctl2,
2078 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2079 .vidioc_querycap = pxac_vidioc_querycap,
2081 .vidioc_enum_input = pxac_vidioc_enum_input,
2082 .vidioc_g_input = pxac_vidioc_g_input,
2083 .vidioc_s_input = pxac_vidioc_s_input,
2085 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2086 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2087 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2088 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2090 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2091 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2092 .vidioc_querybuf = vb2_ioctl_querybuf,
2093 .vidioc_qbuf = vb2_ioctl_qbuf,
2094 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2095 .vidioc_expbuf = vb2_ioctl_expbuf,
2096 .vidioc_streamon = vb2_ioctl_streamon,
2097 .vidioc_streamoff = vb2_ioctl_streamoff,
2098 #ifdef CONFIG_VIDEO_ADV_DEBUG
2099 .vidioc_g_register = pxac_vidioc_g_register,
2100 .vidioc_s_register = pxac_vidioc_s_register,
2102 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2103 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2106 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2109 static const struct video_device pxa_camera_videodev_template = {
2110 .name = "pxa-camera",
2112 .fops = &pxa_camera_fops,
2113 .ioctl_ops = &pxa_camera_ioctl_ops,
2114 .release = video_device_release_empty,
2115 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2118 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2119 struct v4l2_subdev *subdev,
2120 struct v4l2_async_subdev *asd)
2123 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2124 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2125 struct video_device *vdev = &pcdev->vdev;
2126 struct v4l2_pix_format *pix = &pcdev->current_pix;
2127 struct v4l2_subdev_format format = {
2128 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2130 struct v4l2_mbus_framefmt *mf = &format.format;
2132 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2134 mutex_lock(&pcdev->mlock);
2135 *vdev = pxa_camera_videodev_template;
2136 vdev->v4l2_dev = v4l2_dev;
2137 vdev->lock = &pcdev->mlock;
2138 pcdev->sensor = subdev;
2139 pcdev->vdev.queue = &pcdev->vb2_vq;
2140 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2141 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2142 video_set_drvdata(&pcdev->vdev, pcdev);
2144 err = pxa_camera_build_formats(pcdev);
2146 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2151 pcdev->current_fmt = pcdev->user_formats;
2152 pix->field = V4L2_FIELD_NONE;
2153 pix->width = DEFAULT_WIDTH;
2154 pix->height = DEFAULT_HEIGHT;
2156 pxa_mbus_bytes_per_line(pix->width,
2157 pcdev->current_fmt->host_fmt);
2159 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2160 pix->bytesperline, pix->height);
2161 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2162 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2164 err = sensor_call(pcdev, core, s_power, 1);
2168 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2170 goto out_sensor_poweroff;
2172 v4l2_fill_pix_format(pix, mf);
2173 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2174 __func__, pix->colorspace, pix->pixelformat);
2176 err = pxa_camera_init_videobuf2(pcdev);
2178 goto out_sensor_poweroff;
2180 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2182 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2183 pcdev->sensor = NULL;
2185 dev_info(pcdev_to_dev(pcdev),
2186 "PXA Camera driver attached to camera %s\n",
2190 out_sensor_poweroff:
2191 err = sensor_call(pcdev, core, s_power, 0);
2193 mutex_unlock(&pcdev->mlock);
2197 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2198 struct v4l2_subdev *subdev,
2199 struct v4l2_async_subdev *asd)
2201 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2203 mutex_lock(&pcdev->mlock);
2204 dev_info(pcdev_to_dev(pcdev),
2205 "PXA Camera driver detached from camera %s\n",
2208 /* disable capture, disable interrupts */
2209 __raw_writel(0x3ff, pcdev->base + CICR0);
2211 /* Stop DMA engine */
2212 pxa_dma_stop_channels(pcdev);
2214 pxa_camera_destroy_formats(pcdev);
2216 if (pcdev->mclk_clk) {
2217 v4l2_clk_unregister(pcdev->mclk_clk);
2218 pcdev->mclk_clk = NULL;
2221 video_unregister_device(&pcdev->vdev);
2222 pcdev->sensor = NULL;
2224 mutex_unlock(&pcdev->mlock);
2228 * Driver probe, remove, suspend and resume operations
2230 static int pxa_camera_suspend(struct device *dev)
2232 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2235 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2236 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2237 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2238 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2239 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2241 if (pcdev->sensor) {
2242 ret = sensor_call(pcdev, core, s_power, 0);
2243 if (ret == -ENOIOCTLCMD)
2250 static int pxa_camera_resume(struct device *dev)
2252 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2255 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2256 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2257 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2258 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2259 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2261 if (pcdev->sensor) {
2262 ret = sensor_call(pcdev, core, s_power, 1);
2263 if (ret == -ENOIOCTLCMD)
2267 /* Restart frame capture if active buffer exists */
2268 if (!ret && pcdev->active)
2269 pxa_camera_start_capture(pcdev);
2274 static int pxa_camera_pdata_from_dt(struct device *dev,
2275 struct pxa_camera_dev *pcdev,
2276 struct v4l2_async_subdev *asd)
2279 struct device_node *remote, *np = dev->of_node;
2280 struct v4l2_fwnode_endpoint ep;
2281 int err = of_property_read_u32(np, "clock-frequency",
2284 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2285 pcdev->mclk = mclk_rate;
2288 np = of_graph_get_next_endpoint(np, NULL);
2290 dev_err(dev, "could not find endpoint\n");
2294 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2296 dev_err(dev, "could not parse endpoint\n");
2300 switch (ep.bus.parallel.bus_width) {
2302 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2305 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2308 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2311 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2314 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2320 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2321 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2322 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2323 pcdev->platform_flags |= PXA_CAMERA_HSP;
2324 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2325 pcdev->platform_flags |= PXA_CAMERA_VSP;
2326 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2327 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2328 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2329 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2331 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2332 remote = of_graph_get_remote_port(np);
2334 asd->match.fwnode.fwnode = of_fwnode_handle(remote);
2335 of_node_put(remote);
2337 dev_notice(dev, "no remote for %pOF\n", np);
2346 static int pxa_camera_probe(struct platform_device *pdev)
2348 struct pxa_camera_dev *pcdev;
2349 struct resource *res;
2351 struct dma_slave_config config = {
2352 .src_addr_width = 0,
2354 .direction = DMA_DEV_TO_MEM,
2356 dma_cap_mask_t mask;
2357 struct pxad_param params;
2358 char clk_name[V4L2_CLK_NAME_SIZE];
2362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2363 irq = platform_get_irq(pdev, 0);
2364 if (!res || irq < 0)
2367 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2369 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2373 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2374 if (IS_ERR(pcdev->clk))
2375 return PTR_ERR(pcdev->clk);
2379 pcdev->pdata = pdev->dev.platform_data;
2380 if (pdev->dev.of_node && !pcdev->pdata) {
2381 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2383 pcdev->platform_flags = pcdev->pdata->flags;
2384 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2385 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2386 pcdev->asd.match.i2c.adapter_id =
2387 pcdev->pdata->sensor_i2c_adapter_id;
2388 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2393 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2394 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2396 * Platform hasn't set available data widths. This is bad.
2397 * Warn and use a default.
2399 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2400 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2402 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2403 pcdev->width_flags = 1 << 7;
2404 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2405 pcdev->width_flags |= 1 << 8;
2406 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2407 pcdev->width_flags |= 1 << 9;
2409 dev_warn(&pdev->dev,
2410 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2411 pcdev->mclk = 20000000;
2414 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2416 INIT_LIST_HEAD(&pcdev->capture);
2417 spin_lock_init(&pcdev->lock);
2418 mutex_init(&pcdev->mlock);
2421 * Request the regions.
2423 base = devm_ioremap_resource(&pdev->dev, res);
2425 return PTR_ERR(base);
2432 dma_cap_set(DMA_SLAVE, mask);
2433 dma_cap_set(DMA_PRIVATE, mask);
2437 pcdev->dma_chans[0] =
2438 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2439 ¶ms, &pdev->dev, "CI_Y");
2440 if (!pcdev->dma_chans[0]) {
2441 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2446 pcdev->dma_chans[1] =
2447 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2448 ¶ms, &pdev->dev, "CI_U");
2449 if (!pcdev->dma_chans[1]) {
2450 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2452 goto exit_free_dma_y;
2456 pcdev->dma_chans[2] =
2457 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2458 ¶ms, &pdev->dev, "CI_V");
2459 if (!pcdev->dma_chans[2]) {
2460 dev_err(&pdev->dev, "Can't request DMA for V\n");
2462 goto exit_free_dma_u;
2465 for (i = 0; i < 3; i++) {
2466 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2467 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2469 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2476 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2477 PXA_CAM_DRV_NAME, pcdev);
2479 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2483 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2485 pxa_camera_activate(pcdev);
2487 dev_set_drvdata(&pdev->dev, pcdev);
2488 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2492 pcdev->asds[0] = &pcdev->asd;
2493 pcdev->notifier.subdevs = pcdev->asds;
2494 pcdev->notifier.num_subdevs = 1;
2495 pcdev->notifier.bound = pxa_camera_sensor_bound;
2496 pcdev->notifier.unbind = pxa_camera_sensor_unbind;
2498 if (!of_have_populated_dt())
2499 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2501 err = pxa_camera_init_videobuf2(pcdev);
2503 goto exit_free_v4l2dev;
2506 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2507 pcdev->asd.match.i2c.adapter_id,
2508 pcdev->asd.match.i2c.address);
2510 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2512 if (IS_ERR(pcdev->mclk_clk)) {
2513 err = PTR_ERR(pcdev->mclk_clk);
2514 goto exit_free_v4l2dev;
2518 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2524 v4l2_clk_unregister(pcdev->mclk_clk);
2526 v4l2_device_unregister(&pcdev->v4l2_dev);
2528 dma_release_channel(pcdev->dma_chans[2]);
2530 dma_release_channel(pcdev->dma_chans[1]);
2532 dma_release_channel(pcdev->dma_chans[0]);
2536 static int pxa_camera_remove(struct platform_device *pdev)
2538 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2540 pxa_camera_deactivate(pcdev);
2541 dma_release_channel(pcdev->dma_chans[0]);
2542 dma_release_channel(pcdev->dma_chans[1]);
2543 dma_release_channel(pcdev->dma_chans[2]);
2545 v4l2_async_notifier_unregister(&pcdev->notifier);
2547 if (pcdev->mclk_clk) {
2548 v4l2_clk_unregister(pcdev->mclk_clk);
2549 pcdev->mclk_clk = NULL;
2552 v4l2_device_unregister(&pcdev->v4l2_dev);
2554 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2559 static const struct dev_pm_ops pxa_camera_pm = {
2560 .suspend = pxa_camera_suspend,
2561 .resume = pxa_camera_resume,
2564 static const struct of_device_id pxa_camera_of_match[] = {
2565 { .compatible = "marvell,pxa270-qci", },
2568 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2570 static struct platform_driver pxa_camera_driver = {
2572 .name = PXA_CAM_DRV_NAME,
2573 .pm = &pxa_camera_pm,
2574 .of_match_table = of_match_ptr(pxa_camera_of_match),
2576 .probe = pxa_camera_probe,
2577 .remove = pxa_camera_remove,
2580 module_platform_driver(pxa_camera_driver);
2582 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2583 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2584 MODULE_LICENSE("GPL");
2585 MODULE_VERSION(PXA_CAM_VERSION);
2586 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);