drivers/media/platform/nuvoton/npcm-video.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Video Capture/Differentiation Engine (VCD) and Encoding
   4  * Compression Engine (ECE) present on Nuvoton NPCM SoCs.
   5  *
   6  * Copyright (C) 2022 Nuvoton Technologies
   7  */
   8
   9 #include <linux/atomic.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/bitmap.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/of_reserved_mem.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regmap.h>
  27 #include <linux/reset.h>
  28 #include <linux/sched.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/string.h>
  31 #include <linux/v4l2-controls.h>
  32 #include <linux/videodev2.h>
  33 #include <media/v4l2-ctrls.h>
  34 #include <media/v4l2-dev.h>
  35 #include <media/v4l2-device.h>
  36 #include <media/v4l2-dv-timings.h>
  37 #include <media/v4l2-event.h>
  38 #include <media/v4l2-ioctl.h>
  39 #include <media/videobuf2-dma-contig.h>
  40 #include <uapi/linux/npcm-video.h>
  41 #include "npcm-regs.h"
  42
  43 #define DEVICE_NAME     "npcm-video"
  44 #define MAX_WIDTH       1920
  45 #define MAX_HEIGHT      1200
  46 #define MIN_WIDTH       320
  47 #define MIN_HEIGHT      240
  48 #define MIN_LP          512
  49 #define MAX_LP          4096
  50 #define RECT_W          16
  51 #define RECT_H          16
  52 #define BITMAP_SIZE     32
  53
  54 struct npcm_video_addr {
  55         size_t size;
  56         dma_addr_t dma;
  57         void *virt;
  58 };
  59
  60 struct npcm_video_buffer {
  61         struct vb2_v4l2_buffer vb;
  62         struct list_head link;
  63 };
  64
  65 #define to_npcm_video_buffer(x) \
  66         container_of((x), struct npcm_video_buffer, vb)
  67
  68 /*
  69  * VIDEO_STREAMING:     a flag indicating if the video has started streaming
  70  * VIDEO_CAPTURING:     a flag indicating if the VCD is capturing a frame
  71  * VIDEO_RES_CHANGING:  a flag indicating if the resolution is changing
  72  * VIDEO_STOPPED:       a flag indicating if the video has stopped streaming
  73  */
  74 enum {
  75         VIDEO_STREAMING,
  76         VIDEO_CAPTURING,
  77         VIDEO_RES_CHANGING,
  78         VIDEO_STOPPED,
  79 };
  80
  81 struct rect_list {
  82         struct v4l2_clip clip;
  83         struct list_head list;
  84 };
  85
  86 struct rect_list_info {
  87         struct rect_list *list;
  88         struct rect_list *first;
  89         struct list_head *head;
  90         unsigned int index;
  91         unsigned int tile_perline;
  92         unsigned int tile_perrow;
  93         unsigned int offset_perline;
  94         unsigned int tile_size;
  95         unsigned int tile_cnt;
  96 };
  97
  98 struct npcm_ece {
  99         struct regmap *regmap;
 100         atomic_t clients;
 101         struct reset_control *reset;
 102         bool enable;
 103 };
 104
 105 struct npcm_video {
 106         struct regmap *gcr_regmap;
 107         struct regmap *gfx_regmap;
 108         struct regmap *vcd_regmap;
 109
 110         struct device *dev;
 111         struct v4l2_ctrl_handler ctrl_handler;
 112         struct v4l2_ctrl *rect_cnt_ctrl;
 113         struct v4l2_device v4l2_dev;
 114         struct v4l2_pix_format pix_fmt;
 115         struct v4l2_bt_timings active_timings;
 116         struct v4l2_bt_timings detected_timings;
 117         unsigned int v4l2_input_status;
 118         struct vb2_queue queue;
 119         struct video_device vdev;
 120         struct mutex video_lock; /* v4l2 and videobuf2 lock */
 121
 122         struct list_head buffers;
 123         spinlock_t lock; /* buffer list lock */
 124         unsigned long flags;
 125         unsigned int sequence;
 126
 127         struct npcm_video_addr src;
 128         struct reset_control *reset;
 129         struct npcm_ece ece;
 130
 131         unsigned int bytesperline;
 132         unsigned int bytesperpixel;
 133         unsigned int rect_cnt;
 134         struct list_head list[VIDEO_MAX_FRAME];
 135         unsigned int rect[VIDEO_MAX_FRAME];
 136         unsigned int ctrl_cmd;
 137         unsigned int op_cmd;
 138 };
 139
 140 #define to_npcm_video(x) container_of((x), struct npcm_video, v4l2_dev)
 141
 142 struct npcm_fmt {
 143         unsigned int fourcc;
 144         unsigned int bpp; /* bytes per pixel */
 145 };
 146
 147 static const struct npcm_fmt npcm_fmt_list[] = {
 148         {
 149                 .fourcc = V4L2_PIX_FMT_RGB565,
 150                 .bpp    = 2,
 151         },
 152         {
 153                 .fourcc = V4L2_PIX_FMT_HEXTILE,
 154                 .bpp    = 2,
 155         },
 156 };
 157
 158 #define NUM_FORMATS ARRAY_SIZE(npcm_fmt_list)
 159
 160 static const struct v4l2_dv_timings_cap npcm_video_timings_cap = {
 161         .type = V4L2_DV_BT_656_1120,
 162         .bt = {
 163                 .min_width = MIN_WIDTH,
 164                 .max_width = MAX_WIDTH,
 165                 .min_height = MIN_HEIGHT,
 166                 .max_height = MAX_HEIGHT,
 167                 .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */
 168                 .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */
 169                 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 170                              V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
 171                 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
 172                                 V4L2_DV_BT_CAP_REDUCED_BLANKING |
 173                                 V4L2_DV_BT_CAP_CUSTOM,
 174         },
 175 };
 176
 177 static DECLARE_BITMAP(bitmap, BITMAP_SIZE);
 178
 179 static const struct npcm_fmt *npcm_video_find_format(struct v4l2_format *f)
 180 {
 181         const struct npcm_fmt *fmt;
 182         unsigned int k;
 183
 184         for (k = 0; k < NUM_FORMATS; k++) {
 185                 fmt = &npcm_fmt_list[k];
 186                 if (fmt->fourcc == f->fmt.pix.pixelformat)
 187                         break;
 188         }
 189
 190         if (k == NUM_FORMATS)
 191                 return NULL;
 192
 193         return &npcm_fmt_list[k];
 194 }
 195
 196 static void npcm_video_ece_prepend_rect_header(void *addr, u16 x, u16 y, u16 w, u16 h)
 197 {
 198         __be16 x_pos = cpu_to_be16(x);
 199         __be16 y_pos = cpu_to_be16(y);
 200         __be16 width = cpu_to_be16(w);
 201         __be16 height = cpu_to_be16(h);
 202         __be32 encoding = cpu_to_be32(5); /* Hextile encoding */
 203
 204         memcpy(addr, &x_pos, 2);
 205         memcpy(addr + 2, &y_pos, 2);
 206         memcpy(addr + 4, &width, 2);
 207         memcpy(addr + 6, &height, 2);
 208         memcpy(addr + 8, &encoding, 4);
 209 }
 210
 211 static unsigned int npcm_video_ece_get_ed_size(struct npcm_video *video,
 212                                                unsigned int offset, void *addr)
 213 {
 214         struct regmap *ece = video->ece.regmap;
 215         unsigned int size, gap, val;
 216         int ret;
 217
 218         ret = regmap_read_poll_timeout(ece, ECE_DDA_STS, val,
 219                                        (val & ECE_DDA_STS_CDREADY), 0,
 220                                        ECE_POLL_TIMEOUT_US);
 221
 222         if (ret) {
 223                 dev_warn(video->dev, "Wait for ECE_DDA_STS_CDREADY timeout\n");
 224                 return 0;
 225         }
 226
 227         size = readl((void __iomem *)addr + offset);
 228         regmap_read(ece, ECE_HEX_CTRL, &val);
 229         gap = FIELD_GET(ECE_HEX_CTRL_ENC_GAP, val);
 230
 231         dev_dbg(video->dev, "offset = %u, ed_size = %u, gap = %u\n", offset,
 232                 size, gap);
 233
 234         return size + gap;
 235 }
 236
 237 static void npcm_video_ece_enc_rect(struct npcm_video *video,
 238                                     unsigned int r_off_x, unsigned int r_off_y,
 239                                     unsigned int r_w, unsigned int r_h)
 240 {
 241         struct regmap *ece = video->ece.regmap;
 242         unsigned int rect_offset = (r_off_y * video->bytesperline) + (r_off_x * 2);
 243         unsigned int w_size = ECE_TILE_W, h_size = ECE_TILE_H;
 244         unsigned int temp, w_tile, h_tile;
 245
 246         regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
 247         regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, ECE_DDA_CTRL_ECEEN);
 248         regmap_write(ece, ECE_DDA_STS, ECE_DDA_STS_CDREADY | ECE_DDA_STS_ACDRDY);
 249         regmap_write(ece, ECE_RECT_XY, rect_offset);
 250
 251         w_tile = r_w / ECE_TILE_W;
 252         h_tile = r_h / ECE_TILE_H;
 253
 254         if (r_w % ECE_TILE_W) {
 255                 w_tile += 1;
 256                 w_size = r_w % ECE_TILE_W;
 257         }
 258         if (r_h % ECE_TILE_H || !h_tile) {
 259                 h_tile += 1;
 260                 h_size = r_h % ECE_TILE_H;
 261         }
 262
 263         temp = FIELD_PREP(ECE_RECT_DIMEN_WLTR, w_size - 1) |
 264                FIELD_PREP(ECE_RECT_DIMEN_HLTR, h_size - 1) |
 265                FIELD_PREP(ECE_RECT_DIMEN_WR, w_tile - 1) |
 266                FIELD_PREP(ECE_RECT_DIMEN_HR, h_tile - 1);
 267
 268         regmap_write(ece, ECE_RECT_DIMEN, temp);
 269 }
 270
 271 static unsigned int npcm_video_ece_read_rect_offset(struct npcm_video *video)
 272 {
 273         struct regmap *ece = video->ece.regmap;
 274         unsigned int offset;
 275
 276         regmap_read(ece, ECE_HEX_RECT_OFFSET, &offset);
 277         return FIELD_GET(ECE_HEX_RECT_OFFSET_MASK, offset);
 278 }
 279
 280 /*
 281  * Set the line pitch (in bytes) for the frame buffers.
 282  * Can be on of those values: 512, 1024, 2048, 2560 or 4096 bytes.
 283  */
 284 static void npcm_video_ece_set_lp(struct npcm_video *video, unsigned int pitch)
 285 {
 286         struct regmap *ece = video->ece.regmap;
 287         unsigned int lp;
 288
 289         switch (pitch) {
 290         case 512:
 291                 lp = ECE_RESOL_FB_LP_512;
 292                 break;
 293         case 1024:
 294                 lp = ECE_RESOL_FB_LP_1024;
 295                 break;
 296         case 2048:
 297                 lp = ECE_RESOL_FB_LP_2048;
 298                 break;
 299         case 2560:
 300                 lp = ECE_RESOL_FB_LP_2560;
 301                 break;
 302         case 4096:
 303                 lp = ECE_RESOL_FB_LP_4096;
 304                 break;
 305         default:
 306                 return;
 307         }
 308
 309         regmap_write(ece, ECE_RESOL, lp);
 310 }
 311
 312 static inline void npcm_video_ece_set_fb_addr(struct npcm_video *video,
 313                                               unsigned int buffer)
 314 {
 315         struct regmap *ece = video->ece.regmap;
 316
 317         regmap_write(ece, ECE_FBR_BA, buffer);
 318 }
 319
 320 static inline void npcm_video_ece_set_enc_dba(struct npcm_video *video,
 321                                               unsigned int addr)
 322 {
 323         struct regmap *ece = video->ece.regmap;
 324
 325         regmap_write(ece, ECE_ED_BA, addr);
 326 }
 327
 328 static inline void npcm_video_ece_clear_rect_offset(struct npcm_video *video)
 329 {
 330         struct regmap *ece = video->ece.regmap;
 331
 332         regmap_write(ece, ECE_HEX_RECT_OFFSET, 0);
 333 }
 334
 335 static void npcm_video_ece_ctrl_reset(struct npcm_video *video)
 336 {
 337         struct regmap *ece = video->ece.regmap;
 338
 339         regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
 340         regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, ECE_HEX_CTRL_ENCDIS);
 341         regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, ECE_DDA_CTRL_ECEEN);
 342         regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, 0);
 343
 344         npcm_video_ece_clear_rect_offset(video);
 345 }
 346
 347 static void npcm_video_ece_ip_reset(struct npcm_video *video)
 348 {
 349         /*
 350          * After resetting a module and clearing the reset bit, it should wait
 351          * at least 10 us before accessing the module.
 352          */
 353         reset_control_assert(video->ece.reset);
 354         usleep_range(10, 20);
 355         reset_control_deassert(video->ece.reset);
 356         usleep_range(10, 20);
 357 }
 358
 359 static void npcm_video_ece_stop(struct npcm_video *video)
 360 {
 361         struct regmap *ece = video->ece.regmap;
 362
 363         regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_ECEEN, 0);
 364         regmap_update_bits(ece, ECE_DDA_CTRL, ECE_DDA_CTRL_INTEN, 0);
 365         regmap_update_bits(ece, ECE_HEX_CTRL, ECE_HEX_CTRL_ENCDIS, ECE_HEX_CTRL_ENCDIS);
 366         npcm_video_ece_clear_rect_offset(video);
 367 }
 368
 369 static bool npcm_video_alloc_fb(struct npcm_video *video,
 370                                 struct npcm_video_addr *addr)
 371 {
 372         addr->virt = dma_alloc_coherent(video->dev, VCD_FB_SIZE, &addr->dma,
 373                                         GFP_KERNEL);
 374         if (!addr->virt)
 375                 return false;
 376
 377         addr->size = VCD_FB_SIZE;
 378         return true;
 379 }
 380
 381 static void npcm_video_free_fb(struct npcm_video *video,
 382                                struct npcm_video_addr *addr)
 383 {
 384         dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma);
 385         addr->size = 0;
 386         addr->dma = 0ULL;
 387         addr->virt = NULL;
 388 }
 389
 390 static void npcm_video_free_diff_table(struct npcm_video *video)
 391 {
 392         struct list_head *head, *pos, *nx;
 393         struct rect_list *tmp;
 394         unsigned int i;
 395
 396         for (i = 0; i < video->queue.num_buffers; i++) {
 397                 head = &video->list[i];
 398                 list_for_each_safe(pos, nx, head) {
 399                         tmp = list_entry(pos, struct rect_list, list);
 400                         list_del(&tmp->list);
 401                         kfree(tmp);
 402                 }
 403         }
 404 }
 405
 406 static unsigned int npcm_video_add_rect(struct npcm_video *video,
 407                                         unsigned int index,
 408                                         unsigned int x, unsigned int y,
 409                                         unsigned int w, unsigned int h)
 410 {
 411         struct list_head *head = &video->list[index];
 412         struct rect_list *list = NULL;
 413         struct v4l2_rect *r;
 414
 415         list = kzalloc(sizeof(*list), GFP_KERNEL);
 416         if (!list)
 417                 return 0;
 418
 419         r = &list->clip.c;
 420         r->left = x;
 421         r->top = y;
 422         r->width = w;
 423         r->height = h;
 424
 425         list_add_tail(&list->list, head);
 426         return 1;
 427 }
 428
 429 static void npcm_video_merge_rect(struct npcm_video *video,
 430                                   struct rect_list_info *info)
 431 {
 432         struct list_head *head = info->head;
 433         struct rect_list *list = info->list, *first = info->first;
 434         struct v4l2_rect *r = &list->clip.c, *f = &first->clip.c;
 435
 436         if (!first) {
 437                 first = list;
 438                 info->first = first;
 439                 list_add_tail(&list->list, head);
 440                 video->rect_cnt++;
 441         } else {
 442                 if ((r->left == (f->left + f->width)) && r->top == f->top) {
 443                         f->width += r->width;
 444                         kfree(list);
 445                 } else if ((r->top == (f->top + f->height)) &&
 446                            (r->left == f->left)) {
 447                         f->height += r->height;
 448                         kfree(list);
 449                 } else if (((r->top > f->top) &&
 450                            (r->top < (f->top + f->height))) &&
 451                            ((r->left > f->left) &&
 452                            (r->left < (f->left + f->width)))) {
 453                         kfree(list);
 454                 } else {
 455                         list_add_tail(&list->list, head);
 456                         video->rect_cnt++;
 457                         info->first = list;
 458                 }
 459         }
 460 }
 461
 462 static struct rect_list *npcm_video_new_rect(struct npcm_video *video,
 463                                              unsigned int offset,
 464                                              unsigned int index)
 465 {
 466         struct v4l2_bt_timings *act = &video->active_timings;
 467         struct rect_list *list = NULL;
 468         struct v4l2_rect *r;
 469
 470         list = kzalloc(sizeof(*list), GFP_KERNEL);
 471         if (!list)
 472                 return NULL;
 473
 474         r = &list->clip.c;
 475
 476         r->left = (offset << 4);
 477         r->top = (index >> 2);
 478         r->width = RECT_W;
 479         r->height = RECT_H;
 480         if ((r->left + RECT_W) > act->width)
 481                 r->width = act->width - r->left;
 482         if ((r->top + RECT_H) > act->height)
 483                 r->height = act->height - r->top;
 484
 485         return list;
 486 }
 487
 488 static int npcm_video_find_rect(struct npcm_video *video,
 489                                 struct rect_list_info *info,
 490                                 unsigned int offset)
 491 {
 492         if (offset < info->tile_perline) {
 493                 info->list = npcm_video_new_rect(video, offset, info->index);
 494                 if (!info->list) {
 495                         dev_err(video->dev, "Failed to allocate rect_list\n");
 496                         return -ENOMEM;
 497                 }
 498
 499                 npcm_video_merge_rect(video, info);
 500         }
 501         return 0;
 502 }
 503
 504 static int npcm_video_build_table(struct npcm_video *video,
 505                                   struct rect_list_info *info)
 506 {
 507         struct regmap *vcd = video->vcd_regmap;
 508         unsigned int j, bit, value;
 509         int ret;
 510
 511         for (j = 0; j < info->offset_perline; j += 4) {
 512                 regmap_read(vcd, VCD_DIFF_TBL + (j + info->index), &value);
 513
 514                 bitmap_from_arr32(bitmap, &value, BITMAP_SIZE);
 515
 516                 for_each_set_bit(bit, bitmap, BITMAP_SIZE) {
 517                         ret = npcm_video_find_rect(video, info, bit + (j << 3));
 518                         if (ret)
 519                                 return ret;
 520                 }
 521         }
 522         info->index += 64;
 523         return info->tile_perline;
 524 }
 525
 526 static void npcm_video_get_rect_list(struct npcm_video *video, unsigned int index)
 527 {
 528         struct v4l2_bt_timings *act = &video->active_timings;
 529         struct rect_list_info info;
 530         unsigned int tile_cnt = 0, mod;
 531         int ret = 0;
 532
 533         memset(&info, 0, sizeof(struct rect_list_info));
 534         info.head = &video->list[index];
 535
 536         info.tile_perline = act->width >> 4;
 537         mod = act->width % RECT_W;
 538         if (mod != 0)
 539                 info.tile_perline += 1;
 540
 541         info.tile_perrow = act->height >> 4;
 542         mod = act->height % RECT_H;
 543         if (mod != 0)
 544                 info.tile_perrow += 1;
 545
 546         info.tile_size = info.tile_perrow * info.tile_perline;
 547
 548         info.offset_perline = info.tile_perline >> 5;
 549         mod = info.tile_perline % 32;
 550         if (mod != 0)
 551                 info.offset_perline += 1;
 552
 553         info.offset_perline *= 4;
 554
 555         do {
 556                 ret = npcm_video_build_table(video, &info);
 557                 if (ret < 0)
 558                         return;
 559
 560                 tile_cnt += ret;
 561         } while (tile_cnt < info.tile_size);
 562 }
 563
 564 static unsigned int npcm_video_is_mga(struct npcm_video *video)
 565 {
 566         struct regmap *gfxi = video->gfx_regmap;
 567         unsigned int dispst;
 568
 569         regmap_read(gfxi, DISPST, &dispst);
 570         return ((dispst & DISPST_MGAMODE) == DISPST_MGAMODE);
 571 }
 572
 573 static unsigned int npcm_video_hres(struct npcm_video *video)
 574 {
 575         struct regmap *gfxi = video->gfx_regmap;
 576         unsigned int hvcnth, hvcntl, apb_hor_res;
 577
 578         regmap_read(gfxi, HVCNTH, &hvcnth);
 579         regmap_read(gfxi, HVCNTL, &hvcntl);
 580         apb_hor_res = (((hvcnth & HVCNTH_MASK) << 8) + (hvcntl & HVCNTL_MASK) + 1);
 581
 582         return apb_hor_res;
 583 }
 584
 585 static unsigned int npcm_video_vres(struct npcm_video *video)
 586 {
 587         struct regmap *gfxi = video->gfx_regmap;
 588         unsigned int vvcnth, vvcntl, apb_ver_res;
 589
 590         regmap_read(gfxi, VVCNTH, &vvcnth);
 591         regmap_read(gfxi, VVCNTL, &vvcntl);
 592
 593         apb_ver_res = (((vvcnth & VVCNTH_MASK) << 8) + (vvcntl & VVCNTL_MASK));
 594
 595         return apb_ver_res;
 596 }
 597
 598 static int npcm_video_capres(struct npcm_video *video, unsigned int hor_res,
 599                              unsigned int vert_res)
 600 {
 601         struct regmap *vcd = video->vcd_regmap;
 602         unsigned int res, cap_res;
 603
 604         if (hor_res > MAX_WIDTH || vert_res > MAX_HEIGHT)
 605                 return -EINVAL;
 606
 607         res = FIELD_PREP(VCD_CAP_RES_VERT_RES, vert_res) |
 608               FIELD_PREP(VCD_CAP_RES_HOR_RES, hor_res);
 609
 610         regmap_write(vcd, VCD_CAP_RES, res);
 611         regmap_read(vcd, VCD_CAP_RES, &cap_res);
 612
 613         if (cap_res != res)
 614                 return -EINVAL;
 615
 616         return 0;
 617 }
 618
 619 static void npcm_video_vcd_ip_reset(struct npcm_video *video)
 620 {
 621         /*
 622          * After resetting a module and clearing the reset bit, it should wait
 623          * at least 10 us before accessing the module.
 624          */
 625         reset_control_assert(video->reset);
 626         usleep_range(10, 20);
 627         reset_control_deassert(video->reset);
 628         usleep_range(10, 20);
 629 }
 630
 631 static void npcm_video_vcd_state_machine_reset(struct npcm_video *video)
 632 {
 633         struct regmap *vcd = video->vcd_regmap;
 634
 635         regmap_update_bits(vcd, VCD_MODE, VCD_MODE_VCDE, 0);
 636         regmap_update_bits(vcd, VCD_MODE, VCD_MODE_IDBC, 0);
 637         regmap_update_bits(vcd, VCD_CMD, VCD_CMD_RST, VCD_CMD_RST);
 638
 639         /*
 640          * VCD_CMD_RST will reset VCD internal state machines and clear FIFOs,
 641          * it should wait at least 800 us for the reset operations completed.
 642          */
 643         usleep_range(800, 1000);
 644
 645         regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
 646         regmap_update_bits(vcd, VCD_MODE, VCD_MODE_VCDE, VCD_MODE_VCDE);
 647         regmap_update_bits(vcd, VCD_MODE, VCD_MODE_IDBC, VCD_MODE_IDBC);
 648 }
 649
 650 static void npcm_video_gfx_reset(struct npcm_video *video)
 651 {
 652         struct regmap *gcr = video->gcr_regmap;
 653
 654         regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, INTCR2_GIRST2);
 655         npcm_video_vcd_state_machine_reset(video);
 656         regmap_update_bits(gcr, INTCR2, INTCR2_GIRST2, 0);
 657 }
 658
 659 static void npcm_video_kvm_bw(struct npcm_video *video, bool set_bw)
 660 {
 661         struct regmap *vcd = video->vcd_regmap;
 662
 663         if (set_bw || !npcm_video_is_mga(video))
 664                 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_KVM_BW_SET,
 665                                    VCD_MODE_KVM_BW_SET);
 666         else
 667                 regmap_update_bits(vcd, VCD_MODE, VCD_MODE_KVM_BW_SET, 0);
 668 }
 669
 670 static unsigned int npcm_video_pclk(struct npcm_video *video)
 671 {
 672         struct regmap *gfxi = video->gfx_regmap;
 673         unsigned int tmp, pllfbdiv, pllinotdiv, gpllfbdiv;
 674         unsigned int gpllfbdv109, gpllfbdv8, gpllindiv;
 675         unsigned int gpllst_pllotdiv1, gpllst_pllotdiv2;
 676
 677         regmap_read(gfxi, GPLLST, &tmp);
 678         gpllfbdv109 = FIELD_GET(GPLLST_GPLLFBDV109, tmp);
 679         gpllst_pllotdiv1 = FIELD_GET(GPLLST_PLLOTDIV1, tmp);
 680         gpllst_pllotdiv2 = FIELD_GET(GPLLST_PLLOTDIV2, tmp);
 681
 682         regmap_read(gfxi, GPLLINDIV, &tmp);
 683         gpllfbdv8 = FIELD_GET(GPLLINDIV_GPLLFBDV8, tmp);
 684         gpllindiv = FIELD_GET(GPLLINDIV_MASK, tmp);
 685
 686         regmap_read(gfxi, GPLLFBDIV, &tmp);
 687         gpllfbdiv = FIELD_GET(GPLLFBDIV_MASK, tmp);
 688
 689         pllfbdiv = (512 * gpllfbdv109 + 256 * gpllfbdv8 + gpllfbdiv);
 690         pllinotdiv = (gpllindiv * gpllst_pllotdiv1 * gpllst_pllotdiv2);
 691         if (pllfbdiv == 0 || pllinotdiv == 0)
 692                 return 0;
 693
 694         return ((pllfbdiv * 25000) / pllinotdiv) * 1000;
 695 }
 696
 697 static unsigned int npcm_video_get_bpp(struct npcm_video *video)
 698 {
 699         const struct npcm_fmt *fmt;
 700         unsigned int k;
 701
 702         for (k = 0; k < NUM_FORMATS; k++) {
 703                 fmt = &npcm_fmt_list[k];
 704                 if (fmt->fourcc == video->pix_fmt.pixelformat)
 705                         break;
 706         }
 707
 708         return fmt->bpp;
 709 }
 710
 711 /*
 712  * Pitch must be a power of 2, >= linebytes,
 713  * at least 512, and no more than 4096.
 714  */
 715 static void npcm_video_set_linepitch(struct npcm_video *video,
 716                                      unsigned int linebytes)
 717 {
 718         struct regmap *vcd = video->vcd_regmap;
 719         unsigned int pitch = MIN_LP;
 720
 721         while ((pitch < linebytes) && (pitch < MAX_LP))
 722                 pitch *= 2;
 723
 724         regmap_write(vcd, VCD_FB_LP, FIELD_PREP(VCD_FBA_LP, pitch) |
 725                      FIELD_PREP(VCD_FBB_LP, pitch));
 726 }
 727
 728 static unsigned int npcm_video_get_linepitch(struct npcm_video *video)
 729 {
 730         struct regmap *vcd = video->vcd_regmap;
 731         unsigned int linepitch;
 732
 733         regmap_read(vcd, VCD_FB_LP, &linepitch);
 734         return FIELD_GET(VCD_FBA_LP, linepitch);
 735 }
 736
 737 static void npcm_video_command(struct npcm_video *video, unsigned int value)
 738 {
 739         struct regmap *vcd = video->vcd_regmap;
 740         unsigned int cmd;
 741
 742         regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
 743         regmap_read(vcd, VCD_CMD, &cmd);
 744         cmd |= FIELD_PREP(VCD_CMD_OPERATION, value);
 745
 746         regmap_write(vcd, VCD_CMD, cmd);
 747         regmap_update_bits(vcd, VCD_CMD, VCD_CMD_GO, VCD_CMD_GO);
 748         video->op_cmd = value;
 749 }
 750
 751 static void npcm_video_init_reg(struct npcm_video *video)
 752 {
 753         struct regmap *gcr = video->gcr_regmap, *vcd = video->vcd_regmap;
 754
 755         /* Selects Data Enable */
 756         regmap_update_bits(gcr, INTCR, INTCR_DEHS, 0);
 757
 758         /* Enable display of KVM GFX and access to memory */
 759         regmap_update_bits(gcr, INTCR, INTCR_GFXIFDIS, 0);
 760
 761         /* Active Vertical/Horizontal Counters Reset */
 762         regmap_update_bits(gcr, INTCR2, INTCR2_GIHCRST | INTCR2_GIVCRST,
 763                            INTCR2_GIHCRST | INTCR2_GIVCRST);
 764
 765         /* Reset video modules */
 766         npcm_video_vcd_ip_reset(video);
 767         npcm_video_gfx_reset(video);
 768
 769         /* Set the FIFO thresholds */
 770         regmap_write(vcd, VCD_FIFO, VCD_FIFO_TH);
 771
 772         /* Set RCHG timer */
 773         regmap_write(vcd, VCD_RCHG, FIELD_PREP(VCD_RCHG_TIM_PRSCL, 0xf) |
 774                      FIELD_PREP(VCD_RCHG_IG_CHG0, 0x3));
 775
 776         /* Set video mode */
 777         regmap_write(vcd, VCD_MODE, VCD_MODE_VCDE | VCD_MODE_CM565 |
 778                      VCD_MODE_IDBC | VCD_MODE_KVM_BW_SET);
 779 }
 780
 781 static int npcm_video_start_frame(struct npcm_video *video)
 782 {
 783         struct npcm_video_buffer *buf;
 784         struct regmap *vcd = video->vcd_regmap;
 785         unsigned long flags;
 786         unsigned int val;
 787         int ret;
 788
 789         if (video->v4l2_input_status) {
 790                 dev_dbg(video->dev, "No video signal; skip capture frame\n");
 791                 return 0;
 792         }
 793
 794         ret = regmap_read_poll_timeout(vcd, VCD_STAT, val, !(val & VCD_STAT_BUSY),
 795                                        1000, VCD_TIMEOUT_US);
 796         if (ret) {
 797                 dev_err(video->dev, "Wait for VCD_STAT_BUSY timeout\n");
 798                 return -EBUSY;
 799         }
 800
 801         spin_lock_irqsave(&video->lock, flags);
 802         buf = list_first_entry_or_null(&video->buffers,
 803                                        struct npcm_video_buffer, link);
 804         if (!buf) {
 805                 spin_unlock_irqrestore(&video->lock, flags);
 806                 dev_dbg(video->dev, "No empty buffers; skip capture frame\n");
 807                 return 0;
 808         }
 809
 810         set_bit(VIDEO_CAPTURING, &video->flags);
 811         spin_unlock_irqrestore(&video->lock, flags);
 812
 813         npcm_video_vcd_state_machine_reset(video);
 814
 815         regmap_read(vcd, VCD_HOR_AC_TIM, &val);
 816         regmap_update_bits(vcd, VCD_HOR_AC_LST, VCD_HOR_AC_LAST,
 817                            FIELD_GET(VCD_HOR_AC_TIME, val));
 818
 819         regmap_read(vcd, VCD_VER_HI_TIM, &val);
 820         regmap_update_bits(vcd, VCD_VER_HI_LST, VCD_VER_HI_LAST,
 821                            FIELD_GET(VCD_VER_HI_TIME, val));
 822
 823         regmap_update_bits(vcd, VCD_INTE, VCD_INTE_DONE_IE | VCD_INTE_IFOT_IE |
 824                            VCD_INTE_IFOR_IE | VCD_INTE_HAC_IE | VCD_INTE_VHT_IE,
 825                            VCD_INTE_DONE_IE | VCD_INTE_IFOT_IE | VCD_INTE_IFOR_IE |
 826                            VCD_INTE_HAC_IE | VCD_INTE_VHT_IE);
 827
 828         npcm_video_command(video, video->ctrl_cmd);
 829
 830         return 0;
 831 }
 832
 833 static void npcm_video_bufs_done(struct npcm_video *video,
 834                                  enum vb2_buffer_state state)
 835 {
 836         struct npcm_video_buffer *buf;
 837         unsigned long flags;
 838
 839         spin_lock_irqsave(&video->lock, flags);
 840         list_for_each_entry(buf, &video->buffers, link)
 841                 vb2_buffer_done(&buf->vb.vb2_buf, state);
 842
 843         INIT_LIST_HEAD(&video->buffers);
 844         spin_unlock_irqrestore(&video->lock, flags);
 845 }
 846
 847 static void npcm_video_get_diff_rect(struct npcm_video *video, unsigned int index)
 848 {
 849         unsigned int width = video->active_timings.width;
 850         unsigned int height = video->active_timings.height;
 851
 852         if (video->op_cmd != VCD_CMD_OPERATION_CAPTURE) {
 853                 video->rect_cnt = 0;
 854                 npcm_video_get_rect_list(video, index);
 855                 video->rect[index] = video->rect_cnt;
 856         } else {
 857                 video->rect[index] = npcm_video_add_rect(video, index, 0, 0,
 858                                                          width, height);
 859         }
 860 }
 861
 862 static void npcm_video_detect_resolution(struct npcm_video *video)
 863 {
 864         struct v4l2_bt_timings *act = &video->active_timings;
 865         struct v4l2_bt_timings *det = &video->detected_timings;
 866         struct regmap *gfxi = video->gfx_regmap;
 867         unsigned int dispst;
 868
 869         video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
 870         det->width = npcm_video_hres(video);
 871         det->height = npcm_video_vres(video);
 872
 873         if (act->width != det->width || act->height != det->height) {
 874                 dev_dbg(video->dev, "Resolution changed\n");
 875
 876                 if (npcm_video_hres(video) > 0 && npcm_video_vres(video) > 0) {
 877                         if (test_bit(VIDEO_STREAMING, &video->flags)) {
 878                                 /*
 879                                  * Wait for resolution is available,
 880                                  * and it is also captured by host.
 881                                  */
 882                                 do {
 883                                         mdelay(100);
 884                                         regmap_read(gfxi, DISPST, &dispst);
 885                                 } while (npcm_video_vres(video) < 100 ||
 886                                          npcm_video_pclk(video) == 0 ||
 887                                          (dispst & DISPST_HSCROFF));
 888                         }
 889
 890                         det->width = npcm_video_hres(video);
 891                         det->height = npcm_video_vres(video);
 892                         det->pixelclock = npcm_video_pclk(video);
 893                 }
 894
 895                 clear_bit(VIDEO_RES_CHANGING, &video->flags);
 896         }
 897
 898         if (det->width && det->height)
 899                 video->v4l2_input_status = 0;
 900
 901         dev_dbg(video->dev, "Got resolution[%dx%d] -> [%dx%d], status %d\n",
 902                 act->width, act->height, det->width, det->height,
 903                 video->v4l2_input_status);
 904 }
 905
 906 static int npcm_video_set_resolution(struct npcm_video *video,
 907                                      struct v4l2_bt_timings *timing)
 908 {
 909         struct regmap *vcd = video->vcd_regmap;
 910         unsigned int mode;
 911
 912         if (npcm_video_capres(video, timing->width, timing->height)) {
 913                 dev_err(video->dev, "Failed to set VCD_CAP_RES\n");
 914                 return -EINVAL;
 915         }
 916
 917         video->active_timings = *timing;
 918         video->bytesperpixel = npcm_video_get_bpp(video);
 919         npcm_video_set_linepitch(video, timing->width * video->bytesperpixel);
 920         video->bytesperline = npcm_video_get_linepitch(video);
 921         video->pix_fmt.width = timing->width ? timing->width : MIN_WIDTH;
 922         video->pix_fmt.height = timing->height ? timing->height : MIN_HEIGHT;
 923         video->pix_fmt.sizeimage = video->pix_fmt.width * video->pix_fmt.height *
 924                                    video->bytesperpixel;
 925         video->pix_fmt.bytesperline = video->bytesperline;
 926
 927         npcm_video_kvm_bw(video, timing->pixelclock > VCD_KVM_BW_PCLK);
 928         npcm_video_gfx_reset(video);
 929         regmap_read(vcd, VCD_MODE, &mode);
 930
 931         dev_dbg(video->dev, "VCD mode = 0x%x, %s mode\n", mode,
 932                 npcm_video_is_mga(video) ? "Hi Res" : "VGA");
 933
 934         dev_dbg(video->dev,
 935                 "Digital mode: %d x %d x %d, pixelclock %lld, bytesperline %d\n",
 936                 timing->width, timing->height, video->bytesperpixel,
 937                 timing->pixelclock, video->bytesperline);
 938
 939         return 0;
 940 }
 941
 942 static void npcm_video_start(struct npcm_video *video)
 943 {
 944         npcm_video_init_reg(video);
 945
 946         if (!npcm_video_alloc_fb(video, &video->src)) {
 947                 dev_err(video->dev, "Failed to allocate VCD frame buffer\n");
 948                 return;
 949         }
 950
 951         npcm_video_detect_resolution(video);
 952         if (npcm_video_set_resolution(video, &video->detected_timings)) {
 953                 dev_err(video->dev, "Failed to set resolution\n");
 954                 return;
 955         }
 956
 957         /* Set frame buffer physical address */
 958         regmap_write(video->vcd_regmap, VCD_FBA_ADR, video->src.dma);
 959         regmap_write(video->vcd_regmap, VCD_FBB_ADR, video->src.dma);
 960
 961         if (video->ece.enable && atomic_inc_return(&video->ece.clients) == 1) {
 962                 npcm_video_ece_ip_reset(video);
 963                 npcm_video_ece_ctrl_reset(video);
 964                 npcm_video_ece_set_fb_addr(video, video->src.dma);
 965                 npcm_video_ece_set_lp(video, video->bytesperline);
 966
 967                 dev_dbg(video->dev, "ECE open: client %d\n",
 968                         atomic_read(&video->ece.clients));
 969         }
 970 }
 971
 972 static void npcm_video_stop(struct npcm_video *video)
 973 {
 974         struct regmap *vcd = video->vcd_regmap;
 975
 976         set_bit(VIDEO_STOPPED, &video->flags);
 977
 978         regmap_write(vcd, VCD_INTE, 0);
 979         regmap_write(vcd, VCD_MODE, 0);
 980         regmap_write(vcd, VCD_RCHG, 0);
 981         regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
 982
 983         if (video->src.size)
 984                 npcm_video_free_fb(video, &video->src);
 985
 986         npcm_video_free_diff_table(video);
 987         video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
 988         video->flags = 0;
 989         video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
 990
 991         if (video->ece.enable && atomic_dec_return(&video->ece.clients) == 0) {
 992                 npcm_video_ece_stop(video);
 993                 dev_dbg(video->dev, "ECE close: client %d\n",
 994                         atomic_read(&video->ece.clients));
 995         }
 996 }
 997
 998 static unsigned int npcm_video_raw(struct npcm_video *video, int index, void *addr)
 999 {
1000         unsigned int width = video->active_timings.width;
1001         unsigned int height = video->active_timings.height;
1002         unsigned int i, len, offset, bytes = 0;
1003
1004         video->rect[index] = npcm_video_add_rect(video, index, 0, 0, width, height);
1005
1006         for (i = 0; i < height; i++) {
1007                 len = width * video->bytesperpixel;
1008                 offset = i * video->bytesperline;
1009
1010                 memcpy(addr + bytes, video->src.virt + offset, len);
1011                 bytes += len;
1012         }
1013
1014         return bytes;
1015 }
1016
1017 static unsigned int npcm_video_hextile(struct npcm_video *video, unsigned int index,
1018                                        unsigned int dma_addr, void *vaddr)
1019 {
1020         struct rect_list *rect_list;
1021         struct v4l2_rect *rect;
1022         unsigned int offset, len, bytes = 0;
1023
1024         npcm_video_ece_ctrl_reset(video);
1025         npcm_video_ece_clear_rect_offset(video);
1026         npcm_video_ece_set_fb_addr(video, video->src.dma);
1027
1028         /* Set base address of encoded data to video buffer */
1029         npcm_video_ece_set_enc_dba(video, dma_addr);
1030
1031         npcm_video_ece_set_lp(video, video->bytesperline);
1032         npcm_video_get_diff_rect(video, index);
1033
1034         list_for_each_entry(rect_list, &video->list[index], list) {
1035                 rect = &rect_list->clip.c;
1036                 offset = npcm_video_ece_read_rect_offset(video);
1037                 npcm_video_ece_enc_rect(video, rect->left, rect->top,
1038                                         rect->width, rect->height);
1039
1040                 len = npcm_video_ece_get_ed_size(video, offset, vaddr);
1041                 npcm_video_ece_prepend_rect_header(vaddr + offset,
1042                                                    rect->left, rect->top,
1043                                                    rect->width, rect->height);
1044                 bytes += len;
1045         }
1046
1047         return bytes;
1048 }
1049
1050 static irqreturn_t npcm_video_irq(int irq, void *arg)
1051 {
1052         struct npcm_video *video = arg;
1053         struct regmap *vcd = video->vcd_regmap;
1054         struct npcm_video_buffer *buf;
1055         unsigned int index, size, status, fmt;
1056         dma_addr_t dma_addr;
1057         void *addr;
1058         static const struct v4l2_event ev = {
1059                 .type = V4L2_EVENT_SOURCE_CHANGE,
1060                 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1061         };
1062
1063         regmap_read(vcd, VCD_STAT, &status);
1064         dev_dbg(video->dev, "VCD irq status 0x%x\n", status);
1065
1066         regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
1067
1068         if (test_bit(VIDEO_STOPPED, &video->flags) ||
1069             !test_bit(VIDEO_STREAMING, &video->flags))
1070                 return IRQ_NONE;
1071
1072         if (status & VCD_STAT_DONE) {
1073                 regmap_write(vcd, VCD_INTE, 0);
1074                 spin_lock(&video->lock);
1075                 clear_bit(VIDEO_CAPTURING, &video->flags);
1076                 buf = list_first_entry_or_null(&video->buffers,
1077                                                struct npcm_video_buffer, link);
1078                 if (!buf) {
1079                         spin_unlock(&video->lock);
1080                         return IRQ_NONE;
1081                 }
1082
1083                 addr = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);
1084                 index = buf->vb.vb2_buf.index;
1085                 fmt = video->pix_fmt.pixelformat;
1086
1087                 switch (fmt) {
1088                 case V4L2_PIX_FMT_RGB565:
1089                         size = npcm_video_raw(video, index, addr);
1090                         break;
1091                 case V4L2_PIX_FMT_HEXTILE:
1092                         dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
1093                         size = npcm_video_hextile(video, index, dma_addr, addr);
1094                         break;
1095                 default:
1096                         spin_unlock(&video->lock);
1097                         return IRQ_NONE;
1098                 }
1099
1100                 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1101                 buf->vb.vb2_buf.timestamp = ktime_get_ns();
1102                 buf->vb.sequence = video->sequence++;
1103                 buf->vb.field = V4L2_FIELD_NONE;
1104
1105                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
1106                 list_del(&buf->link);
1107                 spin_unlock(&video->lock);
1108
1109                 if (npcm_video_start_frame(video))
1110                         dev_err(video->dev, "Failed to capture next frame\n");
1111         }
1112
1113         /* Resolution changed */
1114         if (status & VCD_STAT_VHT_CHG || status & VCD_STAT_HAC_CHG) {
1115                 if (!test_bit(VIDEO_RES_CHANGING, &video->flags)) {
1116                         set_bit(VIDEO_RES_CHANGING, &video->flags);
1117
1118                         vb2_queue_error(&video->queue);
1119                         v4l2_event_queue(&video->vdev, &ev);
1120                 }
1121         }
1122
1123         if (status & VCD_STAT_IFOR || status & VCD_STAT_IFOT) {
1124                 dev_warn(video->dev, "VCD FIFO overrun or over thresholds\n");
1125                 if (npcm_video_start_frame(video))
1126                         dev_err(video->dev, "Failed to recover from FIFO overrun\n");
1127         }
1128
1129         return IRQ_HANDLED;
1130 }
1131
1132 static int npcm_video_querycap(struct file *file, void *fh,
1133                                struct v4l2_capability *cap)
1134 {
1135         strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver));
1136         strscpy(cap->card, "NPCM Video Engine", sizeof(cap->card));
1137
1138         return 0;
1139 }
1140
1141 static int npcm_video_enum_format(struct file *file, void *fh,
1142                                   struct v4l2_fmtdesc *f)
1143 {
1144         struct npcm_video *video = video_drvdata(file);
1145         const struct npcm_fmt *fmt;
1146
1147         if (f->index >= NUM_FORMATS)
1148                 return -EINVAL;
1149
1150         fmt = &npcm_fmt_list[f->index];
1151         if (fmt->fourcc == V4L2_PIX_FMT_HEXTILE && !video->ece.enable)
1152                 return -EINVAL;
1153
1154         f->pixelformat = fmt->fourcc;
1155         return 0;
1156 }
1157
1158 static int npcm_video_try_format(struct file *file, void *fh,
1159                                  struct v4l2_format *f)
1160 {
1161         struct npcm_video *video = video_drvdata(file);
1162         const struct npcm_fmt *fmt;
1163
1164         fmt = npcm_video_find_format(f);
1165
1166         /* If format not found or HEXTILE not supported, use RGB565 as default */
1167         if (!fmt || (fmt->fourcc == V4L2_PIX_FMT_HEXTILE && !video->ece.enable))
1168                 f->fmt.pix.pixelformat = npcm_fmt_list[0].fourcc;
1169
1170         f->fmt.pix.field = V4L2_FIELD_NONE;
1171         f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
1172         f->fmt.pix.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1173         f->fmt.pix.width = video->pix_fmt.width;
1174         f->fmt.pix.height = video->pix_fmt.height;
1175         f->fmt.pix.bytesperline = video->bytesperline;
1176         f->fmt.pix.sizeimage = video->pix_fmt.sizeimage;
1177
1178         return 0;
1179 }
1180
1181 static int npcm_video_get_format(struct file *file, void *fh,
1182                                  struct v4l2_format *f)
1183 {
1184         struct npcm_video *video = video_drvdata(file);
1185
1186         f->fmt.pix = video->pix_fmt;
1187         return 0;
1188 }
1189
1190 static int npcm_video_set_format(struct file *file, void *fh,
1191                                  struct v4l2_format *f)
1192 {
1193         struct npcm_video *video = video_drvdata(file);
1194         int ret;
1195
1196         ret = npcm_video_try_format(file, fh, f);
1197         if (ret)
1198                 return ret;
1199
1200         if (vb2_is_busy(&video->queue)) {
1201                 dev_err(video->dev, "%s device busy\n", __func__);
1202                 return -EBUSY;
1203         }
1204
1205         video->pix_fmt.pixelformat = f->fmt.pix.pixelformat;
1206         return 0;
1207 }
1208
1209 static int npcm_video_enum_input(struct file *file, void *fh,
1210                                  struct v4l2_input *inp)
1211 {
1212         struct npcm_video *video = video_drvdata(file);
1213
1214         if (inp->index)
1215                 return -EINVAL;
1216
1217         strscpy(inp->name, "Host VGA capture", sizeof(inp->name));
1218         inp->type = V4L2_INPUT_TYPE_CAMERA;
1219         inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1220         inp->status = video->v4l2_input_status;
1221
1222         return 0;
1223 }
1224
1225 static int npcm_video_get_input(struct file *file, void *fh, unsigned int *i)
1226 {
1227         *i = 0;
1228
1229         return 0;
1230 }
1231
1232 static int npcm_video_set_input(struct file *file, void *fh, unsigned int i)
1233 {
1234         if (i)
1235                 return -EINVAL;
1236
1237         return 0;
1238 }
1239
1240 static int npcm_video_set_dv_timings(struct file *file, void *fh,
1241                                      struct v4l2_dv_timings *timings)
1242 {
1243         struct npcm_video *video = video_drvdata(file);
1244         int rc;
1245
1246         if (timings->bt.width == video->active_timings.width &&
1247             timings->bt.height == video->active_timings.height)
1248                 return 0;
1249
1250         if (vb2_is_busy(&video->queue)) {
1251                 dev_err(video->dev, "%s device busy\n", __func__);
1252                 return -EBUSY;
1253         }
1254
1255         rc = npcm_video_set_resolution(video, &timings->bt);
1256         if (rc)
1257                 return rc;
1258
1259         timings->type = V4L2_DV_BT_656_1120;
1260
1261         return 0;
1262 }
1263
1264 static int npcm_video_get_dv_timings(struct file *file, void *fh,
1265                                      struct v4l2_dv_timings *timings)
1266 {
1267         struct npcm_video *video = video_drvdata(file);
1268
1269         timings->type = V4L2_DV_BT_656_1120;
1270         timings->bt = video->active_timings;
1271
1272         return 0;
1273 }
1274
1275 static int npcm_video_query_dv_timings(struct file *file, void *fh,
1276                                        struct v4l2_dv_timings *timings)
1277 {
1278         struct npcm_video *video = video_drvdata(file);
1279
1280         npcm_video_detect_resolution(video);
1281         timings->type = V4L2_DV_BT_656_1120;
1282         timings->bt = video->detected_timings;
1283
1284         return video->v4l2_input_status ? -ENOLINK : 0;
1285 }
1286
1287 static int npcm_video_enum_dv_timings(struct file *file, void *fh,
1288                                       struct v4l2_enum_dv_timings *timings)
1289 {
1290         return v4l2_enum_dv_timings_cap(timings, &npcm_video_timings_cap,
1291                                         NULL, NULL);
1292 }
1293
1294 static int npcm_video_dv_timings_cap(struct file *file, void *fh,
1295                                      struct v4l2_dv_timings_cap *cap)
1296 {
1297         *cap = npcm_video_timings_cap;
1298
1299         return 0;
1300 }
1301
1302 static int npcm_video_sub_event(struct v4l2_fh *fh,
1303                                 const struct v4l2_event_subscription *sub)
1304 {
1305         switch (sub->type) {
1306         case V4L2_EVENT_SOURCE_CHANGE:
1307                 return v4l2_src_change_event_subscribe(fh, sub);
1308         }
1309
1310         return v4l2_ctrl_subscribe_event(fh, sub);
1311 }
1312
1313 static const struct v4l2_ioctl_ops npcm_video_ioctls = {
1314         .vidioc_querycap = npcm_video_querycap,
1315
1316         .vidioc_enum_fmt_vid_cap = npcm_video_enum_format,
1317         .vidioc_g_fmt_vid_cap = npcm_video_get_format,
1318         .vidioc_s_fmt_vid_cap = npcm_video_set_format,
1319         .vidioc_try_fmt_vid_cap = npcm_video_try_format,
1320
1321         .vidioc_reqbufs = vb2_ioctl_reqbufs,
1322         .vidioc_querybuf = vb2_ioctl_querybuf,
1323         .vidioc_qbuf = vb2_ioctl_qbuf,
1324         .vidioc_expbuf = vb2_ioctl_expbuf,
1325         .vidioc_dqbuf = vb2_ioctl_dqbuf,
1326         .vidioc_create_bufs = vb2_ioctl_create_bufs,
1327         .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1328         .vidioc_streamon = vb2_ioctl_streamon,
1329         .vidioc_streamoff = vb2_ioctl_streamoff,
1330
1331         .vidioc_enum_input = npcm_video_enum_input,
1332         .vidioc_g_input = npcm_video_get_input,
1333         .vidioc_s_input = npcm_video_set_input,
1334
1335         .vidioc_s_dv_timings = npcm_video_set_dv_timings,
1336         .vidioc_g_dv_timings = npcm_video_get_dv_timings,
1337         .vidioc_query_dv_timings = npcm_video_query_dv_timings,
1338         .vidioc_enum_dv_timings = npcm_video_enum_dv_timings,
1339         .vidioc_dv_timings_cap = npcm_video_dv_timings_cap,
1340
1341         .vidioc_subscribe_event = npcm_video_sub_event,
1342         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1343 };
1344
1345 static int npcm_video_set_ctrl(struct v4l2_ctrl *ctrl)
1346 {
1347         struct npcm_video *video = container_of(ctrl->handler, struct npcm_video,
1348                                                 ctrl_handler);
1349
1350         switch (ctrl->id) {
1351         case V4L2_CID_NPCM_CAPTURE_MODE:
1352                 if (ctrl->val == V4L2_NPCM_CAPTURE_MODE_COMPLETE)
1353                         video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
1354                 else if (ctrl->val == V4L2_NPCM_CAPTURE_MODE_DIFF)
1355                         video->ctrl_cmd = VCD_CMD_OPERATION_COMPARE;
1356                 break;
1357         default:
1358                 return -EINVAL;
1359         }
1360
1361         return 0;
1362 }
1363
1364 static const struct v4l2_ctrl_ops npcm_video_ctrl_ops = {
1365         .s_ctrl = npcm_video_set_ctrl,
1366 };
1367
1368 static const char * const npcm_ctrl_capture_mode_menu[] = {
1369         "COMPLETE",
1370         "DIFF",
1371         NULL,
1372 };
1373
1374 static const struct v4l2_ctrl_config npcm_ctrl_capture_mode = {
1375         .ops = &npcm_video_ctrl_ops,
1376         .id = V4L2_CID_NPCM_CAPTURE_MODE,
1377         .name = "NPCM Video Capture Mode",
1378         .type = V4L2_CTRL_TYPE_MENU,
1379         .min = 0,
1380         .max = V4L2_NPCM_CAPTURE_MODE_DIFF,
1381         .def = 0,
1382         .qmenu = npcm_ctrl_capture_mode_menu,
1383 };
1384
1385 /*
1386  * This control value is set when a buffer is dequeued by userspace, i.e. in
1387  * npcm_video_buf_finish function.
1388  */
1389 static const struct v4l2_ctrl_config npcm_ctrl_rect_count = {
1390         .id = V4L2_CID_NPCM_RECT_COUNT,
1391         .name = "NPCM Hextile Rectangle Count",
1392         .type = V4L2_CTRL_TYPE_INTEGER,
1393         .min = 0,
1394         .max = (MAX_WIDTH / RECT_W) * (MAX_HEIGHT / RECT_H),
1395         .step = 1,
1396         .def = 0,
1397 };
1398
1399 static int npcm_video_open(struct file *file)
1400 {
1401         struct npcm_video *video = video_drvdata(file);
1402         int rc;
1403
1404         mutex_lock(&video->video_lock);
1405         rc = v4l2_fh_open(file);
1406         if (rc) {
1407                 mutex_unlock(&video->video_lock);
1408                 return rc;
1409         }
1410
1411         if (v4l2_fh_is_singular_file(file))
1412                 npcm_video_start(video);
1413
1414         mutex_unlock(&video->video_lock);
1415         return 0;
1416 }
1417
1418 static int npcm_video_release(struct file *file)
1419 {
1420         struct npcm_video *video = video_drvdata(file);
1421         int rc;
1422
1423         mutex_lock(&video->video_lock);
1424         if (v4l2_fh_is_singular_file(file))
1425                 npcm_video_stop(video);
1426
1427         rc = _vb2_fop_release(file, NULL);
1428
1429         mutex_unlock(&video->video_lock);
1430         return rc;
1431 }
1432
1433 static const struct v4l2_file_operations npcm_video_v4l2_fops = {
1434         .owner = THIS_MODULE,
1435         .read = vb2_fop_read,
1436         .poll = vb2_fop_poll,
1437         .unlocked_ioctl = video_ioctl2,
1438         .mmap = vb2_fop_mmap,
1439         .open = npcm_video_open,
1440         .release = npcm_video_release,
1441 };
1442
1443 static int npcm_video_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
1444                                   unsigned int *num_planes, unsigned int sizes[],
1445                                   struct device *alloc_devs[])
1446 {
1447         struct npcm_video *video = vb2_get_drv_priv(q);
1448         unsigned int i;
1449
1450         if (*num_planes) {
1451                 if (sizes[0] < video->pix_fmt.sizeimage)
1452                         return -EINVAL;
1453
1454                 return 0;
1455         }
1456
1457         *num_planes = 1;
1458         sizes[0] = video->pix_fmt.sizeimage;
1459
1460         for (i = 0; i < VIDEO_MAX_FRAME; i++)
1461                 INIT_LIST_HEAD(&video->list[i]);
1462
1463         return 0;
1464 }
1465
1466 static int npcm_video_buf_prepare(struct vb2_buffer *vb)
1467 {
1468         struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1469
1470         if (vb2_plane_size(vb, 0) < video->pix_fmt.sizeimage)
1471                 return -EINVAL;
1472
1473         return 0;
1474 }
1475
1476 static int npcm_video_start_streaming(struct vb2_queue *q, unsigned int count)
1477 {
1478         struct npcm_video *video = vb2_get_drv_priv(q);
1479         int rc;
1480
1481         video->sequence = 0;
1482         rc = npcm_video_start_frame(video);
1483         if (rc) {
1484                 npcm_video_bufs_done(video, VB2_BUF_STATE_QUEUED);
1485                 return rc;
1486         }
1487
1488         set_bit(VIDEO_STREAMING, &video->flags);
1489         return 0;
1490 }
1491
1492 static void npcm_video_stop_streaming(struct vb2_queue *q)
1493 {
1494         struct npcm_video *video = vb2_get_drv_priv(q);
1495         struct regmap *vcd = video->vcd_regmap;
1496
1497         clear_bit(VIDEO_STREAMING, &video->flags);
1498         regmap_write(vcd, VCD_INTE, 0);
1499         regmap_write(vcd, VCD_STAT, VCD_STAT_CLEAR);
1500         npcm_video_gfx_reset(video);
1501         npcm_video_bufs_done(video, VB2_BUF_STATE_ERROR);
1502         video->ctrl_cmd = VCD_CMD_OPERATION_CAPTURE;
1503         v4l2_ctrl_s_ctrl(video->rect_cnt_ctrl, 0);
1504 }
1505
1506 static void npcm_video_buf_queue(struct vb2_buffer *vb)
1507 {
1508         struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1509         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1510         struct npcm_video_buffer *nvb = to_npcm_video_buffer(vbuf);
1511         unsigned long flags;
1512         bool empty;
1513
1514         spin_lock_irqsave(&video->lock, flags);
1515         empty = list_empty(&video->buffers);
1516         list_add_tail(&nvb->link, &video->buffers);
1517         spin_unlock_irqrestore(&video->lock, flags);
1518
1519         if (test_bit(VIDEO_STREAMING, &video->flags) &&
1520             !test_bit(VIDEO_CAPTURING, &video->flags) && empty) {
1521                 if (npcm_video_start_frame(video))
1522                         dev_err(video->dev, "Failed to capture next frame\n");
1523         }
1524 }
1525
1526 static void npcm_video_buf_finish(struct vb2_buffer *vb)
1527 {
1528         struct npcm_video *video = vb2_get_drv_priv(vb->vb2_queue);
1529         struct list_head *head, *pos, *nx;
1530         struct rect_list *tmp;
1531
1532         /*
1533          * This callback is called when the buffer is dequeued, so update
1534          * V4L2_CID_NPCM_RECT_COUNT control value with the number of rectangles
1535          * in this buffer and free associated rect_list.
1536          */
1537         if (test_bit(VIDEO_STREAMING, &video->flags)) {
1538                 v4l2_ctrl_s_ctrl(video->rect_cnt_ctrl, video->rect[vb->index]);
1539
1540                 head = &video->list[vb->index];
1541                 list_for_each_safe(pos, nx, head) {
1542                         tmp = list_entry(pos, struct rect_list, list);
1543                         list_del(&tmp->list);
1544                         kfree(tmp);
1545                 }
1546         }
1547 }
1548
1549 static const struct regmap_config npcm_video_regmap_cfg = {
1550         .reg_bits       = 32,
1551         .reg_stride     = 4,
1552         .val_bits       = 32,
1553         .max_register   = VCD_FIFO,
1554 };
1555
1556 static const struct regmap_config npcm_video_ece_regmap_cfg = {
1557         .reg_bits       = 32,
1558         .reg_stride     = 4,
1559         .val_bits       = 32,
1560         .max_register   = ECE_HEX_RECT_OFFSET,
1561 };
1562
1563 static const struct vb2_ops npcm_video_vb2_ops = {
1564         .queue_setup = npcm_video_queue_setup,
1565         .wait_prepare = vb2_ops_wait_prepare,
1566         .wait_finish = vb2_ops_wait_finish,
1567         .buf_prepare = npcm_video_buf_prepare,
1568         .buf_finish = npcm_video_buf_finish,
1569         .start_streaming = npcm_video_start_streaming,
1570         .stop_streaming = npcm_video_stop_streaming,
1571         .buf_queue =  npcm_video_buf_queue,
1572 };
1573
1574 static int npcm_video_setup_video(struct npcm_video *video)
1575 {
1576         struct v4l2_device *v4l2_dev = &video->v4l2_dev;
1577         struct video_device *vdev = &video->vdev;
1578         struct vb2_queue *vbq = &video->queue;
1579         int rc;
1580
1581         if (video->ece.enable)
1582                 video->pix_fmt.pixelformat = V4L2_PIX_FMT_HEXTILE;
1583         else
1584                 video->pix_fmt.pixelformat = V4L2_PIX_FMT_RGB565;
1585
1586         video->pix_fmt.field = V4L2_FIELD_NONE;
1587         video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB;
1588         video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1589         video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
1590
1591         rc = v4l2_device_register(video->dev, v4l2_dev);
1592         if (rc) {
1593                 dev_err(video->dev, "Failed to register v4l2 device\n");
1594                 return rc;
1595         }
1596
1597         v4l2_ctrl_handler_init(&video->ctrl_handler, 2);
1598         v4l2_ctrl_new_custom(&video->ctrl_handler, &npcm_ctrl_capture_mode, NULL);
1599         video->rect_cnt_ctrl = v4l2_ctrl_new_custom(&video->ctrl_handler,
1600                                                     &npcm_ctrl_rect_count, NULL);
1601         if (video->ctrl_handler.error) {
1602                 dev_err(video->dev, "Failed to init controls: %d\n",
1603                         video->ctrl_handler.error);
1604
1605                 rc = video->ctrl_handler.error;
1606                 goto rel_ctrl_handler;
1607         }
1608         v4l2_dev->ctrl_handler = &video->ctrl_handler;
1609
1610         vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1611         vbq->io_modes = VB2_MMAP | VB2_DMABUF;
1612         vbq->dev = v4l2_dev->dev;
1613         vbq->lock = &video->video_lock;
1614         vbq->ops = &npcm_video_vb2_ops;
1615         vbq->mem_ops = &vb2_dma_contig_memops;
1616         vbq->drv_priv = video;
1617         vbq->buf_struct_size = sizeof(struct npcm_video_buffer);
1618         vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1619         vbq->min_buffers_needed = 3;
1620
1621         rc = vb2_queue_init(vbq);
1622         if (rc) {
1623                 dev_err(video->dev, "Failed to init vb2 queue\n");
1624                 goto rel_ctrl_handler;
1625         }
1626         vdev->queue = vbq;
1627         vdev->fops = &npcm_video_v4l2_fops;
1628         vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1629         vdev->v4l2_dev = v4l2_dev;
1630         strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name));
1631         vdev->vfl_type = VFL_TYPE_VIDEO;
1632         vdev->vfl_dir = VFL_DIR_RX;
1633         vdev->release = video_device_release_empty;
1634         vdev->ioctl_ops = &npcm_video_ioctls;
1635         vdev->lock = &video->video_lock;
1636
1637         video_set_drvdata(vdev, video);
1638         rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0);
1639         if (rc) {
1640                 dev_err(video->dev, "Failed to register video device\n");
1641                 goto rel_vb_queue;
1642         }
1643
1644         return 0;
1645
1646 rel_vb_queue:
1647         vb2_queue_release(vbq);
1648 rel_ctrl_handler:
1649         v4l2_ctrl_handler_free(&video->ctrl_handler);
1650         v4l2_device_unregister(v4l2_dev);
1651
1652         return rc;
1653 }
1654
1655 static int npcm_video_ece_init(struct npcm_video *video)
1656 {
1657         struct device *dev = video->dev;
1658         struct device_node *ece_node;
1659         struct platform_device *ece_pdev;
1660         void __iomem *regs;
1661
1662         ece_node = of_parse_phandle(video->dev->of_node, "nuvoton,ece", 0);
1663         if (!ece_node) {
1664                 dev_err(dev, "Failed to get ECE phandle in DTS\n");
1665                 return -ENODEV;
1666         }
1667
1668         video->ece.enable = of_device_is_available(ece_node);
1669
1670         if (video->ece.enable) {
1671                 dev_info(dev, "Support HEXTILE pixel format\n");
1672
1673                 ece_pdev = of_find_device_by_node(ece_node);
1674                 if (IS_ERR(ece_pdev)) {
1675                         dev_err(dev, "Failed to find ECE device\n");
1676                         return PTR_ERR(ece_pdev);
1677                 }
1678                 of_node_put(ece_node);
1679
1680                 regs = devm_platform_ioremap_resource(ece_pdev, 0);
1681                 if (IS_ERR(regs)) {
1682                         dev_err(dev, "Failed to parse ECE reg in DTS\n");
1683                         return PTR_ERR(regs);
1684                 }
1685
1686                 video->ece.regmap = devm_regmap_init_mmio(dev, regs,
1687                                                           &npcm_video_ece_regmap_cfg);
1688                 if (IS_ERR(video->ece.regmap)) {
1689                         dev_err(dev, "Failed to initialize ECE regmap\n");
1690                         return PTR_ERR(video->ece.regmap);
1691                 }
1692
1693                 video->ece.reset = devm_reset_control_get(&ece_pdev->dev, NULL);
1694                 if (IS_ERR(video->ece.reset)) {
1695                         dev_err(dev, "Failed to get ECE reset control in DTS\n");
1696                         return PTR_ERR(video->ece.reset);
1697                 }
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int npcm_video_init(struct npcm_video *video)
1704 {
1705         struct device *dev = video->dev;
1706         int irq, rc;
1707
1708         irq = irq_of_parse_and_map(dev->of_node, 0);
1709         if (!irq) {
1710                 dev_err(dev, "Failed to find VCD IRQ\n");
1711                 return -ENODEV;
1712         }
1713
1714         rc = devm_request_threaded_irq(dev, irq, NULL, npcm_video_irq,
1715                                        IRQF_ONESHOT, DEVICE_NAME, video);
1716         if (rc < 0) {
1717                 dev_err(dev, "Failed to request IRQ %d\n", irq);
1718                 return rc;
1719         }
1720
1721         of_reserved_mem_device_init(dev);
1722         rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
1723         if (rc) {
1724                 dev_err(dev, "Failed to set DMA mask\n");
1725                 of_reserved_mem_device_release(dev);
1726         }
1727
1728         rc = npcm_video_ece_init(video);
1729         if (rc) {
1730                 dev_err(dev, "Failed to initialize ECE\n");
1731                 return rc;
1732         }
1733
1734         return 0;
1735 }
1736
1737 static int npcm_video_probe(struct platform_device *pdev)
1738 {
1739         struct npcm_video *video = kzalloc(sizeof(*video), GFP_KERNEL);
1740         int rc;
1741         void __iomem *regs;
1742
1743         if (!video)
1744                 return -ENOMEM;
1745
1746         video->dev = &pdev->dev;
1747         spin_lock_init(&video->lock);
1748         mutex_init(&video->video_lock);
1749         INIT_LIST_HEAD(&video->buffers);
1750
1751         regs = devm_platform_ioremap_resource(pdev, 0);
1752         if (IS_ERR(regs)) {
1753                 dev_err(&pdev->dev, "Failed to parse VCD reg in DTS\n");
1754                 return PTR_ERR(regs);
1755         }
1756
1757         video->vcd_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1758                                                   &npcm_video_regmap_cfg);
1759         if (IS_ERR(video->vcd_regmap)) {
1760                 dev_err(&pdev->dev, "Failed to initialize VCD regmap\n");
1761                 return PTR_ERR(video->vcd_regmap);
1762         }
1763
1764         video->reset = devm_reset_control_get(&pdev->dev, NULL);
1765         if (IS_ERR(video->reset)) {
1766                 dev_err(&pdev->dev, "Failed to get VCD reset control in DTS\n");
1767                 return PTR_ERR(video->reset);
1768         }
1769
1770         video->gcr_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1771                                                             "nuvoton,sysgcr");
1772         if (IS_ERR(video->gcr_regmap))
1773                 return PTR_ERR(video->gcr_regmap);
1774
1775         video->gfx_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1776                                                             "nuvoton,sysgfxi");
1777         if (IS_ERR(video->gfx_regmap))
1778                 return PTR_ERR(video->gfx_regmap);
1779
1780         rc = npcm_video_init(video);
1781         if (rc)
1782                 return rc;
1783
1784         rc = npcm_video_setup_video(video);
1785         if (rc)
1786                 return rc;
1787
1788         dev_info(video->dev, "NPCM video driver probed\n");
1789         return 0;
1790 }
1791
1792 static int npcm_video_remove(struct platform_device *pdev)
1793 {
1794         struct device *dev = &pdev->dev;
1795         struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
1796         struct npcm_video *video = to_npcm_video(v4l2_dev);
1797
1798         video_unregister_device(&video->vdev);
1799         vb2_queue_release(&video->queue);
1800         v4l2_ctrl_handler_free(&video->ctrl_handler);
1801         v4l2_device_unregister(v4l2_dev);
1802         if (video->ece.enable)
1803                 npcm_video_ece_stop(video);
1804         of_reserved_mem_device_release(dev);
1805
1806         return 0;
1807 }
1808
1809 static const struct of_device_id npcm_video_match[] = {
1810         { .compatible = "nuvoton,npcm750-vcd" },
1811         { .compatible = "nuvoton,npcm845-vcd" },
1812         {},
1813 };
1814
1815 MODULE_DEVICE_TABLE(of, npcm_video_match);
1816
1817 static struct platform_driver npcm_video_driver = {
1818         .driver = {
1819                 .name = DEVICE_NAME,
1820                 .of_match_table = npcm_video_match,
1821         },
1822         .probe = npcm_video_probe,
1823         .remove = npcm_video_remove,
1824 };
1825
1826 module_platform_driver(npcm_video_driver);
1827
1828 MODULE_AUTHOR("Joseph Liu <kwliu@nuvoton.com>");
1829 MODULE_AUTHOR("Marvin Lin <kflin@nuvoton.com>");
1830 MODULE_DESCRIPTION("Driver for Nuvoton NPCM Video Capture/Encode Engine");
1831 MODULE_LICENSE("GPL v2");