1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Yunfei Dong <yunfei.dong@mediatek.com>
7 #ifndef _MTK_VCODEC_DEC_HW_H_
8 #define _MTK_VCODEC_DEC_HW_H_
11 #include <linux/platform_device.h>
13 #include "mtk_vcodec_drv.h"
15 #define VDEC_HW_ACTIVE 0x10
16 #define VDEC_IRQ_CFG 0x11
17 #define VDEC_IRQ_CLR 0x10
18 #define VDEC_IRQ_CFG_REG 0xa4
21 * enum mtk_vdec_hw_reg_idx - subdev hardware register base index
22 * @VDEC_HW_SYS : vdec soc register index
23 * @VDEC_HW_MISC: vdec misc register index
24 * @VDEC_HW_MAX : vdec supported max register index
26 enum mtk_vdec_hw_reg_idx {
33 * struct mtk_vdec_hw_dev - vdec hardware driver data
34 * @plat_dev: platform device
35 * @main_dev: main device
36 * @reg_base: mapped address of MTK Vcodec registers.
38 * @curr_ctx: the context that is waiting for codec hardware
40 * @dec_irq : decoder irq resource
41 * @pm : power management control
42 * @hw_idx : each hardware index
44 struct mtk_vdec_hw_dev {
45 struct platform_device *plat_dev;
46 struct mtk_vcodec_dev *main_dev;
47 void __iomem *reg_base[VDEC_HW_MAX];
49 struct mtk_vcodec_ctx *curr_ctx;
52 struct mtk_vcodec_pm pm;
56 #endif /* _MTK_VCODEC_DEC_HW_H_ */