1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
7 #ifndef __MTK_MDP3_COMP_H__
8 #define __MTK_MDP3_COMP_H__
10 #include "mtk-mdp3-cmdq.h"
12 #define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask, ...) \
13 cmdq_pkt_write_mask(&((cmd)->pkt), id, \
14 (base) + (ofst), (val), (mask), ##__VA_ARGS__)
16 #define MM_REG_WRITE(cmd, id, base, ofst, val, mask, ...) \
18 typeof(mask) (m) = (mask); \
19 MM_REG_WRITE_MASK(cmd, id, base, ofst, val, \
20 (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \
21 (0xffffffff) : (m), ##__VA_ARGS__); \
24 #define MM_REG_WAIT(cmd, evt) \
26 typeof(cmd) (c) = (cmd); \
27 typeof(evt) (e) = (evt); \
28 cmdq_pkt_wfe(&((c)->pkt), (e), true); \
31 #define MM_REG_WAIT_NO_CLEAR(cmd, evt) \
33 typeof(cmd) (c) = (cmd); \
34 typeof(evt) (e) = (evt); \
35 cmdq_pkt_wfe(&((c)->pkt), (e), false); \
38 #define MM_REG_CLEAR(cmd, evt) \
40 typeof(cmd) (c) = (cmd); \
41 typeof(evt) (e) = (evt); \
42 cmdq_pkt_clear_event(&((c)->pkt), (e)); \
45 #define MM_REG_SET_EVENT(cmd, evt) \
47 typeof(cmd) (c) = (cmd); \
48 typeof(evt) (e) = (evt); \
49 cmdq_pkt_set_event(&((c)->pkt), (e)); \
52 #define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask, ...) \
54 typeof(_mask) (_m) = (_mask); \
55 cmdq_pkt_poll_mask(&((cmd)->pkt), id, \
56 (base) + (ofst), (val), (_m), ##__VA_ARGS__); \
59 #define MM_REG_POLL(cmd, id, base, ofst, val, mask, ...) \
61 typeof(mask) (m) = (mask); \
62 MM_REG_POLL_MASK((cmd), id, base, ofst, val, \
63 (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \
64 (0xffffffff) : (m), ##__VA_ARGS__); \
67 enum mtk_mdp_comp_id {
68 MDP_COMP_NONE = -1, /* Invalid engine */
72 MDP_COMP_WPEO, /* 1 */
73 MDP_COMP_WPEI2, /* 2 */
74 MDP_COMP_WPEO2, /* 3 */
75 MDP_COMP_ISP_IMGI, /* 4 */
76 MDP_COMP_ISP_IMGO, /* 5 */
77 MDP_COMP_ISP_IMG2O, /* 6 */
80 MDP_COMP_IPUI, /* 7 */
81 MDP_COMP_IPUO, /* 8 */
84 MDP_COMP_CAMIN, /* 9 */
85 MDP_COMP_CAMIN2, /* 10 */
86 MDP_COMP_RDMA0, /* 11 */
87 MDP_COMP_AAL0, /* 12 */
88 MDP_COMP_CCORR0, /* 13 */
89 MDP_COMP_RSZ0, /* 14 */
90 MDP_COMP_RSZ1, /* 15 */
91 MDP_COMP_TDSHP0, /* 16 */
92 MDP_COMP_COLOR0, /* 17 */
93 MDP_COMP_PATH0_SOUT, /* 18 */
94 MDP_COMP_PATH1_SOUT, /* 19 */
95 MDP_COMP_WROT0, /* 20 */
96 MDP_COMP_WDMA, /* 21 */
99 MDP_COMP_RDMA1, /* 22 */
100 MDP_COMP_RSZ2, /* 23 */
101 MDP_COMP_TDSHP1, /* 24 */
102 MDP_COMP_WROT1, /* 25 */
104 MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
108 MDP_COMP_TYPE_INVALID = 0,
124 MDP_COMP_TYPE_EXTO, /* External path */
125 MDP_COMP_TYPE_DL_PATH, /* Direct-link path */
127 MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */
130 #define MDP_GCE_NO_EVENT (-1)
132 MDP_GCE_EVENT_SOF = 0,
133 MDP_GCE_EVENT_EOF = 1,
137 struct mdp_comp_match {
138 enum mdp_comp_type type;
143 /* Used to describe the item order in MDP property */
144 struct mdp_comp_info {
150 struct mdp_comp_data {
151 struct mdp_comp_match match;
152 struct mdp_comp_info info;
158 struct mdp_dev *mdp_dev;
160 phys_addr_t reg_base;
164 struct device *comp_dev;
165 enum mdp_comp_type type;
166 enum mtk_mdp_comp_id public_id;
169 s32 gce_event[MDP_GCE_EVENT_MAX];
170 const struct mdp_comp_ops *ops;
173 struct mdp_comp_ctx {
174 struct mdp_comp *comp;
175 const struct img_compparam *param;
176 const struct img_input *input;
177 const struct img_output *outputs[IMG_MAX_HW_OUTPUTS];
180 struct mdp_comp_ops {
181 s64 (*get_comp_flag)(const struct mdp_comp_ctx *ctx);
182 int (*init_comp)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd);
183 int (*config_frame)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd,
184 const struct v4l2_rect *compose);
185 int (*config_subfrm)(struct mdp_comp_ctx *ctx,
186 struct mdp_cmdq_cmd *cmd, u32 index);
187 int (*wait_comp_event)(struct mdp_comp_ctx *ctx,
188 struct mdp_cmdq_cmd *cmd);
189 int (*advance_subfrm)(struct mdp_comp_ctx *ctx,
190 struct mdp_cmdq_cmd *cmd, u32 index);
191 int (*post_process)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd);
196 int mdp_comp_config(struct mdp_dev *mdp);
197 void mdp_comp_destroy(struct mdp_dev *mdp);
198 int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp);
199 void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp);
200 int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num);
201 void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
202 int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
203 const struct img_compparam *param,
204 const struct img_ipi_frameparam *frame);
206 #endif /* __MTK_MDP3_COMP_H__ */