1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
8 #include <linux/of_platform.h>
9 #include <linux/of_address.h>
10 #include <linux/pm_runtime.h>
11 #include "mtk-mdp3-cfg.h"
12 #include "mtk-mdp3-comp.h"
13 #include "mtk-mdp3-core.h"
14 #include "mtk-mdp3-regs.h"
16 #include "mdp_reg_rdma.h"
17 #include "mdp_reg_ccorr.h"
18 #include "mdp_reg_rsz.h"
19 #include "mdp_reg_wrot.h"
20 #include "mdp_reg_wdma.h"
22 static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT];
25 static inline const struct mdp_platform_config *
26 __get_plat_cfg(const struct mdp_comp_ctx *ctx)
31 return ctx->comp->mdp_dev->mdp_data->mdp_cfg;
34 static s64 get_comp_flag(const struct mdp_comp_ctx *ctx)
36 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
39 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
40 rsz1 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RSZ1);
44 if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing)
45 if (ctx->comp->inner_id == rdma0)
46 return BIT(rdma0) | BIT(rsz1);
48 return BIT(ctx->comp->inner_id);
51 static int init_rdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
53 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
54 phys_addr_t base = ctx->comp->reg_base;
55 u8 subsys_id = ctx->comp->subsys_id;
58 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
62 if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
63 struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1];
66 if (ctx->comp->inner_id == rdma0 && prz1)
67 MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE,
72 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0));
73 MM_REG_POLL(cmd, subsys_id, base, MDP_RDMA_MON_STA_1, BIT(8), BIT(8));
74 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0));
78 static int config_rdma_frame(struct mdp_comp_ctx *ctx,
79 struct mdp_cmdq_cmd *cmd,
80 const struct v4l2_rect *compose)
82 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
83 u32 colorformat = ctx->input->buffer.format.colorformat;
84 bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat);
85 bool en_ufo = MDP_COLOR_IS_UFP(colorformat);
86 phys_addr_t base = ctx->comp->reg_base;
87 u8 subsys_id = ctx->comp->subsys_id;
90 if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
92 MM_REG_WRITE(cmd, subsys_id, base,
93 MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7);
95 MM_REG_WRITE(cmd, subsys_id, base,
96 MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7);
99 /* Setup smi control */
100 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON,
101 (7 << 4) + //burst type to 8
102 (1 << 16), //enable pre-ultra
105 /* Setup source frame info */
106 if (CFG_CHECK(MT8183, p_id))
107 reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl);
108 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg,
112 if (mdp_cfg->rdma_support_10bit && en_ufo) {
113 /* Setup source buffer base */
114 if (CFG_CHECK(MT8183, p_id))
115 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y);
116 MM_REG_WRITE(cmd, subsys_id,
117 base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y,
119 if (CFG_CHECK(MT8183, p_id))
120 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c);
121 MM_REG_WRITE(cmd, subsys_id,
122 base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C,
124 /* Set 10bit source frame pitch */
126 if (CFG_CHECK(MT8183, p_id))
127 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl);
128 MM_REG_WRITE(cmd, subsys_id,
129 base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL,
134 if (CFG_CHECK(MT8183, p_id))
135 reg = CFG_COMP(MT8183, ctx->param, rdma.control);
136 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg,
138 /* Setup source buffer base */
139 if (CFG_CHECK(MT8183, p_id))
140 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]);
141 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg,
143 if (CFG_CHECK(MT8183, p_id))
144 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]);
145 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg,
147 if (CFG_CHECK(MT8183, p_id))
148 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]);
149 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg,
151 /* Setup source buffer end */
152 if (CFG_CHECK(MT8183, p_id))
153 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]);
154 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0,
156 if (CFG_CHECK(MT8183, p_id))
157 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]);
158 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1,
160 if (CFG_CHECK(MT8183, p_id))
161 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]);
162 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2,
164 /* Setup source frame pitch */
165 if (CFG_CHECK(MT8183, p_id))
166 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd);
167 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
169 if (CFG_CHECK(MT8183, p_id))
170 reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd);
171 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
173 /* Setup color transform */
174 if (CFG_CHECK(MT8183, p_id))
175 reg = CFG_COMP(MT8183, ctx->param, rdma.transform);
176 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0,
182 static int config_rdma_subfrm(struct mdp_comp_ctx *ctx,
183 struct mdp_cmdq_cmd *cmd, u32 index)
185 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
186 u32 colorformat = ctx->input->buffer.format.colorformat;
187 bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat);
188 bool en_ufo = MDP_COLOR_IS_UFP(colorformat);
189 phys_addr_t base = ctx->comp->reg_base;
190 u8 subsys_id = ctx->comp->subsys_id;
191 u32 csf_l = 0, csf_r = 0;
195 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));
197 /* Set Y pixel offset */
198 if (CFG_CHECK(MT8183, p_id))
199 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]);
200 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0,
203 /* Set 10bit UFO mode */
205 if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) {
206 if (CFG_CHECK(MT8183, p_id))
207 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p);
208 MM_REG_WRITE(cmd, subsys_id, base,
209 MDP_RDMA_SRC_OFFSET_0_P,
214 /* Set U pixel offset */
215 if (CFG_CHECK(MT8183, p_id))
216 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]);
217 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1,
219 /* Set V pixel offset */
220 if (CFG_CHECK(MT8183, p_id))
221 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]);
222 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2,
224 /* Set source size */
225 if (CFG_CHECK(MT8183, p_id))
226 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src);
227 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg,
229 /* Set target size */
230 if (CFG_CHECK(MT8183, p_id))
231 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip);
232 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE,
234 /* Set crop offset */
235 if (CFG_CHECK(MT8183, p_id))
236 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst);
237 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1,
240 if (CFG_CHECK(MT8183, p_id)) {
241 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
242 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
244 if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only)
245 if ((csf_r - csf_l + 1) > 320)
246 MM_REG_WRITE(cmd, subsys_id, base,
247 MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2));
252 static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
254 struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
255 phys_addr_t base = ctx->comp->reg_base;
256 u8 subsys_id = ctx->comp->subsys_id;
258 if (ctx->comp->alias_id == 0)
259 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]);
261 dev_err(dev, "Do not support RDMA1_DONE event\n");
264 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
268 static const struct mdp_comp_ops rdma_ops = {
269 .get_comp_flag = get_comp_flag,
270 .init_comp = init_rdma,
271 .config_frame = config_rdma_frame,
272 .config_subfrm = config_rdma_subfrm,
273 .wait_comp_event = wait_rdma_event,
276 static int init_rsz(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
278 phys_addr_t base = ctx->comp->reg_base;
279 u8 subsys_id = ctx->comp->subsys_id;
282 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16));
283 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16));
285 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0));
289 static int config_rsz_frame(struct mdp_comp_ctx *ctx,
290 struct mdp_cmdq_cmd *cmd,
291 const struct v4l2_rect *compose)
293 phys_addr_t base = ctx->comp->reg_base;
294 u8 subsys_id = ctx->comp->subsys_id;
298 if (CFG_CHECK(MT8183, p_id))
299 bypass = CFG_COMP(MT8183, ctx->param, frame.bypass);
303 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0));
307 if (CFG_CHECK(MT8183, p_id))
308 reg = CFG_COMP(MT8183, ctx->param, rsz.control1);
309 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg,
311 if (CFG_CHECK(MT8183, p_id))
312 reg = CFG_COMP(MT8183, ctx->param, rsz.control2);
313 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg,
315 if (CFG_CHECK(MT8183, p_id))
316 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x);
317 MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP,
319 if (CFG_CHECK(MT8183, p_id))
320 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y);
321 MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP,
326 static int config_rsz_subfrm(struct mdp_comp_ctx *ctx,
327 struct mdp_cmdq_cmd *cmd, u32 index)
329 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
330 phys_addr_t base = ctx->comp->reg_base;
331 u8 subsys_id = ctx->comp->subsys_id;
332 u32 csf_l = 0, csf_r = 0;
335 if (CFG_CHECK(MT8183, p_id))
336 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2);
337 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg,
339 if (CFG_CHECK(MT8183, p_id))
340 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src);
341 MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg,
344 if (CFG_CHECK(MT8183, p_id)) {
345 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
346 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
348 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample)
349 if ((csf_r - csf_l + 1) <= 16)
350 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1,
353 if (CFG_CHECK(MT8183, p_id))
354 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left);
355 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET,
357 if (CFG_CHECK(MT8183, p_id))
358 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix);
359 MM_REG_WRITE(cmd, subsys_id,
360 base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET,
362 if (CFG_CHECK(MT8183, p_id))
363 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top);
364 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET,
366 if (CFG_CHECK(MT8183, p_id))
367 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix);
368 MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET,
370 if (CFG_CHECK(MT8183, p_id))
371 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left);
372 MM_REG_WRITE(cmd, subsys_id,
373 base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET,
375 if (CFG_CHECK(MT8183, p_id))
376 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix);
377 MM_REG_WRITE(cmd, subsys_id,
378 base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET,
381 if (CFG_CHECK(MT8183, p_id))
382 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip);
383 MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg,
389 static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx,
390 struct mdp_cmdq_cmd *cmd, u32 index)
392 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
394 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) {
395 phys_addr_t base = ctx->comp->reg_base;
396 u8 subsys_id = ctx->comp->subsys_id;
397 u32 csf_l = 0, csf_r = 0;
399 if (CFG_CHECK(MT8183, p_id)) {
400 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
401 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
404 if ((csf_r - csf_l + 1) <= 16)
405 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0,
412 static const struct mdp_comp_ops rsz_ops = {
413 .get_comp_flag = get_comp_flag,
414 .init_comp = init_rsz,
415 .config_frame = config_rsz_frame,
416 .config_subfrm = config_rsz_subfrm,
417 .advance_subfrm = advance_rsz_subfrm,
420 static int init_wrot(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
422 phys_addr_t base = ctx->comp->reg_base;
423 u8 subsys_id = ctx->comp->subsys_id;
426 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0));
427 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0));
428 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0));
429 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0));
433 static int config_wrot_frame(struct mdp_comp_ctx *ctx,
434 struct mdp_cmdq_cmd *cmd,
435 const struct v4l2_rect *compose)
437 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
438 phys_addr_t base = ctx->comp->reg_base;
439 u8 subsys_id = ctx->comp->subsys_id;
442 /* Write frame base address */
443 if (CFG_CHECK(MT8183, p_id))
444 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]);
445 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg,
447 if (CFG_CHECK(MT8183, p_id))
448 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]);
449 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg,
451 if (CFG_CHECK(MT8183, p_id))
452 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]);
453 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg,
455 /* Write frame related registers */
456 if (CFG_CHECK(MT8183, p_id))
457 reg = CFG_COMP(MT8183, ctx->param, wrot.control);
458 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg,
460 /* Write frame Y pitch */
461 if (CFG_CHECK(MT8183, p_id))
462 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]);
463 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg,
465 /* Write frame UV pitch */
466 if (CFG_CHECK(MT8183, p_id))
467 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]);
468 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg,
470 if (CFG_CHECK(MT8183, p_id))
471 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]);
472 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg,
474 /* Write matrix control */
475 if (CFG_CHECK(MT8183, p_id))
476 reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl);
477 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3);
479 /* Set the fixed ALPHA as 0xFF */
480 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000,
482 /* Set VIDO_EOL_SEL */
483 MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31));
484 /* Set VIDO_FIFO_TEST */
485 if (CFG_CHECK(MT8183, p_id))
486 reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test);
488 MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST,
491 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) {
492 if (CFG_CHECK(MT8183, p_id))
493 reg = CFG_COMP(MT8183, ctx->param, wrot.filter);
494 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
501 static int config_wrot_subfrm(struct mdp_comp_ctx *ctx,
502 struct mdp_cmdq_cmd *cmd, u32 index)
504 phys_addr_t base = ctx->comp->reg_base;
505 u8 subsys_id = ctx->comp->subsys_id;
508 /* Write Y pixel offset */
509 if (CFG_CHECK(MT8183, p_id))
510 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]);
511 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR,
513 /* Write U pixel offset */
514 if (CFG_CHECK(MT8183, p_id))
515 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]);
516 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C,
518 /* Write V pixel offset */
519 if (CFG_CHECK(MT8183, p_id))
520 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]);
521 MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V,
523 /* Write source size */
524 if (CFG_CHECK(MT8183, p_id))
525 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src);
526 MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg,
528 /* Write target size */
529 if (CFG_CHECK(MT8183, p_id))
530 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip);
531 MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg,
533 if (CFG_CHECK(MT8183, p_id))
534 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst);
535 MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg,
538 if (CFG_CHECK(MT8183, p_id))
539 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf);
540 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
544 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0));
549 static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
551 const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
552 struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
553 phys_addr_t base = ctx->comp->reg_base;
554 u8 subsys_id = ctx->comp->subsys_id;
556 if (ctx->comp->alias_id == 0)
557 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]);
559 dev_err(dev, "Do not support WROT1_DONE event\n");
561 if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
562 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0,
566 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0));
571 static const struct mdp_comp_ops wrot_ops = {
572 .get_comp_flag = get_comp_flag,
573 .init_comp = init_wrot,
574 .config_frame = config_wrot_frame,
575 .config_subfrm = config_wrot_subfrm,
576 .wait_comp_event = wait_wrot_event,
579 static int init_wdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
581 phys_addr_t base = ctx->comp->reg_base;
582 u8 subsys_id = ctx->comp->subsys_id;
585 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0));
586 MM_REG_POLL(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0));
587 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0));
591 static int config_wdma_frame(struct mdp_comp_ctx *ctx,
592 struct mdp_cmdq_cmd *cmd,
593 const struct v4l2_rect *compose)
595 phys_addr_t base = ctx->comp->reg_base;
596 u8 subsys_id = ctx->comp->subsys_id;
599 MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050,
602 /* Setup frame information */
603 if (CFG_CHECK(MT8183, p_id))
604 reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg);
605 MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg,
607 /* Setup frame base address */
608 if (CFG_CHECK(MT8183, p_id))
609 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]);
610 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg,
612 if (CFG_CHECK(MT8183, p_id))
613 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]);
614 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg,
616 if (CFG_CHECK(MT8183, p_id))
617 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]);
618 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg,
621 if (CFG_CHECK(MT8183, p_id))
622 reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte);
623 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE,
626 if (CFG_CHECK(MT8183, p_id))
627 reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride);
628 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH,
630 /* Set the fixed ALPHA as 0xFF */
631 MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF,
637 static int config_wdma_subfrm(struct mdp_comp_ctx *ctx,
638 struct mdp_cmdq_cmd *cmd, u32 index)
640 phys_addr_t base = ctx->comp->reg_base;
641 u8 subsys_id = ctx->comp->subsys_id;
644 /* Write Y pixel offset */
645 if (CFG_CHECK(MT8183, p_id))
646 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]);
647 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET,
649 /* Write U pixel offset */
650 if (CFG_CHECK(MT8183, p_id))
651 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]);
652 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET,
654 /* Write V pixel offset */
655 if (CFG_CHECK(MT8183, p_id))
656 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]);
657 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET,
659 /* Write source size */
660 if (CFG_CHECK(MT8183, p_id))
661 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src);
662 MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg,
664 /* Write target size */
665 if (CFG_CHECK(MT8183, p_id))
666 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip);
667 MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg,
669 /* Write clip offset */
670 if (CFG_CHECK(MT8183, p_id))
671 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst);
672 MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg,
676 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0));
681 static int wait_wdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
683 phys_addr_t base = ctx->comp->reg_base;
684 u8 subsys_id = ctx->comp->subsys_id;
686 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]);
688 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0));
692 static const struct mdp_comp_ops wdma_ops = {
693 .get_comp_flag = get_comp_flag,
694 .init_comp = init_wdma,
695 .config_frame = config_wdma_frame,
696 .config_subfrm = config_wdma_subfrm,
697 .wait_comp_event = wait_wdma_event,
700 static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd)
702 phys_addr_t base = ctx->comp->reg_base;
703 u8 subsys_id = ctx->comp->subsys_id;
706 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0));
708 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0));
712 static int config_ccorr_subfrm(struct mdp_comp_ctx *ctx,
713 struct mdp_cmdq_cmd *cmd, u32 index)
715 phys_addr_t base = ctx->comp->reg_base;
716 u8 subsys_id = ctx->comp->subsys_id;
717 u32 csf_l = 0, csf_r = 0;
718 u32 csf_t = 0, csf_b = 0;
721 if (CFG_CHECK(MT8183, p_id)) {
722 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left);
723 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right);
724 csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top);
725 csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom);
728 hsize = csf_r - csf_l + 1;
729 vsize = csf_b - csf_t + 1;
730 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE,
731 (hsize << 16) + (vsize << 0), 0x1FFF1FFF);
735 static const struct mdp_comp_ops ccorr_ops = {
736 .get_comp_flag = get_comp_flag,
737 .init_comp = init_ccorr,
738 .config_subfrm = config_ccorr_subfrm,
741 static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
742 [MDP_COMP_TYPE_RDMA] = &rdma_ops,
743 [MDP_COMP_TYPE_RSZ] = &rsz_ops,
744 [MDP_COMP_TYPE_WROT] = &wrot_ops,
745 [MDP_COMP_TYPE_WDMA] = &wdma_ops,
746 [MDP_COMP_TYPE_CCORR] = &ccorr_ops,
749 static const struct of_device_id mdp_comp_dt_ids[] __maybe_unused = {
751 .compatible = "mediatek,mt8183-mdp3-rdma",
752 .data = (void *)MDP_COMP_TYPE_RDMA,
754 .compatible = "mediatek,mt8183-mdp3-ccorr",
755 .data = (void *)MDP_COMP_TYPE_CCORR,
757 .compatible = "mediatek,mt8183-mdp3-rsz",
758 .data = (void *)MDP_COMP_TYPE_RSZ,
760 .compatible = "mediatek,mt8183-mdp3-wrot",
761 .data = (void *)MDP_COMP_TYPE_WROT,
763 .compatible = "mediatek,mt8183-mdp3-wdma",
764 .data = (void *)MDP_COMP_TYPE_WDMA,
769 static inline bool is_dma_capable(const enum mdp_comp_type type)
771 return (type == MDP_COMP_TYPE_RDMA ||
772 type == MDP_COMP_TYPE_WROT ||
773 type == MDP_COMP_TYPE_WDMA);
776 static inline bool is_bypass_gce_event(const enum mdp_comp_type type)
779 * Subcomponent PATH is only used for the direction of data flow and
780 * dose not need to wait for GCE event.
782 return (type == MDP_COMP_TYPE_PATH);
785 static int mdp_comp_get_id(struct mdp_dev *mdp, enum mdp_comp_type type, u32 alias_id)
789 for (i = 0; i < mdp->mdp_data->comp_data_len; i++)
790 if (mdp->mdp_data->comp_data[i].match.type == type &&
791 mdp->mdp_data->comp_data[i].match.alias_id == alias_id)
796 int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
800 /* Only DMA capable components need the pm control */
801 if (comp->comp_dev && is_dma_capable(comp->type)) {
802 ret = pm_runtime_resume_and_get(comp->comp_dev);
805 "Failed to get power, err %d. type:%d id:%d\n",
806 ret, comp->type, comp->inner_id);
811 for (i = 0; i < comp->clk_num; i++) {
812 if (IS_ERR_OR_NULL(comp->clks[i]))
814 ret = clk_prepare_enable(comp->clks[i]);
817 "Failed to enable clk %d. type:%d id:%d\n",
818 i, comp->type, comp->inner_id);
827 if (IS_ERR_OR_NULL(comp->clks[i]))
829 clk_disable_unprepare(comp->clks[i]);
831 if (comp->comp_dev && is_dma_capable(comp->type))
832 pm_runtime_put_sync(comp->comp_dev);
837 void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp)
841 for (i = 0; i < comp->clk_num; i++) {
842 if (IS_ERR_OR_NULL(comp->clks[i]))
844 clk_disable_unprepare(comp->clks[i]);
847 if (comp->comp_dev && is_dma_capable(comp->type))
848 pm_runtime_put(comp->comp_dev);
851 int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num)
855 for (i = 0; i < num; i++) {
856 ret = mdp_comp_clock_on(dev, &comps[i]);
864 void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num)
868 for (i = 0; i < num; i++)
869 mdp_comp_clock_off(dev, &comps[i]);
872 static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev,
873 struct device_node *node, struct mdp_comp *comp)
875 struct platform_device *comp_pdev;
876 struct cmdq_client_reg cmdq_reg;
880 if (!dev || !node || !comp)
883 comp_pdev = of_find_device_by_node(node);
886 dev_err(dev, "get comp_pdev fail! comp public id=%d, inner id=%d, type=%d\n",
887 comp->public_id, comp->inner_id, comp->type);
891 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
892 ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index);
894 dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n");
895 put_device(&comp_pdev->dev);
899 comp->subsys_id = cmdq_reg.subsys;
900 dev_dbg(&comp_pdev->dev, "subsys id=%d\n", cmdq_reg.subsys);
901 put_device(&comp_pdev->dev);
906 static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
907 struct mdp_comp *comp)
913 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
914 if (of_address_to_resource(node, index, &res) < 0)
920 comp->regs = of_iomap(node, 0);
921 comp->reg_base = base;
924 static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
925 struct mdp_comp *comp, enum mtk_mdp_comp_id id)
927 struct device *dev = &mdp->pdev->dev;
928 struct platform_device *pdev_c;
933 if (id < 0 || id >= MDP_MAX_COMP_COUNT) {
934 dev_err(dev, "Invalid component id %d\n", id);
938 pdev_c = of_find_device_by_node(node);
940 dev_warn(dev, "can't find platform device of node:%s\n",
945 comp->comp_dev = &pdev_c->dev;
946 comp->public_id = id;
947 comp->type = mdp->mdp_data->comp_data[id].match.type;
948 comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id;
949 comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id;
950 comp->ops = mdp_comp_ops[comp->type];
951 __mdp_comp_init(mdp, node, comp);
953 comp->clk_num = mdp->mdp_data->comp_data[id].info.clk_num;
954 comp->clks = devm_kzalloc(dev, sizeof(struct clk *) * comp->clk_num,
959 clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst;
961 for (i = 0; i < comp->clk_num; i++) {
962 comp->clks[i] = of_clk_get(node, i + clk_ofst);
963 if (IS_ERR(comp->clks[i]))
967 mdp_get_subsys_id(mdp, dev, node, comp);
969 /* Set GCE SOF event */
970 if (is_bypass_gce_event(comp->type) ||
971 of_property_read_u32_index(node, "mediatek,gce-events",
972 MDP_GCE_EVENT_SOF, &event))
973 event = MDP_GCE_NO_EVENT;
975 comp->gce_event[MDP_GCE_EVENT_SOF] = event;
977 /* Set GCE EOF event */
978 if (is_dma_capable(comp->type)) {
979 if (of_property_read_u32_index(node, "mediatek,gce-events",
980 MDP_GCE_EVENT_EOF, &event)) {
981 dev_err(dev, "Component id %d has no EOF\n", id);
985 event = MDP_GCE_NO_EVENT;
988 comp->gce_event[MDP_GCE_EVENT_EOF] = event;
993 static void mdp_comp_deinit(struct mdp_comp *comp)
998 if (comp->comp_dev && comp->clks) {
999 devm_kfree(&comp->mdp_dev->pdev->dev, comp->clks);
1004 iounmap(comp->regs);
1007 static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
1008 struct device_node *node,
1009 enum mtk_mdp_comp_id id)
1011 struct device *dev = &mdp->pdev->dev;
1012 struct mdp_comp *comp;
1016 return ERR_PTR(-EEXIST);
1018 comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
1020 return ERR_PTR(-ENOMEM);
1022 ret = mdp_comp_init(mdp, node, comp, id);
1024 devm_kfree(dev, comp);
1025 return ERR_PTR(ret);
1027 mdp->comp[id] = comp;
1028 mdp->comp[id]->mdp_dev = mdp;
1030 dev_dbg(dev, "%s type:%d alias:%d public id:%d inner id:%d base:%#x regs:%p\n",
1031 dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id,
1032 (u32)comp->reg_base, comp->regs);
1036 static int mdp_comp_sub_create(struct mdp_dev *mdp)
1038 struct device *dev = &mdp->pdev->dev;
1039 struct device_node *node, *parent;
1042 parent = dev->of_node->parent;
1044 for_each_child_of_node(parent, node) {
1045 const struct of_device_id *of_id;
1046 enum mdp_comp_type type;
1048 struct mdp_comp *comp;
1050 of_id = of_match_node(mdp->mdp_data->mdp_sub_comp_dt_ids, node);
1053 if (!of_device_is_available(node)) {
1054 dev_dbg(dev, "Skipping disabled sub comp. %pOF\n",
1059 type = (enum mdp_comp_type)(uintptr_t)of_id->data;
1060 alias_id = mdp_comp_alias_id[type];
1061 id = mdp_comp_get_id(mdp, type, alias_id);
1064 "Fail to get sub comp. id: type %d alias %d\n",
1069 mdp_comp_alias_id[type]++;
1071 comp = mdp_comp_create(mdp, node, id);
1073 ret = PTR_ERR(comp);
1084 void mdp_comp_destroy(struct mdp_dev *mdp)
1088 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) {
1090 if (is_dma_capable(mdp->comp[i]->type))
1091 pm_runtime_disable(mdp->comp[i]->comp_dev);
1092 mdp_comp_deinit(mdp->comp[i]);
1093 devm_kfree(mdp->comp[i]->comp_dev, mdp->comp[i]);
1094 mdp->comp[i] = NULL;
1099 int mdp_comp_config(struct mdp_dev *mdp)
1101 struct device *dev = &mdp->pdev->dev;
1102 struct device_node *node, *parent;
1105 memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id));
1106 p_id = mdp->mdp_data->mdp_plat_id;
1108 parent = dev->of_node->parent;
1109 /* Iterate over sibling MDP function blocks */
1110 for_each_child_of_node(parent, node) {
1111 const struct of_device_id *of_id;
1112 enum mdp_comp_type type;
1114 struct mdp_comp *comp;
1116 of_id = of_match_node(mdp_comp_dt_ids, node);
1120 if (!of_device_is_available(node)) {
1121 dev_dbg(dev, "Skipping disabled component %pOF\n",
1126 type = (enum mdp_comp_type)(uintptr_t)of_id->data;
1127 alias_id = mdp_comp_alias_id[type];
1128 id = mdp_comp_get_id(mdp, type, alias_id);
1131 "Fail to get component id: type %d alias %d\n",
1135 mdp_comp_alias_id[type]++;
1137 comp = mdp_comp_create(mdp, node, id);
1139 ret = PTR_ERR(comp);
1141 goto err_init_comps;
1144 /* Only DMA capable components need the pm control */
1145 if (!is_dma_capable(comp->type))
1147 pm_runtime_enable(comp->comp_dev);
1150 ret = mdp_comp_sub_create(mdp);
1152 goto err_init_comps;
1157 mdp_comp_destroy(mdp);
1161 int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
1162 const struct img_compparam *param,
1163 const struct img_ipi_frameparam *frame)
1165 struct device *dev = &mdp->pdev->dev;
1166 enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
1171 dev_err(dev, "Invalid component param");
1175 if (CFG_CHECK(MT8183, p_id))
1176 arg = CFG_COMP(MT8183, param, type);
1179 public_id = mdp_cfg_get_id_public(mdp, arg);
1180 if (public_id < 0) {
1181 dev_err(dev, "Invalid component id %d", public_id);
1185 ctx->comp = mdp->comp[public_id];
1187 dev_err(dev, "Uninit component inner id %d", arg);
1192 if (CFG_CHECK(MT8183, p_id))
1193 arg = CFG_COMP(MT8183, param, input);
1196 ctx->input = &frame->inputs[arg];
1197 if (CFG_CHECK(MT8183, p_id))
1198 idx = CFG_COMP(MT8183, param, num_outputs);
1201 for (i = 0; i < idx; i++) {
1202 if (CFG_CHECK(MT8183, p_id))
1203 arg = CFG_COMP(MT8183, param, outputs[i]);
1206 ctx->outputs[i] = &frame->outputs[arg];