2 * The Marvell camera core. This device appears in a number of settings,
3 * so it needs platform-specific support outside of the core.
5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
7 #include <linux/kernel.h>
8 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/spinlock.h>
14 #include <linux/slab.h>
15 #include <linux/device.h>
16 #include <linux/wait.h>
17 #include <linux/list.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
20 #include <linux/vmalloc.h>
22 #include <linux/clk.h>
23 #include <linux/videodev2.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/i2c/ov7670.h>
29 #include <media/videobuf2-vmalloc.h>
30 #include <media/videobuf2-dma-contig.h>
31 #include <media/videobuf2-dma-sg.h>
33 #include "mcam-core.h"
35 #ifdef MCAM_MODE_VMALLOC
37 * Internal DMA buffer management. Since the controller cannot do S/G I/O,
38 * we must have physically contiguous buffers to bring frames into.
39 * These parameters control how many buffers we use, whether we
40 * allocate them at load time (better chance of success, but nails down
41 * memory) or when somebody tries to use the camera (riskier), and,
42 * for load-time allocation, how big they should be.
44 * The controller can cycle through three buffers. We could use
45 * more by flipping pointers around, but it probably makes little
49 static bool alloc_bufs_at_read;
50 module_param(alloc_bufs_at_read, bool, 0444);
51 MODULE_PARM_DESC(alloc_bufs_at_read,
52 "Non-zero value causes DMA buffers to be allocated when the "
53 "video capture device is read, rather than at module load "
54 "time. This saves memory, but decreases the chances of "
55 "successfully getting those buffers. This parameter is "
56 "only used in the vmalloc buffer mode");
58 static int n_dma_bufs = 3;
59 module_param(n_dma_bufs, uint, 0644);
60 MODULE_PARM_DESC(n_dma_bufs,
61 "The number of DMA buffers to allocate. Can be either two "
62 "(saves memory, makes timing tighter) or three.");
64 static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
65 module_param(dma_buf_size, uint, 0444);
66 MODULE_PARM_DESC(dma_buf_size,
67 "The size of the allocated DMA buffers. If actual operating "
68 "parameters require larger buffers, an attempt to reallocate "
70 #else /* MCAM_MODE_VMALLOC */
71 static const bool alloc_bufs_at_read;
72 static const int n_dma_bufs = 3; /* Used by S/G_PARM */
73 #endif /* MCAM_MODE_VMALLOC */
76 module_param(flip, bool, 0444);
77 MODULE_PARM_DESC(flip,
78 "If set, the sensor will be instructed to flip the image "
81 static int buffer_mode = -1;
82 module_param(buffer_mode, int, 0444);
83 MODULE_PARM_DESC(buffer_mode,
84 "Set the buffer mode to be used; default is to go with what "
85 "the platform driver asks for. Set to 0 for vmalloc, 1 for "
89 * Status flags. Always manipulated with bit operations.
91 #define CF_BUF0_VALID 0 /* Buffers valid - first three */
92 #define CF_BUF1_VALID 1
93 #define CF_BUF2_VALID 2
94 #define CF_DMA_ACTIVE 3 /* A frame is incoming */
95 #define CF_CONFIG_NEEDED 4 /* Must configure hardware */
96 #define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
97 #define CF_SG_RESTART 6 /* SG restart needed */
98 #define CF_FRAME_SOF0 7 /* Frame 0 started */
99 #define CF_FRAME_SOF1 8
100 #define CF_FRAME_SOF2 9
102 #define sensor_call(cam, o, f, args...) \
103 v4l2_subdev_call(cam->sensor, o, f, ##args)
105 static struct mcam_format_struct {
108 int bpp; /* Bytes per pixel */
113 .desc = "YUYV 4:2:2",
114 .pixelformat = V4L2_PIX_FMT_YUYV,
115 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
120 .desc = "YVYU 4:2:2",
121 .pixelformat = V4L2_PIX_FMT_YVYU,
122 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
127 .desc = "YUV 4:2:0 PLANAR",
128 .pixelformat = V4L2_PIX_FMT_YUV420,
129 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
134 .desc = "YVU 4:2:0 PLANAR",
135 .pixelformat = V4L2_PIX_FMT_YVU420,
136 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
142 .pixelformat = V4L2_PIX_FMT_XRGB444,
143 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
149 .pixelformat = V4L2_PIX_FMT_RGB565,
150 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
155 .desc = "Raw RGB Bayer",
156 .pixelformat = V4L2_PIX_FMT_SBGGR8,
157 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
162 #define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
164 static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
168 for (i = 0; i < N_MCAM_FMTS; i++)
169 if (mcam_formats[i].pixelformat == pixelformat)
170 return mcam_formats + i;
171 /* Not found? Then return the first format. */
176 * The default format we use until somebody says otherwise.
178 static const struct v4l2_pix_format mcam_def_pix_format = {
180 .height = VGA_HEIGHT,
181 .pixelformat = V4L2_PIX_FMT_YUYV,
182 .field = V4L2_FIELD_NONE,
183 .bytesperline = VGA_WIDTH*2,
184 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
185 .colorspace = V4L2_COLORSPACE_SRGB,
188 static const u32 mcam_def_mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
192 * The two-word DMA descriptor format used by the Armada 610 and like. There
193 * Is a three-word format as well (set C1_DESC_3WORD) where the third
194 * word is a pointer to the next descriptor, but we don't use it. Two-word
195 * descriptors have to be contiguous in memory.
197 struct mcam_dma_desc {
203 * Our buffer type for working with videobuf2. Note that the vb2
204 * developers have decreed that struct vb2_v4l2_buffer must be at the
205 * beginning of this structure.
207 struct mcam_vb_buffer {
208 struct vb2_v4l2_buffer vb_buf;
209 struct list_head queue;
210 struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
211 dma_addr_t dma_desc_pa; /* Descriptor physical address */
214 static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_v4l2_buffer *vb)
216 return container_of(vb, struct mcam_vb_buffer, vb_buf);
220 * Hand a completed buffer back to user space.
222 static void mcam_buffer_done(struct mcam_camera *cam, int frame,
223 struct vb2_v4l2_buffer *vbuf)
225 vbuf->vb2_buf.planes[0].bytesused = cam->pix_format.sizeimage;
226 vbuf->sequence = cam->buf_seq[frame];
227 vbuf->field = V4L2_FIELD_NONE;
228 vbuf->vb2_buf.timestamp = ktime_get_ns();
229 vb2_set_plane_payload(&vbuf->vb2_buf, 0, cam->pix_format.sizeimage);
230 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
236 * Debugging and related.
238 #define cam_err(cam, fmt, arg...) \
239 dev_err((cam)->dev, fmt, ##arg);
240 #define cam_warn(cam, fmt, arg...) \
241 dev_warn((cam)->dev, fmt, ##arg);
242 #define cam_dbg(cam, fmt, arg...) \
243 dev_dbg((cam)->dev, fmt, ##arg);
247 * Flag manipulation helpers
249 static void mcam_reset_buffers(struct mcam_camera *cam)
254 for (i = 0; i < cam->nbufs; i++) {
255 clear_bit(i, &cam->flags);
256 clear_bit(CF_FRAME_SOF0 + i, &cam->flags);
260 static inline int mcam_needs_config(struct mcam_camera *cam)
262 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
265 static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
268 set_bit(CF_CONFIG_NEEDED, &cam->flags);
270 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
273 /* ------------------------------------------------------------------- */
275 * Make the controller start grabbing images. Everything must
276 * be set up before doing this.
278 static void mcam_ctlr_start(struct mcam_camera *cam)
280 /* set_bit performs a read, so no other barrier should be
282 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
285 static void mcam_ctlr_stop(struct mcam_camera *cam)
287 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
290 static void mcam_enable_mipi(struct mcam_camera *mcam)
292 /* Using MIPI mode and enable MIPI */
293 cam_dbg(mcam, "camera: DPHY3=0x%x, DPHY5=0x%x, DPHY6=0x%x\n",
294 mcam->dphy[0], mcam->dphy[1], mcam->dphy[2]);
295 mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]);
296 mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]);
297 mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]);
299 if (!mcam->mipi_enabled) {
300 if (mcam->lane > 4 || mcam->lane <= 0) {
301 cam_warn(mcam, "lane number error\n");
302 mcam->lane = 1; /* set the default value */
305 * 0x41 actives 1 lane
306 * 0x43 actives 2 lanes
307 * 0x45 actives 3 lanes (never happen)
308 * 0x47 actives 4 lanes
310 mcam_reg_write(mcam, REG_CSI2_CTRL0,
311 CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane));
312 mcam_reg_write(mcam, REG_CLKCTRL,
313 (mcam->mclk_src << 29) | mcam->mclk_div);
315 mcam->mipi_enabled = true;
319 static void mcam_disable_mipi(struct mcam_camera *mcam)
321 /* Using Parallel mode or disable MIPI */
322 mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0);
323 mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0);
324 mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0);
325 mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0);
326 mcam->mipi_enabled = false;
329 static bool mcam_fmt_is_planar(__u32 pfmt)
331 struct mcam_format_struct *f;
333 f = mcam_find_format(pfmt);
337 static void mcam_write_yuv_bases(struct mcam_camera *cam,
338 unsigned frame, dma_addr_t base)
340 struct v4l2_pix_format *fmt = &cam->pix_format;
341 u32 pixel_count = fmt->width * fmt->height;
342 dma_addr_t y, u = 0, v = 0;
346 switch (fmt->pixelformat) {
347 case V4L2_PIX_FMT_YUV420:
349 v = u + pixel_count / 4;
351 case V4L2_PIX_FMT_YVU420:
353 u = v + pixel_count / 4;
359 mcam_reg_write(cam, REG_Y0BAR + frame * 4, y);
360 if (mcam_fmt_is_planar(fmt->pixelformat)) {
361 mcam_reg_write(cam, REG_U0BAR + frame * 4, u);
362 mcam_reg_write(cam, REG_V0BAR + frame * 4, v);
366 /* ------------------------------------------------------------------- */
368 #ifdef MCAM_MODE_VMALLOC
370 * Code specific to the vmalloc buffer mode.
374 * Allocate in-kernel DMA buffers for vmalloc mode.
376 static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
380 mcam_set_config_needed(cam, 1);
382 cam->dma_buf_size = dma_buf_size;
384 cam->dma_buf_size = cam->pix_format.sizeimage;
389 for (i = 0; i < n_dma_bufs; i++) {
390 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
391 cam->dma_buf_size, cam->dma_handles + i,
393 if (cam->dma_bufs[i] == NULL) {
394 cam_warn(cam, "Failed to allocate DMA buffer\n");
400 switch (cam->nbufs) {
402 dma_free_coherent(cam->dev, cam->dma_buf_size,
403 cam->dma_bufs[0], cam->dma_handles[0]);
406 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
411 cam_warn(cam, "Will limp along with only 2 buffers\n");
417 static void mcam_free_dma_bufs(struct mcam_camera *cam)
421 for (i = 0; i < cam->nbufs; i++) {
422 dma_free_coherent(cam->dev, cam->dma_buf_size,
423 cam->dma_bufs[i], cam->dma_handles[i]);
424 cam->dma_bufs[i] = NULL;
431 * Set up DMA buffers when operating in vmalloc mode
433 static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
436 * Store the first two YUV buffers. Then either
437 * set the third if it exists, or tell the controller
440 mcam_write_yuv_bases(cam, 0, cam->dma_handles[0]);
441 mcam_write_yuv_bases(cam, 1, cam->dma_handles[1]);
442 if (cam->nbufs > 2) {
443 mcam_write_yuv_bases(cam, 2, cam->dma_handles[2]);
444 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
446 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
447 if (cam->chip_id == MCAM_CAFE)
448 mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
452 * Copy data out to user space in the vmalloc case
454 static void mcam_frame_tasklet(unsigned long data)
456 struct mcam_camera *cam = (struct mcam_camera *) data;
459 struct mcam_vb_buffer *buf;
461 spin_lock_irqsave(&cam->dev_lock, flags);
462 for (i = 0; i < cam->nbufs; i++) {
463 int bufno = cam->next_buf;
465 if (cam->state != S_STREAMING || bufno < 0)
466 break; /* I/O got stopped */
467 if (++(cam->next_buf) >= cam->nbufs)
469 if (!test_bit(bufno, &cam->flags))
471 if (list_empty(&cam->buffers)) {
472 cam->frame_state.singles++;
473 break; /* Leave it valid, hope for better later */
475 cam->frame_state.delivered++;
476 clear_bit(bufno, &cam->flags);
477 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
479 list_del_init(&buf->queue);
481 * Drop the lock during the big copy. This *should* be safe...
483 spin_unlock_irqrestore(&cam->dev_lock, flags);
484 memcpy(vb2_plane_vaddr(&buf->vb_buf.vb2_buf, 0),
485 cam->dma_bufs[bufno],
486 cam->pix_format.sizeimage);
487 mcam_buffer_done(cam, bufno, &buf->vb_buf);
488 spin_lock_irqsave(&cam->dev_lock, flags);
490 spin_unlock_irqrestore(&cam->dev_lock, flags);
495 * Make sure our allocated buffers are up to the task.
497 static int mcam_check_dma_buffers(struct mcam_camera *cam)
499 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
500 mcam_free_dma_bufs(cam);
502 return mcam_alloc_dma_bufs(cam, 0);
506 static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
508 tasklet_schedule(&cam->s_tasklet);
511 #else /* MCAM_MODE_VMALLOC */
513 static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
518 static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
523 static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
530 #endif /* MCAM_MODE_VMALLOC */
533 #ifdef MCAM_MODE_DMA_CONTIG
534 /* ---------------------------------------------------------------------- */
536 * DMA-contiguous code.
540 * Set up a contiguous buffer for the given frame. Here also is where
541 * the underrun strategy is set: if there is no buffer available, reuse
542 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
543 * keep the interrupt handler from giving that buffer back to user
544 * space. In this way, we always have a buffer to DMA to and don't
545 * have to try to play games stopping and restarting the controller.
547 static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
549 struct mcam_vb_buffer *buf;
550 dma_addr_t dma_handle;
551 struct vb2_v4l2_buffer *vb;
554 * If there are no available buffers, go into single mode
556 if (list_empty(&cam->buffers)) {
557 buf = cam->vb_bufs[frame ^ 0x1];
558 set_bit(CF_SINGLE_BUFFER, &cam->flags);
559 cam->frame_state.singles++;
562 * OK, we have a buffer we can use.
564 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
566 list_del_init(&buf->queue);
567 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
570 cam->vb_bufs[frame] = buf;
573 dma_handle = vb2_dma_contig_plane_dma_addr(&vb->vb2_buf, 0);
574 mcam_write_yuv_bases(cam, frame, dma_handle);
578 * Initial B_DMA_contig setup.
580 static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
582 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
584 mcam_set_contig_buffer(cam, 0);
585 mcam_set_contig_buffer(cam, 1);
589 * Frame completion handling.
591 static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
593 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
595 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
596 cam->frame_state.delivered++;
597 cam->vb_bufs[frame] = NULL;
598 mcam_buffer_done(cam, frame, &buf->vb_buf);
600 mcam_set_contig_buffer(cam, frame);
603 #endif /* MCAM_MODE_DMA_CONTIG */
605 #ifdef MCAM_MODE_DMA_SG
606 /* ---------------------------------------------------------------------- */
608 * Scatter/gather-specific code.
612 * Set up the next buffer for S/G I/O; caller should be sure that
613 * the controller is stopped and a buffer is available.
615 static void mcam_sg_next_buffer(struct mcam_camera *cam)
617 struct mcam_vb_buffer *buf;
618 struct sg_table *sg_table;
620 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
621 list_del_init(&buf->queue);
622 sg_table = vb2_dma_sg_plane_desc(&buf->vb_buf.vb2_buf, 0);
624 * Very Bad Not Good Things happen if you don't clear
625 * C1_DESC_ENA before making any descriptor changes.
627 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
628 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
629 mcam_reg_write(cam, REG_DESC_LEN_Y,
630 sg_table->nents * sizeof(struct mcam_dma_desc));
631 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
632 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
633 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
634 cam->vb_bufs[0] = buf;
638 * Initial B_DMA_sg setup
640 static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
643 * The list-empty condition can hit us at resume time
644 * if the buffer list was empty when the system was suspended.
646 if (list_empty(&cam->buffers)) {
647 set_bit(CF_SG_RESTART, &cam->flags);
651 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
652 mcam_sg_next_buffer(cam);
658 * Frame completion with S/G is trickier. We can't muck with
659 * a descriptor chain on the fly, since the controller buffers it
660 * internally. So we have to actually stop and restart; Marvell
661 * says this is the way to do it.
663 * Of course, stopping is easier said than done; experience shows
664 * that the controller can start a frame *after* C0_ENABLE has been
665 * cleared. So when running in S/G mode, the controller is "stopped"
666 * on receipt of the start-of-frame interrupt. That means we can
667 * safely change the DMA descriptor array here and restart things
668 * (assuming there's another buffer waiting to go).
670 static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
672 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
675 * If we're no longer supposed to be streaming, don't do anything.
677 if (cam->state != S_STREAMING)
680 * If we have another buffer available, put it in and
681 * restart the engine.
683 if (!list_empty(&cam->buffers)) {
684 mcam_sg_next_buffer(cam);
685 mcam_ctlr_start(cam);
687 * Otherwise set CF_SG_RESTART and the controller will
688 * be restarted once another buffer shows up.
691 set_bit(CF_SG_RESTART, &cam->flags);
692 cam->frame_state.singles++;
693 cam->vb_bufs[0] = NULL;
696 * Now we can give the completed frame back to user space.
698 cam->frame_state.delivered++;
699 mcam_buffer_done(cam, frame, &buf->vb_buf);
704 * Scatter/gather mode requires stopping the controller between
705 * frames so we can put in a new DMA descriptor array. If no new
706 * buffer exists at frame completion, the controller is left stopped;
707 * this function is charged with gettig things going again.
709 static void mcam_sg_restart(struct mcam_camera *cam)
711 mcam_ctlr_dma_sg(cam);
712 mcam_ctlr_start(cam);
713 clear_bit(CF_SG_RESTART, &cam->flags);
716 #else /* MCAM_MODE_DMA_SG */
718 static inline void mcam_sg_restart(struct mcam_camera *cam)
723 #endif /* MCAM_MODE_DMA_SG */
725 /* ---------------------------------------------------------------------- */
727 * Buffer-mode-independent controller code.
733 static void mcam_ctlr_image(struct mcam_camera *cam)
735 struct v4l2_pix_format *fmt = &cam->pix_format;
736 u32 widthy = 0, widthuv = 0, imgsz_h, imgsz_w;
738 cam_dbg(cam, "camera: bytesperline = %d; height = %d\n",
739 fmt->bytesperline, fmt->sizeimage / fmt->bytesperline);
740 imgsz_h = (fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK;
741 imgsz_w = (fmt->width * 2) & IMGSZ_H_MASK;
743 switch (fmt->pixelformat) {
744 case V4L2_PIX_FMT_YUYV:
745 case V4L2_PIX_FMT_YVYU:
746 widthy = fmt->width * 2;
749 case V4L2_PIX_FMT_YUV420:
750 case V4L2_PIX_FMT_YVU420:
752 widthuv = fmt->width / 2;
755 widthy = fmt->bytesperline;
760 mcam_reg_write_mask(cam, REG_IMGPITCH, widthuv << 16 | widthy,
761 IMGP_YP_MASK | IMGP_UVP_MASK);
762 mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w);
763 mcam_reg_write(cam, REG_IMGOFFSET, 0x0);
766 * Tell the controller about the image format we are using.
768 switch (fmt->pixelformat) {
769 case V4L2_PIX_FMT_YUV420:
770 case V4L2_PIX_FMT_YVU420:
771 mcam_reg_write_mask(cam, REG_CTRL0,
772 C0_DF_YUV | C0_YUV_420PL | C0_YUVE_VYUY, C0_DF_MASK);
774 case V4L2_PIX_FMT_YUYV:
775 mcam_reg_write_mask(cam, REG_CTRL0,
776 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_NOSWAP, C0_DF_MASK);
778 case V4L2_PIX_FMT_YVYU:
779 mcam_reg_write_mask(cam, REG_CTRL0,
780 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_SWAP24, C0_DF_MASK);
782 case V4L2_PIX_FMT_XRGB444:
783 mcam_reg_write_mask(cam, REG_CTRL0,
784 C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XBGR, C0_DF_MASK);
786 case V4L2_PIX_FMT_RGB565:
787 mcam_reg_write_mask(cam, REG_CTRL0,
788 C0_DF_RGB | C0_RGBF_565 | C0_RGB5_BGGR, C0_DF_MASK);
790 case V4L2_PIX_FMT_SBGGR8:
791 mcam_reg_write_mask(cam, REG_CTRL0,
792 C0_DF_RGB | C0_RGB5_GRBG, C0_DF_MASK);
795 cam_err(cam, "camera: unknown format: %#x\n", fmt->pixelformat);
800 * Make sure it knows we want to use hsync/vsync.
802 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK);
804 * This field controls the generation of EOF(DVP only)
806 if (cam->bus_type != V4L2_MBUS_CSI2)
807 mcam_reg_set_bit(cam, REG_CTRL0,
808 C0_EOF_VSYNC | C0_VEDGE_CTRL);
813 * Configure the controller for operation; caller holds the
816 static int mcam_ctlr_configure(struct mcam_camera *cam)
820 spin_lock_irqsave(&cam->dev_lock, flags);
821 clear_bit(CF_SG_RESTART, &cam->flags);
823 mcam_ctlr_image(cam);
824 mcam_set_config_needed(cam, 0);
825 spin_unlock_irqrestore(&cam->dev_lock, flags);
829 static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
832 * Clear any pending interrupts, since we do not
833 * expect to have I/O active prior to enabling.
835 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
836 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
839 static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
841 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
846 static void mcam_ctlr_init(struct mcam_camera *cam)
850 spin_lock_irqsave(&cam->dev_lock, flags);
852 * Make sure it's not powered down.
854 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
856 * Turn off the enable bit. It sure should be off anyway,
857 * but it's good to be sure.
859 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
861 * Clock the sensor appropriately. Controller clock should
862 * be 48MHz, sensor "typical" value is half that.
864 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
865 spin_unlock_irqrestore(&cam->dev_lock, flags);
870 * Stop the controller, and don't return until we're really sure that no
871 * further DMA is going on.
873 static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
878 * Theory: stop the camera controller (whether it is operating
879 * or not). Delay briefly just in case we race with the SOF
880 * interrupt, then wait until no DMA is active.
882 spin_lock_irqsave(&cam->dev_lock, flags);
883 clear_bit(CF_SG_RESTART, &cam->flags);
886 spin_unlock_irqrestore(&cam->dev_lock, flags);
888 * This is a brutally long sleep, but experience shows that
889 * it can take the controller a while to get the message that
890 * it needs to stop grabbing frames. In particular, we can
891 * sometimes (on mmp) get a frame at the end WITHOUT the
892 * start-of-frame indication.
895 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
896 cam_err(cam, "Timeout waiting for DMA to end\n");
897 /* This would be bad news - what now? */
898 spin_lock_irqsave(&cam->dev_lock, flags);
899 mcam_ctlr_irq_disable(cam);
900 spin_unlock_irqrestore(&cam->dev_lock, flags);
906 static int mcam_ctlr_power_up(struct mcam_camera *cam)
911 spin_lock_irqsave(&cam->dev_lock, flags);
912 ret = cam->plat_power_up(cam);
914 spin_unlock_irqrestore(&cam->dev_lock, flags);
917 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
918 spin_unlock_irqrestore(&cam->dev_lock, flags);
919 msleep(5); /* Just to be sure */
923 static void mcam_ctlr_power_down(struct mcam_camera *cam)
927 spin_lock_irqsave(&cam->dev_lock, flags);
929 * School of hard knocks department: be sure we do any register
930 * twiddling on the controller *before* calling the platform
931 * power down routine.
933 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
934 cam->plat_power_down(cam);
935 spin_unlock_irqrestore(&cam->dev_lock, flags);
938 /* -------------------------------------------------------------------- */
940 * Communications with the sensor.
943 static int __mcam_cam_reset(struct mcam_camera *cam)
945 return sensor_call(cam, core, reset, 0);
949 * We have found the sensor on the i2c. Let's try to have a
952 static int mcam_cam_init(struct mcam_camera *cam)
956 if (cam->state != S_NOTREADY)
957 cam_warn(cam, "Cam init with device in funky state %d",
959 ret = __mcam_cam_reset(cam);
960 /* Get/set parameters? */
962 mcam_ctlr_power_down(cam);
967 * Configure the sensor to match the parameters we have. Caller should
970 static int mcam_cam_set_flip(struct mcam_camera *cam)
972 struct v4l2_control ctrl;
974 memset(&ctrl, 0, sizeof(ctrl));
975 ctrl.id = V4L2_CID_VFLIP;
977 return v4l2_s_ctrl(NULL, cam->sensor->ctrl_handler, &ctrl);
981 static int mcam_cam_configure(struct mcam_camera *cam)
983 struct v4l2_subdev_format format = {
984 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
988 v4l2_fill_mbus_format(&format.format, &cam->pix_format, cam->mbus_code);
989 ret = sensor_call(cam, core, init, 0);
991 ret = sensor_call(cam, pad, set_fmt, NULL, &format);
993 * OV7670 does weird things if flip is set *before* format...
995 ret += mcam_cam_set_flip(cam);
1000 * Get everything ready, and start grabbing frames.
1002 static int mcam_read_setup(struct mcam_camera *cam)
1005 unsigned long flags;
1008 * Configuration. If we still don't have DMA buffers,
1009 * make one last, desperate attempt.
1011 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
1012 mcam_alloc_dma_bufs(cam, 0))
1015 if (mcam_needs_config(cam)) {
1016 mcam_cam_configure(cam);
1017 ret = mcam_ctlr_configure(cam);
1025 spin_lock_irqsave(&cam->dev_lock, flags);
1026 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1027 mcam_reset_buffers(cam);
1029 * Update CSI2_DPHY value
1032 cam->calc_dphy(cam);
1033 cam_dbg(cam, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n",
1034 cam->dphy[0], cam->dphy[1], cam->dphy[2]);
1035 if (cam->bus_type == V4L2_MBUS_CSI2)
1036 mcam_enable_mipi(cam);
1038 mcam_disable_mipi(cam);
1039 mcam_ctlr_irq_enable(cam);
1040 cam->state = S_STREAMING;
1041 if (!test_bit(CF_SG_RESTART, &cam->flags))
1042 mcam_ctlr_start(cam);
1043 spin_unlock_irqrestore(&cam->dev_lock, flags);
1047 /* ----------------------------------------------------------------------- */
1049 * Videobuf2 interface code.
1052 static int mcam_vb_queue_setup(struct vb2_queue *vq,
1053 unsigned int *nbufs,
1054 unsigned int *num_planes, unsigned int sizes[],
1055 struct device *alloc_devs[])
1057 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1058 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
1059 unsigned size = cam->pix_format.sizeimage;
1061 if (*nbufs < minbufs)
1065 return sizes[0] < size ? -EINVAL : 0;
1067 *num_planes = 1; /* Someday we have to support planar formats... */
1072 static void mcam_vb_buf_queue(struct vb2_buffer *vb)
1074 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1075 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1076 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1077 unsigned long flags;
1080 spin_lock_irqsave(&cam->dev_lock, flags);
1081 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
1082 list_add(&mvb->queue, &cam->buffers);
1083 if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
1084 mcam_sg_restart(cam);
1085 spin_unlock_irqrestore(&cam->dev_lock, flags);
1087 mcam_read_setup(cam);
1090 static void mcam_vb_requeue_bufs(struct vb2_queue *vq,
1091 enum vb2_buffer_state state)
1093 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1094 struct mcam_vb_buffer *buf, *node;
1095 unsigned long flags;
1098 spin_lock_irqsave(&cam->dev_lock, flags);
1099 list_for_each_entry_safe(buf, node, &cam->buffers, queue) {
1100 vb2_buffer_done(&buf->vb_buf.vb2_buf, state);
1101 list_del(&buf->queue);
1103 for (i = 0; i < MAX_DMA_BUFS; i++) {
1104 buf = cam->vb_bufs[i];
1107 vb2_buffer_done(&buf->vb_buf.vb2_buf, state);
1108 cam->vb_bufs[i] = NULL;
1111 spin_unlock_irqrestore(&cam->dev_lock, flags);
1115 * These need to be called with the mutex held from vb2
1117 static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
1119 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1123 if (cam->state != S_IDLE) {
1124 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1127 cam->frame_state.frames = 0;
1128 cam->frame_state.singles = 0;
1129 cam->frame_state.delivered = 0;
1132 * Videobuf2 sneakily hoards all the buffers and won't
1133 * give them to us until *after* streaming starts. But
1134 * we can't actually start streaming until we have a
1135 * destination. So go into a wait state and hope they
1136 * give us buffers soon.
1138 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
1139 cam->state = S_BUFWAIT;
1144 * Ensure clear the left over frame flags
1145 * before every really start streaming
1147 for (frame = 0; frame < cam->nbufs; frame++)
1148 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1150 ret = mcam_read_setup(cam);
1152 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1156 static void mcam_vb_stop_streaming(struct vb2_queue *vq)
1158 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1160 cam_dbg(cam, "stop_streaming: %d frames, %d singles, %d delivered\n",
1161 cam->frame_state.frames, cam->frame_state.singles,
1162 cam->frame_state.delivered);
1163 if (cam->state == S_BUFWAIT) {
1164 /* They never gave us buffers */
1165 cam->state = S_IDLE;
1168 if (cam->state != S_STREAMING)
1170 mcam_ctlr_stop_dma(cam);
1172 * Reset the CCIC PHY after stopping streaming,
1173 * otherwise, the CCIC may be unstable.
1175 if (cam->ctlr_reset)
1176 cam->ctlr_reset(cam);
1178 * VB2 reclaims the buffers, so we need to forget
1181 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_ERROR);
1185 static const struct vb2_ops mcam_vb2_ops = {
1186 .queue_setup = mcam_vb_queue_setup,
1187 .buf_queue = mcam_vb_buf_queue,
1188 .start_streaming = mcam_vb_start_streaming,
1189 .stop_streaming = mcam_vb_stop_streaming,
1190 .wait_prepare = vb2_ops_wait_prepare,
1191 .wait_finish = vb2_ops_wait_finish,
1195 #ifdef MCAM_MODE_DMA_SG
1197 * Scatter/gather mode uses all of the above functions plus a
1198 * few extras to deal with DMA mapping.
1200 static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1202 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1203 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1204 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1205 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1207 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1208 ndesc * sizeof(struct mcam_dma_desc),
1209 &mvb->dma_desc_pa, GFP_KERNEL);
1210 if (mvb->dma_desc == NULL) {
1211 cam_err(cam, "Unable to get DMA descriptor array\n");
1217 static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1219 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1220 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1221 struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0);
1222 struct mcam_dma_desc *desc = mvb->dma_desc;
1223 struct scatterlist *sg;
1226 for_each_sg(sg_table->sgl, sg, sg_table->nents, i) {
1227 desc->dma_addr = sg_dma_address(sg);
1228 desc->segment_len = sg_dma_len(sg);
1234 static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1236 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1237 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1238 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1239 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1241 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1242 mvb->dma_desc, mvb->dma_desc_pa);
1246 static const struct vb2_ops mcam_vb2_sg_ops = {
1247 .queue_setup = mcam_vb_queue_setup,
1248 .buf_init = mcam_vb_sg_buf_init,
1249 .buf_prepare = mcam_vb_sg_buf_prepare,
1250 .buf_queue = mcam_vb_buf_queue,
1251 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1252 .start_streaming = mcam_vb_start_streaming,
1253 .stop_streaming = mcam_vb_stop_streaming,
1254 .wait_prepare = vb2_ops_wait_prepare,
1255 .wait_finish = vb2_ops_wait_finish,
1258 #endif /* MCAM_MODE_DMA_SG */
1260 static int mcam_setup_vb2(struct mcam_camera *cam)
1262 struct vb2_queue *vq = &cam->vb_queue;
1264 memset(vq, 0, sizeof(*vq));
1265 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1267 vq->lock = &cam->s_mutex;
1268 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1269 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1270 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1272 INIT_LIST_HEAD(&cam->buffers);
1273 switch (cam->buffer_mode) {
1275 #ifdef MCAM_MODE_DMA_CONTIG
1276 vq->ops = &mcam_vb2_ops;
1277 vq->mem_ops = &vb2_dma_contig_memops;
1278 cam->dma_setup = mcam_ctlr_dma_contig;
1279 cam->frame_complete = mcam_dma_contig_done;
1283 #ifdef MCAM_MODE_DMA_SG
1284 vq->ops = &mcam_vb2_sg_ops;
1285 vq->mem_ops = &vb2_dma_sg_memops;
1286 cam->dma_setup = mcam_ctlr_dma_sg;
1287 cam->frame_complete = mcam_dma_sg_done;
1291 #ifdef MCAM_MODE_VMALLOC
1292 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1293 (unsigned long) cam);
1294 vq->ops = &mcam_vb2_ops;
1295 vq->mem_ops = &vb2_vmalloc_memops;
1296 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1297 cam->frame_complete = mcam_vmalloc_done;
1301 return vb2_queue_init(vq);
1305 /* ---------------------------------------------------------------------- */
1307 * The long list of V4L2 ioctl() operations.
1310 static int mcam_vidioc_querycap(struct file *file, void *priv,
1311 struct v4l2_capability *cap)
1313 struct mcam_camera *cam = video_drvdata(file);
1315 strcpy(cap->driver, "marvell_ccic");
1316 strcpy(cap->card, "marvell_ccic");
1317 strlcpy(cap->bus_info, cam->bus_info, sizeof(cap->bus_info));
1318 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
1319 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1320 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1325 static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1326 void *priv, struct v4l2_fmtdesc *fmt)
1328 if (fmt->index >= N_MCAM_FMTS)
1330 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1331 sizeof(fmt->description));
1332 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1336 static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1337 struct v4l2_format *fmt)
1339 struct mcam_camera *cam = video_drvdata(filp);
1340 struct mcam_format_struct *f;
1341 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1342 struct v4l2_subdev_pad_config pad_cfg;
1343 struct v4l2_subdev_format format = {
1344 .which = V4L2_SUBDEV_FORMAT_TRY,
1348 f = mcam_find_format(pix->pixelformat);
1349 pix->pixelformat = f->pixelformat;
1350 v4l2_fill_mbus_format(&format.format, pix, f->mbus_code);
1351 ret = sensor_call(cam, pad, set_fmt, &pad_cfg, &format);
1352 v4l2_fill_pix_format(pix, &format.format);
1353 pix->bytesperline = pix->width * f->bpp;
1354 switch (f->pixelformat) {
1355 case V4L2_PIX_FMT_YUV420:
1356 case V4L2_PIX_FMT_YVU420:
1357 pix->sizeimage = pix->height * pix->bytesperline * 3 / 2;
1360 pix->sizeimage = pix->height * pix->bytesperline;
1363 pix->colorspace = V4L2_COLORSPACE_SRGB;
1367 static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1368 struct v4l2_format *fmt)
1370 struct mcam_camera *cam = video_drvdata(filp);
1371 struct mcam_format_struct *f;
1375 * Can't do anything if the device is not idle
1376 * Also can't if there are streaming buffers in place.
1378 if (cam->state != S_IDLE || vb2_is_busy(&cam->vb_queue))
1381 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1384 * See if the formatting works in principle.
1386 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1390 * Now we start to change things for real, so let's do it
1393 cam->pix_format = fmt->fmt.pix;
1394 cam->mbus_code = f->mbus_code;
1397 * Make sure we have appropriate DMA buffers.
1399 if (cam->buffer_mode == B_vmalloc) {
1400 ret = mcam_check_dma_buffers(cam);
1404 mcam_set_config_needed(cam, 1);
1410 * Return our stored notion of how the camera is/should be configured.
1411 * The V4l2 spec wants us to be smarter, and actually get this from
1412 * the camera (and not mess with it at open time). Someday.
1414 static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1415 struct v4l2_format *f)
1417 struct mcam_camera *cam = video_drvdata(filp);
1419 f->fmt.pix = cam->pix_format;
1424 * We only have one input - the sensor - so minimize the nonsense here.
1426 static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1427 struct v4l2_input *input)
1429 if (input->index != 0)
1432 input->type = V4L2_INPUT_TYPE_CAMERA;
1433 strcpy(input->name, "Camera");
1437 static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1443 static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1451 * G/S_PARM. Most of this is done by the sensor, but we are
1452 * the level which controls the number of read buffers.
1454 static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1455 struct v4l2_streamparm *parms)
1457 struct mcam_camera *cam = video_drvdata(filp);
1460 ret = sensor_call(cam, video, g_parm, parms);
1461 parms->parm.capture.readbuffers = n_dma_bufs;
1465 static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1466 struct v4l2_streamparm *parms)
1468 struct mcam_camera *cam = video_drvdata(filp);
1471 ret = sensor_call(cam, video, s_parm, parms);
1472 parms->parm.capture.readbuffers = n_dma_bufs;
1476 static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1477 struct v4l2_frmsizeenum *sizes)
1479 struct mcam_camera *cam = video_drvdata(filp);
1480 struct mcam_format_struct *f;
1481 struct v4l2_subdev_frame_size_enum fse = {
1482 .index = sizes->index,
1483 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1487 f = mcam_find_format(sizes->pixel_format);
1488 if (f->pixelformat != sizes->pixel_format)
1490 fse.code = f->mbus_code;
1491 ret = sensor_call(cam, pad, enum_frame_size, NULL, &fse);
1494 if (fse.min_width == fse.max_width &&
1495 fse.min_height == fse.max_height) {
1496 sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1497 sizes->discrete.width = fse.min_width;
1498 sizes->discrete.height = fse.min_height;
1501 sizes->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1502 sizes->stepwise.min_width = fse.min_width;
1503 sizes->stepwise.max_width = fse.max_width;
1504 sizes->stepwise.min_height = fse.min_height;
1505 sizes->stepwise.max_height = fse.max_height;
1506 sizes->stepwise.step_width = 1;
1507 sizes->stepwise.step_height = 1;
1511 static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1512 struct v4l2_frmivalenum *interval)
1514 struct mcam_camera *cam = video_drvdata(filp);
1515 struct mcam_format_struct *f;
1516 struct v4l2_subdev_frame_interval_enum fie = {
1517 .index = interval->index,
1518 .width = interval->width,
1519 .height = interval->height,
1520 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1524 f = mcam_find_format(interval->pixel_format);
1525 if (f->pixelformat != interval->pixel_format)
1527 fie.code = f->mbus_code;
1528 ret = sensor_call(cam, pad, enum_frame_interval, NULL, &fie);
1531 interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1532 interval->discrete = fie.interval;
1536 #ifdef CONFIG_VIDEO_ADV_DEBUG
1537 static int mcam_vidioc_g_register(struct file *file, void *priv,
1538 struct v4l2_dbg_register *reg)
1540 struct mcam_camera *cam = video_drvdata(file);
1542 if (reg->reg > cam->regs_size - 4)
1544 reg->val = mcam_reg_read(cam, reg->reg);
1549 static int mcam_vidioc_s_register(struct file *file, void *priv,
1550 const struct v4l2_dbg_register *reg)
1552 struct mcam_camera *cam = video_drvdata(file);
1554 if (reg->reg > cam->regs_size - 4)
1556 mcam_reg_write(cam, reg->reg, reg->val);
1561 static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1562 .vidioc_querycap = mcam_vidioc_querycap,
1563 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1564 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1565 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1566 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1567 .vidioc_enum_input = mcam_vidioc_enum_input,
1568 .vidioc_g_input = mcam_vidioc_g_input,
1569 .vidioc_s_input = mcam_vidioc_s_input,
1570 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1571 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1572 .vidioc_querybuf = vb2_ioctl_querybuf,
1573 .vidioc_qbuf = vb2_ioctl_qbuf,
1574 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1575 .vidioc_expbuf = vb2_ioctl_expbuf,
1576 .vidioc_streamon = vb2_ioctl_streamon,
1577 .vidioc_streamoff = vb2_ioctl_streamoff,
1578 .vidioc_g_parm = mcam_vidioc_g_parm,
1579 .vidioc_s_parm = mcam_vidioc_s_parm,
1580 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1581 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1582 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1583 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1584 #ifdef CONFIG_VIDEO_ADV_DEBUG
1585 .vidioc_g_register = mcam_vidioc_g_register,
1586 .vidioc_s_register = mcam_vidioc_s_register,
1590 /* ---------------------------------------------------------------------- */
1592 * Our various file operations.
1594 static int mcam_v4l_open(struct file *filp)
1596 struct mcam_camera *cam = video_drvdata(filp);
1599 mutex_lock(&cam->s_mutex);
1600 ret = v4l2_fh_open(filp);
1603 if (v4l2_fh_is_singular_file(filp)) {
1604 ret = mcam_ctlr_power_up(cam);
1607 __mcam_cam_reset(cam);
1608 mcam_set_config_needed(cam, 1);
1611 mutex_unlock(&cam->s_mutex);
1613 v4l2_fh_release(filp);
1618 static int mcam_v4l_release(struct file *filp)
1620 struct mcam_camera *cam = video_drvdata(filp);
1623 mutex_lock(&cam->s_mutex);
1624 last_open = v4l2_fh_is_singular_file(filp);
1625 _vb2_fop_release(filp, NULL);
1627 mcam_disable_mipi(cam);
1628 mcam_ctlr_power_down(cam);
1629 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1630 mcam_free_dma_bufs(cam);
1633 mutex_unlock(&cam->s_mutex);
1637 static const struct v4l2_file_operations mcam_v4l_fops = {
1638 .owner = THIS_MODULE,
1639 .open = mcam_v4l_open,
1640 .release = mcam_v4l_release,
1641 .read = vb2_fop_read,
1642 .poll = vb2_fop_poll,
1643 .mmap = vb2_fop_mmap,
1644 .unlocked_ioctl = video_ioctl2,
1649 * This template device holds all of those v4l2 methods; we
1650 * clone it for specific real devices.
1652 static struct video_device mcam_v4l_template = {
1654 .fops = &mcam_v4l_fops,
1655 .ioctl_ops = &mcam_v4l_ioctl_ops,
1656 .release = video_device_release_empty,
1659 /* ---------------------------------------------------------------------- */
1661 * Interrupt handler stuff
1663 static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1666 * Basic frame housekeeping.
1668 set_bit(frame, &cam->flags);
1669 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1670 cam->next_buf = frame;
1671 cam->buf_seq[frame] = cam->sequence++;
1672 cam->frame_state.frames++;
1674 * "This should never happen"
1676 if (cam->state != S_STREAMING)
1679 * Process the frame and set up the next one.
1681 cam->frame_complete(cam, frame);
1686 * The interrupt handler; this needs to be called from the
1687 * platform irq handler with the lock held.
1689 int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1691 unsigned int frame, handled = 0;
1693 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1695 * Handle any frame completions. There really should
1696 * not be more than one of these, or we have fallen
1699 * When running in S/G mode, the frame number lacks any
1700 * real meaning - there's only one descriptor array - but
1701 * the controller still picks a different one to signal
1704 for (frame = 0; frame < cam->nbufs; frame++)
1705 if (irqs & (IRQ_EOF0 << frame) &&
1706 test_bit(CF_FRAME_SOF0 + frame, &cam->flags)) {
1707 mcam_frame_complete(cam, frame);
1709 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1710 if (cam->buffer_mode == B_DMA_sg)
1714 * If a frame starts, note that we have DMA active. This
1715 * code assumes that we won't get multiple frame interrupts
1716 * at once; may want to rethink that.
1718 for (frame = 0; frame < cam->nbufs; frame++) {
1719 if (irqs & (IRQ_SOF0 << frame)) {
1720 set_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1721 handled = IRQ_HANDLED;
1725 if (handled == IRQ_HANDLED) {
1726 set_bit(CF_DMA_ACTIVE, &cam->flags);
1727 if (cam->buffer_mode == B_DMA_sg)
1728 mcam_ctlr_stop(cam);
1733 /* ---------------------------------------------------------------------- */
1735 * Registration and such.
1737 static struct ov7670_config sensor_cfg = {
1739 * Exclude QCIF mode, because it only captures a tiny portion
1747 int mccic_register(struct mcam_camera *cam)
1749 struct i2c_board_info ov7670_info = {
1752 .platform_data = &sensor_cfg,
1757 * Validate the requested buffer mode.
1759 if (buffer_mode >= 0)
1760 cam->buffer_mode = buffer_mode;
1761 if (cam->buffer_mode == B_DMA_sg &&
1762 cam->chip_id == MCAM_CAFE) {
1763 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1764 "attempting vmalloc mode instead\n");
1765 cam->buffer_mode = B_vmalloc;
1767 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1768 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1775 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1779 mutex_init(&cam->s_mutex);
1780 cam->state = S_NOTREADY;
1781 mcam_set_config_needed(cam, 1);
1782 cam->pix_format = mcam_def_pix_format;
1783 cam->mbus_code = mcam_def_mbus_code;
1784 mcam_ctlr_init(cam);
1787 * Get the v4l2 setup done.
1789 ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10);
1791 goto out_unregister;
1792 cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler;
1795 * Try to find the sensor.
1797 sensor_cfg.clock_speed = cam->clock_speed;
1798 sensor_cfg.use_smbus = cam->use_smbus;
1799 cam->sensor_addr = ov7670_info.addr;
1800 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
1801 cam->i2c_adapter, &ov7670_info, NULL);
1802 if (cam->sensor == NULL) {
1804 goto out_unregister;
1807 ret = mcam_cam_init(cam);
1809 goto out_unregister;
1811 ret = mcam_setup_vb2(cam);
1813 goto out_unregister;
1815 mutex_lock(&cam->s_mutex);
1816 cam->vdev = mcam_v4l_template;
1817 cam->vdev.v4l2_dev = &cam->v4l2_dev;
1818 cam->vdev.lock = &cam->s_mutex;
1819 cam->vdev.queue = &cam->vb_queue;
1820 video_set_drvdata(&cam->vdev, cam);
1821 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1823 mutex_unlock(&cam->s_mutex);
1824 goto out_unregister;
1828 * If so requested, try to get our DMA buffers now.
1830 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
1831 if (mcam_alloc_dma_bufs(cam, 1))
1832 cam_warn(cam, "Unable to alloc DMA buffers at load"
1833 " will try again later.");
1836 mutex_unlock(&cam->s_mutex);
1840 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1841 v4l2_device_unregister(&cam->v4l2_dev);
1846 void mccic_shutdown(struct mcam_camera *cam)
1849 * If we have no users (and we really, really should have no
1850 * users) the device will already be powered down. Trying to
1851 * take it down again will wedge the machine, which is frowned
1854 if (!list_empty(&cam->vdev.fh_list)) {
1855 cam_warn(cam, "Removing a device with users!\n");
1856 mcam_ctlr_power_down(cam);
1858 if (cam->buffer_mode == B_vmalloc)
1859 mcam_free_dma_bufs(cam);
1860 video_unregister_device(&cam->vdev);
1861 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1862 v4l2_device_unregister(&cam->v4l2_dev);
1870 void mccic_suspend(struct mcam_camera *cam)
1872 mutex_lock(&cam->s_mutex);
1873 if (!list_empty(&cam->vdev.fh_list)) {
1874 enum mcam_state cstate = cam->state;
1876 mcam_ctlr_stop_dma(cam);
1877 mcam_ctlr_power_down(cam);
1878 cam->state = cstate;
1880 mutex_unlock(&cam->s_mutex);
1883 int mccic_resume(struct mcam_camera *cam)
1887 mutex_lock(&cam->s_mutex);
1888 if (!list_empty(&cam->vdev.fh_list)) {
1889 ret = mcam_ctlr_power_up(cam);
1891 mutex_unlock(&cam->s_mutex);
1894 __mcam_cam_reset(cam);
1896 mcam_ctlr_power_down(cam);
1898 mutex_unlock(&cam->s_mutex);
1900 set_bit(CF_CONFIG_NEEDED, &cam->flags);
1901 if (cam->state == S_STREAMING) {
1903 * If there was a buffer in the DMA engine at suspend
1904 * time, put it back on the queue or we'll forget about it.
1906 if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
1907 list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
1908 ret = mcam_read_setup(cam);
1912 #endif /* CONFIG_PM */